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author | Rob Purchase <shotofadds@rockbox.org> | 2008-01-14 22:04:48 +0000 |
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committer | Rob Purchase <shotofadds@rockbox.org> | 2008-01-14 22:04:48 +0000 |
commit | 47ea030e2e68a51f91a2c2302b7ea4d3ee1a2a07 (patch) | |
tree | 0a48ce653e22ec9a2673474f718217d9659e0c6b /firmware/app.lds | |
parent | b30ca8ca5ab6c8ea27b8fe1f5fb38ebad09b7e62 (diff) | |
download | rockbox-47ea030e2e68a51f91a2c2302b7ea4d3ee1a2a07.tar.gz rockbox-47ea030e2e68a51f91a2c2302b7ea4d3ee1a2a07.zip |
Initial Cowon D2 commit:
* bootloader test program (basic LCD & button drivers, reads touchscreen)
* work-in-progress stubs for main build
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16090 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/app.lds')
-rw-r--r-- | firmware/app.lds | 111 |
1 files changed, 110 insertions, 1 deletions
diff --git a/firmware/app.lds b/firmware/app.lds index 9b83537dfe..c5c4e6e30e 100644 --- a/firmware/app.lds +++ b/firmware/app.lds | |||
@@ -13,6 +13,8 @@ INPUT(target/arm/crt0-pp.o) | |||
13 | INPUT(target/arm/tms320dm320/crt0.o) | 13 | INPUT(target/arm/tms320dm320/crt0.o) |
14 | #elif CONFIG_CPU==S3C2440 | 14 | #elif CONFIG_CPU==S3C2440 |
15 | INPUT(target/arm/s3c2440/crt0.o) | 15 | INPUT(target/arm/s3c2440/crt0.o) |
16 | #elif defined(CPU_TCC780X) | ||
17 | INPUT(target/arm/tcc780x/crt0.o) | ||
16 | #elif CONFIG_CPU == PNX0101 | 18 | #elif CONFIG_CPU == PNX0101 |
17 | INPUT(target/arm/pnx0101/crt0-pnx0101.o) | 19 | INPUT(target/arm/pnx0101/crt0-pnx0101.o) |
18 | #elif CONFIG_CPU == IMX31L | 20 | #elif CONFIG_CPU == IMX31L |
@@ -75,6 +77,14 @@ INPUT(target/sh/crt0.o) | |||
75 | #define DRAMORIG (0x0 + STUBOFFSET) | 77 | #define DRAMORIG (0x0 + STUBOFFSET) |
76 | #define IRAMORIG 0x1FFFC000 | 78 | #define IRAMORIG 0x1FFFC000 |
77 | #define IRAMSIZE 0x4000 | 79 | #define IRAMSIZE 0x4000 |
80 | #elif defined(CPU_TCC780X) | ||
81 | #define DRAMORIG 0x20000000 + STUBOFFSET | ||
82 | #define ITCMORIG 0x00000000 | ||
83 | #define ITCMSIZE 0x1000 | ||
84 | #define DTCMORIG 0xA0000000 | ||
85 | #define DTCMSIZE 0x2000 | ||
86 | #define SRAMORIG 0x10000000 | ||
87 | #define SRAMSIZE 0xc000 | ||
78 | #else | 88 | #else |
79 | #define DRAMORIG 0x09000000 + STUBOFFSET | 89 | #define DRAMORIG 0x09000000 + STUBOFFSET |
80 | #define IRAMORIG 0x0f000000 | 90 | #define IRAMORIG 0x0f000000 |
@@ -90,7 +100,12 @@ INPUT(target/sh/crt0.o) | |||
90 | MEMORY | 100 | MEMORY |
91 | { | 101 | { |
92 | DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE | 102 | DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE |
93 | #if CONFIG_CPU != S3C2440 | 103 | #if defined(CPU_TCC780X) |
104 | /* Seperate data & instruction TCMs plus SRAM. */ | ||
105 | ITCM : ORIGIN = ITCMORIG, LENGTH = ITCMSIZE | ||
106 | DTCM : ORIGIN = DTCMORIG, LENGTH = DTCMSIZE | ||
107 | SRAM : ORIGIN = SRAMORIG, LENGTH = SRAMSIZE | ||
108 | #elif CONFIG_CPU != S3C2440 | ||
94 | IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE | 109 | IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE |
95 | #endif | 110 | #endif |
96 | #if CONFIG_CPU==PNX0101 | 111 | #if CONFIG_CPU==PNX0101 |
@@ -187,6 +202,100 @@ SECTIONS | |||
187 | _end = .; | 202 | _end = .; |
188 | } > DRAM | 203 | } > DRAM |
189 | 204 | ||
205 | #elif defined(CPU_TCC780X) | ||
206 | .text : | ||
207 | { | ||
208 | loadaddress = .; | ||
209 | _loadaddress = .; | ||
210 | . = ALIGN(0x200); | ||
211 | *(.init.text) | ||
212 | *(.text*) | ||
213 | *(.glue_7) | ||
214 | *(.glue_7t) | ||
215 | . = ALIGN(0x4); | ||
216 | } > DRAM | ||
217 | |||
218 | .rodata : | ||
219 | { | ||
220 | *(.rodata) /* problems without this, dunno why */ | ||
221 | *(.rodata*) | ||
222 | *(.rodata.str1.1) | ||
223 | *(.rodata.str1.4) | ||
224 | . = ALIGN(0x4); | ||
225 | |||
226 | /* Pseudo-allocate the copies of the data sections */ | ||
227 | _datacopy = .; | ||
228 | } > DRAM | ||
229 | |||
230 | /* TRICK ALERT! For RAM execution, we put the .data section at the | ||
231 | same load address as the copy. Thus, we don't waste extra RAM | ||
232 | when we don't actually need the copy. */ | ||
233 | .data : AT ( _datacopy ) | ||
234 | { | ||
235 | _datastart = .; | ||
236 | *(.data*) | ||
237 | . = ALIGN(0x4); | ||
238 | _dataend = .; | ||
239 | } > DRAM | ||
240 | |||
241 | /DISCARD/ : | ||
242 | { | ||
243 | *(.eh_frame) | ||
244 | } | ||
245 | |||
246 | .vectors ITCMORIG : | ||
247 | { | ||
248 | _vectorsstart = .; | ||
249 | *(.vectors); | ||
250 | _vectorsend = .; | ||
251 | } > ITCM AT> DRAM | ||
252 | |||
253 | _vectorscopy = LOADADDR(.vectors); | ||
254 | |||
255 | .itcm : | ||
256 | { | ||
257 | _itcmstart = .; | ||
258 | *(.icode) | ||
259 | _itcmend = .; | ||
260 | } > ITCM AT> DRAM | ||
261 | |||
262 | _itcmcopy = LOADADDR(.itcm); | ||
263 | |||
264 | .dtcm : | ||
265 | { | ||
266 | _dtcmstart = .; | ||
267 | *(.irodata) | ||
268 | *(.idata) | ||
269 | _dtcmend = .; | ||
270 | } > DTCM AT> DRAM | ||
271 | |||
272 | _dtcmcopy = LOADADDR(.dtcm); | ||
273 | |||
274 | .ibss (NOLOAD) : | ||
275 | { | ||
276 | _iedata = .; | ||
277 | *(.ibss) | ||
278 | . = ALIGN(0x4); | ||
279 | _iend = .; | ||
280 | } > SRAM | ||
281 | |||
282 | .stack : | ||
283 | { | ||
284 | *(.stack) | ||
285 | stackbegin = .; | ||
286 | . += 0x2000; | ||
287 | stackend = .; | ||
288 | } > SRAM | ||
289 | |||
290 | .bss : | ||
291 | { | ||
292 | _edata = .; | ||
293 | *(.bss*) | ||
294 | *(COMMON) | ||
295 | . = ALIGN(0x4); | ||
296 | _end = .; | ||
297 | } > DRAM | ||
298 | |||
190 | #elif CONFIG_CPU==S3C2440 | 299 | #elif CONFIG_CPU==S3C2440 |
191 | .text : | 300 | .text : |
192 | { | 301 | { |