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author | Solomon Peachy <pizza@shaftnet.org> | 2020-07-15 19:40:55 -0400 |
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committer | Solomon Peachy <pizza@shaftnet.org> | 2020-07-24 21:20:13 +0000 |
commit | 092c340a2062fa98b7387fc5fd63578ddae7d0b6 (patch) | |
tree | 98ec96946eeb2ae709cb0528cc6998e21bb9b290 /apps/plugins/fractals/cpu_sh7043.h | |
parent | 17f7cc92c258bc456a27c3e7c5a19c9409851879 (diff) | |
download | rockbox-092c340a2062fa98b7387fc5fd63578ddae7d0b6.tar.gz rockbox-092c340a2062fa98b7387fc5fd63578ddae7d0b6.zip |
[1/4] Remove SH support and all archos targets
This removes all code specific to SH targets
Change-Id: I7980523785d2596e65c06430f4638eec74a06061
Diffstat (limited to 'apps/plugins/fractals/cpu_sh7043.h')
-rw-r--r-- | apps/plugins/fractals/cpu_sh7043.h | 96 |
1 files changed, 0 insertions, 96 deletions
diff --git a/apps/plugins/fractals/cpu_sh7043.h b/apps/plugins/fractals/cpu_sh7043.h deleted file mode 100644 index 0d773432a8..0000000000 --- a/apps/plugins/fractals/cpu_sh7043.h +++ /dev/null | |||
@@ -1,96 +0,0 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2009 Tomer Shalev | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #ifndef _CPU_SH7043_H | ||
23 | #define _CPU_SH7043_H | ||
24 | |||
25 | inline static short muls16_asr10(short a, short b) | ||
26 | { | ||
27 | short r; | ||
28 | asm ( | ||
29 | "muls %[a],%[b] \n" | ||
30 | "sts macl,%[r] \n" | ||
31 | "shlr8 %[r] \n" | ||
32 | "shlr2 %[r] \n" | ||
33 | : /* outputs */ | ||
34 | [r]"=r"(r) | ||
35 | : /* inputs */ | ||
36 | [a]"r"(a), | ||
37 | [b]"r"(b) | ||
38 | ); | ||
39 | return r; | ||
40 | } | ||
41 | |||
42 | inline static long muls32_asr26(long a, long b) | ||
43 | { | ||
44 | long r, t1, t2, t3; | ||
45 | asm ( | ||
46 | /* Signed 32bit * 32bit -> 64bit multiplication. | ||
47 | Notation: xxab * xxcd, where each letter represents 16 bits. | ||
48 | xx is the 64 bit sign extension. */ | ||
49 | "swap.w %[a],%[t1] \n" /* t1 = ba */ | ||
50 | "mulu %[t1],%[b] \n" /* a * d */ | ||
51 | "swap.w %[b],%[t3] \n" /* t3 = dc */ | ||
52 | "sts macl,%[t2] \n" /* t2 = a * d */ | ||
53 | "mulu %[t1],%[t3] \n" /* a * c */ | ||
54 | "sts macl,%[r] \n" /* hi = a * c */ | ||
55 | "mulu %[a],%[t3] \n" /* b * c */ | ||
56 | "clrt \n" | ||
57 | "sts macl,%[t3] \n" /* t3 = b * c */ | ||
58 | "addc %[t2],%[t3] \n" /* t3 += t2, carry -> t2 */ | ||
59 | "movt %[t2] \n" | ||
60 | "mulu %[a],%[b] \n" /* b * d */ | ||
61 | "mov %[t3],%[t1] \n" /* t1t3 = t2t3 << 16 */ | ||
62 | "xtrct %[t2],%[t1] \n" | ||
63 | "shll16 %[t3] \n" | ||
64 | "sts macl,%[t2] \n" /* lo = b * d */ | ||
65 | "clrt \n" /* hi.lo += t1t3 */ | ||
66 | "addc %[t3],%[t2] \n" | ||
67 | "addc %[t1],%[r] \n" | ||
68 | "cmp/pz %[a] \n" /* ab >= 0 ? */ | ||
69 | "bt 1f \n" | ||
70 | "sub %[b],%[r] \n" /* no: hi -= cd (sign extension of ab is -1) */ | ||
71 | "1: \n" | ||
72 | "cmp/pz %[b] \n" /* cd >= 0 ? */ | ||
73 | "bt 2f \n" | ||
74 | "sub %[a],%[r] \n" /* no: hi -= ab (sign extension of cd is -1) */ | ||
75 | "2: \n" | ||
76 | /* Shift right by 26 and return low 32 bits */ | ||
77 | "shll2 %[r] \n" /* hi <<= 6 */ | ||
78 | "shll2 %[r] \n" | ||
79 | "shll2 %[r] \n" | ||
80 | "shlr16 %[t2] \n" /* (unsigned)lo >>= 26 */ | ||
81 | "shlr8 %[t2] \n" | ||
82 | "shlr2 %[t2] \n" | ||
83 | "or %[t2],%[r] \n" /* combine result */ | ||
84 | : /* outputs */ | ||
85 | [r] "=&r"(r), | ||
86 | [t1]"=&r"(t1), | ||
87 | [t2]"=&r"(t2), | ||
88 | [t3]"=&r"(t3) | ||
89 | : /* inputs */ | ||
90 | [a] "r" (a), | ||
91 | [b] "r" (b) | ||
92 | ); | ||
93 | return r; | ||
94 | } | ||
95 | |||
96 | #endif | ||