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| author | Aidan MacDonald <amachronic@protonmail.com> | 2022-03-26 17:49:09 +0000 |
|---|---|---|
| committer | Aidan MacDonald <amachronic@protonmail.com> | 2022-04-01 12:08:41 -0400 |
| commit | 98f762316f0b065e9e4ce0ed8027eb0cc378eb32 (patch) | |
| tree | 084b14cfd35aa60751529ef946b2e484ff11c4c5 /apps/cuesheet.c | |
| parent | de285741bfe5094d5f67b9244378359cb94b66ee (diff) | |
| download | rockbox-98f762316f0b065e9e4ce0ed8027eb0cc378eb32.tar.gz rockbox-98f762316f0b065e9e4ce0ed8027eb0cc378eb32.zip | |
system: update MEM_ALIGN_ATTR for targets with CPU cachesbootloader_erosq_v1
MEM_ALIGN_ATTR should take advantage of cache line alignment on
all native CPUs which define it, not just ARM CPUs. (This could
arguably be done for hosted targets too, but we don't necessarily
know the size of a cache line there.)
Change-Id: Ife9302105ea57388afd55ce31da848b00b5b1b25
Diffstat (limited to 'apps/cuesheet.c')
0 files changed, 0 insertions, 0 deletions