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authorJens Arnold <amiconn@rockbox.org>2009-07-17 09:17:54 +0000
committerJens Arnold <amiconn@rockbox.org>2009-07-17 09:17:54 +0000
commit82dc91a1028b702151e5735fb383356028d7bbae (patch)
tree2fa2d7a053c9d064b0531652954e4a9acae531ec /apps/codecs/demac/libdemac/predictor-arm.S
parent867eb5feb3d8aaa92cdd647018a4e3ea49bec975 (diff)
downloadrockbox-82dc91a1028b702151e5735fb383356028d7bbae.tar.gz
rockbox-82dc91a1028b702151e5735fb383356028d7bbae.zip
Don't use ldrd/strd on ARMv5 since not all revisions support them and the gain from using them is minimal (basically code size only).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21916 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'apps/codecs/demac/libdemac/predictor-arm.S')
-rw-r--r--apps/codecs/demac/libdemac/predictor-arm.S8
1 files changed, 4 insertions, 4 deletions
diff --git a/apps/codecs/demac/libdemac/predictor-arm.S b/apps/codecs/demac/libdemac/predictor-arm.S
index f1d3bc3739..28808c8e96 100644
--- a/apps/codecs/demac/libdemac/predictor-arm.S
+++ b/apps/codecs/demac/libdemac/predictor-arm.S
@@ -61,13 +61,13 @@ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
61@ Registers must start with an even register, and must be consecutive. 61@ Registers must start with an even register, and must be consecutive.
62 62
63.macro LDR2OFS reg1, reg2, base, offset 63.macro LDR2OFS reg1, reg2, base, offset
64#if ARM_ARCH >= 5 64#if ARM_ARCH >= 6
65 ldrd \reg1, [\base, \offset] 65 ldrd \reg1, [\base, \offset]
66#else /* ARM_ARCH < 5 */ 66#else /* ARM_ARCH < 6 */
67#ifdef CPU_ARM7TDMI 67#ifdef CPU_ARM7TDMI
68 add \reg1, \base, \offset 68 add \reg1, \base, \offset
69 ldmia \reg1, {\reg1, \reg2} 69 ldmia \reg1, {\reg1, \reg2}
70#else 70#else /* ARM9 (v4 and v5) is faster this way */
71 ldr \reg1, [\base, \offset] 71 ldr \reg1, [\base, \offset]
72 ldr \reg2, [\base, \offset+4] 72 ldr \reg2, [\base, \offset+4]
73#endif 73#endif
@@ -78,7 +78,7 @@ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
78@ Registers must start with an even register, and must be consecutive. 78@ Registers must start with an even register, and must be consecutive.
79 79
80.macro STR2OFS reg1, reg2, base, offset 80.macro STR2OFS reg1, reg2, base, offset
81#if ARM_ARCH >= 5 81#if ARM_ARCH >= 6
82 strd \reg1, [\base, \offset] 82 strd \reg1, [\base, \offset]
83#else 83#else
84 str \reg1, [\base, \offset] 84 str \reg1, [\base, \offset]