diff options
| author | Michael Sevakis <jethead71@rockbox.org> | 2007-10-07 05:59:38 +0000 |
|---|---|---|
| committer | Michael Sevakis <jethead71@rockbox.org> | 2007-10-07 05:59:38 +0000 |
| commit | fc8bc5ca358eecf5d368f0482fb20c82da51e2f7 (patch) | |
| tree | 3d9fc756e2198d5b6514f7378fa60bdf0f941a69 | |
| parent | 51967f4856b50943ca76e38e32c3b27249dc2ed0 (diff) | |
| download | rockbox-fc8bc5ca358eecf5d368f0482fb20c82da51e2f7.tar.gz rockbox-fc8bc5ca358eecf5d368f0482fb20c82da51e2f7.zip | |
Oops. Correct reversed DSP mode A/B bits for WM8731/21.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15008 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/export/wm8721.h | 4 | ||||
| -rw-r--r-- | firmware/export/wm8731.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/firmware/export/wm8721.h b/firmware/export/wm8721.h index 223c3e1a0e..bb4c8b01d3 100644 --- a/firmware/export/wm8721.h +++ b/firmware/export/wm8721.h | |||
| @@ -73,8 +73,8 @@ extern void audiohw_set_sample_rate(int sampling_control); | |||
| 73 | #define AINTFCE_IWL_MASK (3 << 2) | 73 | #define AINTFCE_IWL_MASK (3 << 2) |
| 74 | #define AINTFCE_LRP_I2S_RLO (0 << 4) | 74 | #define AINTFCE_LRP_I2S_RLO (0 << 4) |
| 75 | #define AINTFCE_LRP_I2S_RHI (1 << 4) | 75 | #define AINTFCE_LRP_I2S_RHI (1 << 4) |
| 76 | #define AINTFCE_DSP_MODE_A (0 << 4) | 76 | #define AINTFCE_DSP_MODE_B (0 << 4) |
| 77 | #define AINTFCE_DSP_MODE_B (1 << 4) | 77 | #define AINTFCE_DSP_MODE_A (1 << 4) |
| 78 | #define AINTFCE_LRSWAP (1 << 5) | 78 | #define AINTFCE_LRSWAP (1 << 5) |
| 79 | #define AINTFCE_MS (1 << 6) | 79 | #define AINTFCE_MS (1 << 6) |
| 80 | #define AINTFCE_BCLKINV (1 << 7) | 80 | #define AINTFCE_BCLKINV (1 << 7) |
diff --git a/firmware/export/wm8731.h b/firmware/export/wm8731.h index 3fc6bc7a5a..5e94a4e9a6 100644 --- a/firmware/export/wm8731.h +++ b/firmware/export/wm8731.h | |||
| @@ -105,8 +105,8 @@ extern void audiohw_set_monitor(int enable); | |||
| 105 | #define AINTFCE_IWL_MASK (3 << 2) | 105 | #define AINTFCE_IWL_MASK (3 << 2) |
| 106 | #define AINTFCE_LRP_I2S_RLO (0 << 4) | 106 | #define AINTFCE_LRP_I2S_RLO (0 << 4) |
| 107 | #define AINTFCE_LRP_I2S_RHI (1 << 4) | 107 | #define AINTFCE_LRP_I2S_RHI (1 << 4) |
| 108 | #define AINTFCE_DSP_MODE_A (0 << 4) | 108 | #define AINTFCE_DSP_MODE_B (0 << 4) |
| 109 | #define AINTFCE_DSP_MODE_B (1 << 4) | 109 | #define AINTFCE_DSP_MODE_A (1 << 4) |
| 110 | #define AINTFCE_LRSWAP (1 << 5) | 110 | #define AINTFCE_LRSWAP (1 << 5) |
| 111 | #define AINTFCE_MS (1 << 6) | 111 | #define AINTFCE_MS (1 << 6) |
| 112 | #define AINTFCE_BCLKINV (1 << 7) | 112 | #define AINTFCE_BCLKINV (1 << 7) |