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author | Aidan MacDonald <amachronic@protonmail.com> | 2021-03-04 19:38:14 +0000 |
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committer | Aidan MacDonald <amachronic@protonmail.com> | 2021-03-04 19:39:28 +0000 |
commit | fb99d890a8ed5da627885da62f85c9f5bcd08d47 (patch) | |
tree | 756d7dbc0887801070abc77a201bc00aa1031e58 | |
parent | cbace906c6c17bf4912d838385d7c1ee7fb81b25 (diff) | |
download | rockbox-fb99d890a8ed5da627885da62f85c9f5bcd08d47.tar.gz rockbox-fb99d890a8ed5da627885da62f85c9f5bcd08d47.zip |
Fix typo in MIPS cache discard
Change-Id: I6a06e5f3098324d985bd59322755cd68122ec0bf
-rw-r--r-- | firmware/target/mips/mmu-mips.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c index 4f2de528bd..2daed5ed9e 100644 --- a/firmware/target/mips/mmu-mips.c +++ b/firmware/target/mips/mmu-mips.c | |||
@@ -234,7 +234,7 @@ void discard_dcache_range(const void *base, unsigned int size) | |||
234 | cacheline and shrink down the region to discard. */ | 234 | cacheline and shrink down the region to discard. */ |
235 | if (ptr != end && (end !=((char*)base + size))) { | 235 | if (ptr != end && (end !=((char*)base + size))) { |
236 | end -= CACHEALIGN_SIZE; | 236 | end -= CACHEALIGN_SIZE; |
237 | __CACHE_OP(DCHitWBInv, ptr); | 237 | __CACHE_OP(DCHitWBInv, end); |
238 | } | 238 | } |
239 | 239 | ||
240 | /* Finally, discard whatever is left */ | 240 | /* Finally, discard whatever is left */ |