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authorMarcin Bukat <marcin.bukat@gmail.com>2011-07-18 22:30:53 +0000
committerMarcin Bukat <marcin.bukat@gmail.com>2011-07-18 22:30:53 +0000
commitf1c7fba5a474ebdfd1e162459df1a513911da1b7 (patch)
tree481ea3c78f83a968dc5861b2c55c493254e9bfb5
parent64b5f1c625f500e8837147f31997b7671e724462 (diff)
downloadrockbox-f1c7fba5a474ebdfd1e162459df1a513911da1b7.tar.gz
rockbox-f1c7fba5a474ebdfd1e162459df1a513911da1b7.zip
rk27xx - add missing interrupt source
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30166 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/target/arm/rk27xx/system-rk27xx.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/firmware/target/arm/rk27xx/system-rk27xx.c b/firmware/target/arm/rk27xx/system-rk27xx.c
index 67024a5fea..724273b61a 100644
--- a/firmware/target/arm/rk27xx/system-rk27xx.c
+++ b/firmware/target/arm/rk27xx/system-rk27xx.c
@@ -52,6 +52,7 @@ default_interrupt(INT_UHC);
52default_interrupt(INT_PWM0); 52default_interrupt(INT_PWM0);
53default_interrupt(INT_PWM1); 53default_interrupt(INT_PWM1);
54default_interrupt(INT_PWM2); 54default_interrupt(INT_PWM2);
55default_interrupt(INT_PWM3);
55default_interrupt(INT_ADC); 56default_interrupt(INT_ADC);
56default_interrupt(INT_GPIO1); 57default_interrupt(INT_GPIO1);
57default_interrupt(INT_VIP); 58default_interrupt(INT_VIP);
@@ -66,16 +67,16 @@ default_interrupt(INT_SW_INT3);
66static void (* const irqvector[])(void) = 67static void (* const irqvector[])(void) =
67{ 68{
68 INT_UART0,INT_UART1,INT_TIMER0,INT_TIMER1,INT_TIMER2,INT_GPIO0,INT_SW_INT0,INT_AHB0_MAILBOX, 69 INT_UART0,INT_UART1,INT_TIMER0,INT_TIMER1,INT_TIMER2,INT_GPIO0,INT_SW_INT0,INT_AHB0_MAILBOX,
69 INT_RTC,INT_SCU,INT_SD,INT_SPI,INT_HDMA,INT_A2A_BRIDGE,INT_I2C, 70 INT_RTC,INT_SCU,INT_SD,INT_SPI,INT_HDMA,INT_A2A_BRIDGE,INT_I2C,INT_I2S,
70 INT_I2S,INT_UDC,INT_UHC,INT_PWM0,INT_PWM1,INT_PWM2,INT_ADC,INT_GPIO1, 71 INT_UDC,INT_UHC,INT_PWM0,INT_PWM1,INT_PWM2,INT_PWM3,INT_ADC,INT_GPIO1,
71 INT_VIP,INT_DWDMA,INT_NANDC,INT_LCDC,INT_DSP,INT_SW_INT1,INT_SW_INT2,INT_SW_INT3 72 INT_VIP,INT_DWDMA,INT_NANDC,INT_LCDC,INT_DSP,INT_SW_INT1,INT_SW_INT2,INT_SW_INT3
72}; 73};
73 74
74static const char * const irqname[] = 75static const char * const irqname[] =
75{ 76{
76 "INT_UART0","INT_UART1","INT_TIMER0","INT_TIMER1","INT_TIMER2","INT_GPIO0","INT_SW_INT0","INT_AHB0_MAILBOX", 77 "INT_UART0","INT_UART1","INT_TIMER0","INT_TIMER1","INT_TIMER2","INT_GPIO0","INT_SW_INT0","INT_AHB0_MAILBOX",
77 "INT_RTC","INT_SCU","INT_SD","INT_SPI","INT_HDMA","INT_A2A_BRIDGE","INT_I2C", 78 "INT_RTC","INT_SCU","INT_SD","INT_SPI","INT_HDMA","INT_A2A_BRIDGE","INT_I2C","INT_I2S",
78 "INT_I2S","INT_UDC","INT_UHC","INT_PWM0","INT_PWM1","INT_PWM2","INT_ADC","INT_GPIO1", 79 "INT_UDC","INT_UHC","INT_PWM0","INT_PWM1","INT_PWM2","INT_PWM3","INT_ADC","INT_GPIO1",
79 "INT_VIP","INT_DWDMA","INT_NANDC","INT_LCDC","INT_DSP","INT_SW_INT1","INT_SW_INT2","INT_SW_INT3" 80 "INT_VIP","INT_DWDMA","INT_NANDC","INT_LCDC","INT_DSP","INT_SW_INT1","INT_SW_INT2","INT_SW_INT3"
80}; 81};
81 82