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authorRafaël Carré <rafael.carre@gmail.com>2008-12-05 14:37:28 +0000
committerRafaël Carré <rafael.carre@gmail.com>2008-12-05 14:37:28 +0000
commitf07aa65117a196ecfd5ef097dc432d6f5d49c743 (patch)
tree750485cbfad9072aeddd2753645f556ee4832fe6
parentf577cd1fdbc24a3ffcd1f96204f862746b2362c5 (diff)
downloadrockbox-f07aa65117a196ecfd5ef097dc432d6f5d49c743.tar.gz
rockbox-f07aa65117a196ecfd5ef097dc432d6f5d49c743.zip
Sansa AMS: correct VIC registers usage
* Do not use |= on write only registers * Do use it in when setting kernel tick timer git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19350 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/target/arm/as3525/kernel-as3525.c2
-rw-r--r--firmware/timer.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/firmware/target/arm/as3525/kernel-as3525.c b/firmware/target/arm/as3525/kernel-as3525.c
index 3a4a067b6c..3252e5abd1 100644
--- a/firmware/target/arm/as3525/kernel-as3525.c
+++ b/firmware/target/arm/as3525/kernel-as3525.c
@@ -48,7 +48,7 @@ void tick_start(unsigned int interval_in_ms)
48 panicf("%s : interval too big", __func__); 48 panicf("%s : interval too big", __func__);
49 49
50 CGU_PERI |= CGU_TIMER2_CLOCK_ENABLE; /* enable peripheral */ 50 CGU_PERI |= CGU_TIMER2_CLOCK_ENABLE; /* enable peripheral */
51 VIC_INT_ENABLE = INTERRUPT_TIMER2; /* enable interrupt */ 51 VIC_INT_ENABLE |= INTERRUPT_TIMER2; /* enable interrupt */
52 52
53 TIMER2_LOAD = TIMER2_BGLOAD = cycles; /* timer period */ 53 TIMER2_LOAD = TIMER2_BGLOAD = cycles; /* timer period */
54 54
diff --git a/firmware/timer.c b/firmware/timer.c
index 0746b05e46..a11cd10b7e 100644
--- a/firmware/timer.c
+++ b/firmware/timer.c
@@ -357,7 +357,7 @@ void timer_unregister(void)
357 irq_disable_int(IRQ_TIMER1); 357 irq_disable_int(IRQ_TIMER1);
358#elif CONFIG_CPU == AS3525 358#elif CONFIG_CPU == AS3525
359 TIMER1_CONTROL &= 0x10; /* disable timer 1 (don't modify bit 4) */ 359 TIMER1_CONTROL &= 0x10; /* disable timer 1 (don't modify bit 4) */
360 VIC_INT_EN_CLEAR |= INTERRUPT_TIMER1; /* disable interrupt */ 360 VIC_INT_EN_CLEAR = INTERRUPT_TIMER1; /* disable interrupt */
361 CGU_PERI &= ~CGU_TIMER1_CLOCK_ENABLE; /* disable peripheral */ 361 CGU_PERI &= ~CGU_TIMER1_CLOCK_ENABLE; /* disable peripheral */
362#elif CONFIG_CPU == S3C2440 || CONFIG_CPU == DM320 362#elif CONFIG_CPU == S3C2440 || CONFIG_CPU == DM320
363 __TIMER_UNREGISTER(); 363 __TIMER_UNREGISTER();