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author | Andree Buschmann <AndreeBuschmann@t-online.de> | 2010-11-21 12:27:01 +0000 |
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committer | Andree Buschmann <AndreeBuschmann@t-online.de> | 2010-11-21 12:27:01 +0000 |
commit | eef21cb18ae4bc7cdf83830554a848e0c733a73d (patch) | |
tree | db04e994c7be9d634a49245928a99f6888e576b5 | |
parent | f54cbfa1647a1bcacb7998e0e19b17f0d1bde84a (diff) | |
download | rockbox-eef21cb18ae4bc7cdf83830554a848e0c733a73d.tar.gz rockbox-eef21cb18ae4bc7cdf83830554a848e0c733a73d.zip |
Change alignment macros to allow further performance optimization. Define the CACHEALIGN macros for all ARM CPUs, the used alignment size is derived from CACHEALIGN_BITS which has been defined for each supported ARM CPU with r28619. The default alignment size for ARM is set to 32 bytes as new -- not yet supported -- ARM CPUs will most probably need this alignment. To be able to differ between ARM and other CPUs a new macro called MEM_ALIGN_ATTR is introduced. This equals CACHEALIGN_ATTR for ARM, 16 byte alignment for Coldfire and is kept empty for other CPUs. MEM_ALIGN_ATTR is available system wide. From measurements it is expected that the usage of MEM_ALIGN_ATTR can give significant performance gain on ARM11 CPUs.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28625 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/export/system.h | 111 | ||||
-rw-r--r-- | firmware/target/arm/system-target.h | 4 |
2 files changed, 65 insertions, 50 deletions
diff --git a/firmware/export/system.h b/firmware/export/system.h index ed10c84a58..af70152299 100644 --- a/firmware/export/system.h +++ b/firmware/export/system.h | |||
@@ -309,58 +309,77 @@ static inline void cpucache_flush(void) | |||
309 | } | 309 | } |
310 | #endif | 310 | #endif |
311 | 311 | ||
312 | #ifndef CACHEALIGN_SIZE /* could be elsewhere for a particular reason */ | 312 | /* Define this, if the CPU may take advantage of cache aligment. Is enabled |
313 | * for all ARM CPUs. */ | ||
314 | #ifdef CPU_ARM | ||
315 | #define HAVE_CPU_CACHE_ALIGN | ||
316 | #endif | ||
317 | |||
318 | /* Calculate CACHEALIGN_SIZE from CACHEALIGN_BITS */ | ||
319 | #ifdef CACHEALIGN_SIZE | ||
320 | /* undefine, if defined. always calculate from CACHEALIGN_BITS */ | ||
321 | #undef CACHEALIGN_SIZE | ||
322 | #endif | ||
313 | #ifdef CACHEALIGN_BITS | 323 | #ifdef CACHEALIGN_BITS |
314 | /* 2^CACHEALIGN_BITS = the byte size */ | 324 | /* CACHEALIGN_BITS = 2 ^ CACHEALIGN_BITS */ |
315 | #define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS) | 325 | #define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS) |
326 | #else | ||
327 | /* FIXME: set to maximum known cache alignment of supported CPUs */ | ||
328 | #define CACHEALIGN_BITS 5 | ||
329 | #define CACHEALIGN_SIZE 32 | ||
330 | #endif | ||
331 | |||
332 | #ifdef HAVE_CPU_CACHE_ALIGN | ||
333 | /* Cache alignment attributes and sizes are enabled */ | ||
334 | #define CACHEALIGN_ATTR __attribute__((aligned(CACHEALIGN_SIZE))) | ||
335 | /* Aligns x up to a CACHEALIGN_SIZE boundary */ | ||
336 | #define CACHEALIGN_UP(x) \ | ||
337 | ((typeof (x))ALIGN_UP_P2((uintptr_t)(x), CACHEALIGN_BITS)) | ||
338 | /* Aligns x down to a CACHEALIGN_SIZE boundary */ | ||
339 | #define CACHEALIGN_DOWN(x) \ | ||
340 | ((typeof (x))ALIGN_DOWN_P2((uintptr_t)(x), CACHEALIGN_BITS)) | ||
341 | /* Aligns at least to the greater of size x or CACHEALIGN_SIZE */ | ||
342 | #define CACHEALIGN_AT_LEAST_ATTR(x) \ | ||
343 | __attribute__((aligned(CACHEALIGN_UP(x)))) | ||
344 | /* Aligns a buffer pointer and size to proper boundaries */ | ||
345 | #define CACHEALIGN_BUFFER(start, size) \ | ||
346 | ALIGN_BUFFER((start), (size), CACHEALIGN_SIZE) | ||
347 | #else | ||
348 | /* Cache alignment attributes and sizes are not enabled */ | ||
349 | #define CACHEALIGN_ATTR | ||
350 | #define CACHEALIGN_AT_LEAST_ATTR(x) __attribute__((aligned(x))) | ||
351 | #define CACHEALIGN_UP(x) (x) | ||
352 | #define CACHEALIGN_DOWN(x) (x) | ||
353 | /* Make no adjustments */ | ||
354 | #define CACHEALIGN_BUFFER(start, size) | ||
355 | #endif | ||
356 | |||
357 | /* Define MEM_ALIGN_ATTR which may be used to align e.g. buffers for faster | ||
358 | * access. */ | ||
359 | #if defined(CPU_ARM) | ||
360 | /* Use ARMs cache alignment. */ | ||
361 | #define MEM_ALIGN_ATTR CACHEALIGN_ATTR | ||
362 | #elif defined(CPU_COLDFIRE) | ||
363 | /* Use fixed alignment of 16 bytes. Speed up only for 'movem' in DRAM. */ | ||
364 | #define MEM_ALIGN_ATTR __attribute__((aligned(16))) | ||
316 | #else | 365 | #else |
317 | #define CACHEALIGN_SIZE 16 /* FIXME */ | 366 | /* Do nothing. */ |
367 | #define MEM_ALIGN_ATTR | ||
318 | #endif | 368 | #endif |
319 | #endif /* CACHEALIGN_SIZE */ | ||
320 | |||
321 | #ifdef PROC_NEEDS_CACHEALIGN | ||
322 | /* Cache alignment attributes and sizes are enabled */ | ||
323 | |||
324 | #define CACHEALIGN_ATTR __attribute__((aligned(CACHEALIGN_SIZE))) | ||
325 | /* Aligns x up to a CACHEALIGN_SIZE boundary */ | ||
326 | #define CACHEALIGN_UP(x) \ | ||
327 | ((typeof (x))ALIGN_UP_P2((uintptr_t)(x), CACHEALIGN_BITS)) | ||
328 | /* Aligns x down to a CACHEALIGN_SIZE boundary */ | ||
329 | #define CACHEALIGN_DOWN(x) \ | ||
330 | ((typeof (x))ALIGN_DOWN_P2((uintptr_t)(x), CACHEALIGN_BITS)) | ||
331 | /* Aligns at least to the greater of size x or CACHEALIGN_SIZE */ | ||
332 | #define CACHEALIGN_AT_LEAST_ATTR(x) \ | ||
333 | __attribute__((aligned(CACHEALIGN_UP(x)))) | ||
334 | /* Aligns a buffer pointer and size to proper boundaries */ | ||
335 | #define CACHEALIGN_BUFFER(start, size) \ | ||
336 | ALIGN_BUFFER((start), (size), CACHEALIGN_SIZE) | ||
337 | |||
338 | #else /* ndef PROC_NEEDS_CACHEALIGN */ | ||
339 | |||
340 | /* Cache alignment attributes and sizes are not enabled */ | ||
341 | #define CACHEALIGN_ATTR | ||
342 | #define CACHEALIGN_AT_LEAST_ATTR(x) \ | ||
343 | __attribute__((aligned(x))) | ||
344 | #define CACHEALIGN_UP(x) (x) | ||
345 | #define CACHEALIGN_DOWN(x) (x) | ||
346 | /* Make no adjustments */ | ||
347 | #define CACHEALIGN_BUFFER(start, size) | ||
348 | |||
349 | #endif /* PROC_NEEDS_CACHEALIGN */ | ||
350 | 369 | ||
351 | #ifdef STORAGE_WANTS_ALIGN | 370 | #ifdef STORAGE_WANTS_ALIGN |
352 | #define STORAGE_ALIGN_ATTR __attribute__((aligned(CACHEALIGN_SIZE))) | 371 | #define STORAGE_ALIGN_ATTR __attribute__((aligned(CACHEALIGN_SIZE))) |
353 | #define STORAGE_ALIGN_DOWN(x) \ | 372 | #define STORAGE_ALIGN_DOWN(x) \ |
354 | ((typeof (x))ALIGN_DOWN_P2((uintptr_t)(x), CACHEALIGN_BITS)) | 373 | ((typeof (x))ALIGN_DOWN_P2((uintptr_t)(x), CACHEALIGN_BITS)) |
355 | /* Pad a size so the buffer can be aligned later */ | 374 | /* Pad a size so the buffer can be aligned later */ |
356 | #define STORAGE_PAD(x) ((x) + CACHEALIGN_SIZE - 1) | 375 | #define STORAGE_PAD(x) ((x) + CACHEALIGN_SIZE - 1) |
357 | /* Number of bytes in the last cacheline assuming buffer of size x is aligned */ | 376 | /* Number of bytes in the last cacheline assuming buffer of size x is aligned */ |
358 | #define STORAGE_OVERLAP(x) ((x) & (CACHEALIGN_SIZE - 1)) | 377 | #define STORAGE_OVERLAP(x) ((x) & (CACHEALIGN_SIZE - 1)) |
359 | #else | 378 | #else |
360 | #define STORAGE_ALIGN_ATTR | 379 | #define STORAGE_ALIGN_ATTR |
361 | #define STORAGE_ALIGN_DOWN(x) (x) | 380 | #define STORAGE_ALIGN_DOWN(x) (x) |
362 | #define STORAGE_PAD(x) (x) | 381 | #define STORAGE_PAD(x) (x) |
363 | #define STORAGE_OVERLAP(x) 0 | 382 | #define STORAGE_OVERLAP(x) 0 |
364 | #endif | 383 | #endif |
365 | 384 | ||
366 | /* Double-cast to avoid 'dereferencing type-punned pointer will | 385 | /* Double-cast to avoid 'dereferencing type-punned pointer will |
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 1e573be291..3e3eab8f8d 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h | |||
@@ -158,10 +158,6 @@ static inline void wake_core(int core) | |||
158 | ((typeof (a))((uintptr_t)(a) | UNCACHED_BASE_ADDR)) | 158 | ((typeof (a))((uintptr_t)(a) | UNCACHED_BASE_ADDR)) |
159 | #endif /* BOOTLOADER */ | 159 | #endif /* BOOTLOADER */ |
160 | 160 | ||
161 | /* Certain data needs to be out of the way of cache line interference | ||
162 | * such as data for COP use or for use with UNCACHED_ADDR */ | ||
163 | #define PROC_NEEDS_CACHEALIGN | ||
164 | |||
165 | #if defined(CPU_PP502x) && defined(HAVE_ATA_DMA) | 161 | #if defined(CPU_PP502x) && defined(HAVE_ATA_DMA) |
166 | #define STORAGE_WANTS_ALIGN | 162 | #define STORAGE_WANTS_ALIGN |
167 | #endif | 163 | #endif |