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author | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2009-01-21 21:29:47 +0000 |
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committer | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2009-01-21 21:29:47 +0000 |
commit | e79fc8aaef541b48a84a23e6771e3ec5a2efe5ac (patch) | |
tree | 13fc36e51acf934d8f6a17a9b29778dcc95a2d84 | |
parent | 29b136b82dda3b3170589df62120705b1b954652 (diff) | |
download | rockbox-e79fc8aaef541b48a84a23e6771e3ec5a2efe5ac.tar.gz rockbox-e79fc8aaef541b48a84a23e6771e3ec5a2efe5ac.zip |
Onda VX747: disable DMA for now on NAND for performance
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19816 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c index 4a36b069f9..8c4ad40f72 100644 --- a/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c | |||
@@ -31,6 +31,8 @@ | |||
31 | #include "buffer.h" | 31 | #include "buffer.h" |
32 | #include "string.h" | 32 | #include "string.h" |
33 | 33 | ||
34 | //#define USE_DMA | ||
35 | |||
34 | /* | 36 | /* |
35 | * Standard NAND flash commands | 37 | * Standard NAND flash commands |
36 | */ | 38 | */ |
@@ -108,8 +110,10 @@ struct nand_param | |||
108 | 110 | ||
109 | static struct nand_info* chip_info = NULL; | 111 | static struct nand_info* chip_info = NULL; |
110 | static struct nand_param internal_param; | 112 | static struct nand_param internal_param; |
113 | #ifdef USE_DMA | ||
111 | static struct mutex nand_mtx; | 114 | static struct mutex nand_mtx; |
112 | static struct wakeup nand_wkup; | 115 | static struct wakeup nand_wkup; |
116 | #endif | ||
113 | static unsigned char temp_page[4096]; /* Max page size */ | 117 | static unsigned char temp_page[4096]; /* Max page size */ |
114 | 118 | ||
115 | static inline void jz_nand_wait_ready(void) | 119 | static inline void jz_nand_wait_ready(void) |
@@ -119,6 +123,8 @@ static inline void jz_nand_wait_ready(void) | |||
119 | while (!(REG_GPIO_PXPIN(2) & 0x40000000)); | 123 | while (!(REG_GPIO_PXPIN(2) & 0x40000000)); |
120 | } | 124 | } |
121 | 125 | ||
126 | #ifndef USE_DMA | ||
127 | |||
122 | static inline void jz_nand_read_buf16(void *buf, int count) | 128 | static inline void jz_nand_read_buf16(void *buf, int count) |
123 | { | 129 | { |
124 | int i; | 130 | int i; |
@@ -137,6 +143,8 @@ static inline void jz_nand_read_buf8(void *buf, int count) | |||
137 | *p++ = __nand_data8(); | 143 | *p++ = __nand_data8(); |
138 | } | 144 | } |
139 | 145 | ||
146 | #else | ||
147 | |||
140 | static void jz_nand_write_dma(void *source, unsigned int len, int bw) | 148 | static void jz_nand_write_dma(void *source, unsigned int len, int bw) |
141 | { | 149 | { |
142 | mutex_lock(&nand_mtx); | 150 | mutex_lock(&nand_mtx); |
@@ -162,6 +170,8 @@ static void jz_nand_write_dma(void *source, unsigned int len, int bw) | |||
162 | REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */ | 170 | REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */ |
163 | wakeup_wait(&nand_wkup, TIMEOUT_BLOCK); | 171 | wakeup_wait(&nand_wkup, TIMEOUT_BLOCK); |
164 | #endif | 172 | #endif |
173 | |||
174 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ | ||
165 | 175 | ||
166 | dma_disable(); | 176 | dma_disable(); |
167 | 177 | ||
@@ -177,7 +187,7 @@ static void jz_nand_read_dma(void *target, unsigned int len, int bw) | |||
177 | 187 | ||
178 | dma_enable(); | 188 | dma_enable(); |
179 | 189 | ||
180 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES; | 190 | REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES ; |
181 | REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT); | 191 | REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT); |
182 | REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)target); | 192 | REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)target); |
183 | REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 4; | 193 | REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 4; |
@@ -192,6 +202,8 @@ static void jz_nand_read_dma(void *target, unsigned int len, int bw) | |||
192 | REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */ | 202 | REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */ |
193 | wakeup_wait(&nand_wkup, TIMEOUT_BLOCK); | 203 | wakeup_wait(&nand_wkup, TIMEOUT_BLOCK); |
194 | #endif | 204 | #endif |
205 | |||
206 | //REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ | ||
195 | 207 | ||
196 | dma_disable(); | 208 | dma_disable(); |
197 | 209 | ||
@@ -215,12 +227,21 @@ void DMA_CALLBACK(DMA_NAND_CHANNEL)(void) | |||
215 | wakeup_signal(&nand_wkup); | 227 | wakeup_signal(&nand_wkup); |
216 | } | 228 | } |
217 | 229 | ||
230 | #endif | ||
231 | |||
218 | static inline void jz_nand_read_buf(void *buf, int count, int bw) | 232 | static inline void jz_nand_read_buf(void *buf, int count, int bw) |
219 | { | 233 | { |
234 | #ifdef USE_DMA | ||
220 | if (bw == 8) | 235 | if (bw == 8) |
221 | jz_nand_read_dma(buf, count, 8); | 236 | jz_nand_read_dma(buf, count, 8); |
222 | else | 237 | else |
223 | jz_nand_read_dma(buf, count, 16); | 238 | jz_nand_read_dma(buf, count, 16); |
239 | #else | ||
240 | if (bw == 8) | ||
241 | jz_nand_read_buf8(buf, count); | ||
242 | else | ||
243 | jz_nand_read_buf16(buf, count); | ||
244 | #endif | ||
224 | } | 245 | } |
225 | 246 | ||
226 | /* | 247 | /* |
@@ -495,8 +516,11 @@ int nand_init(void) | |||
495 | if(!inited) | 516 | if(!inited) |
496 | { | 517 | { |
497 | res = jz_nand_init(); | 518 | res = jz_nand_init(); |
519 | #ifdef USE_DMA | ||
498 | mutex_init(&nand_mtx); | 520 | mutex_init(&nand_mtx); |
499 | wakeup_init(&nand_wkup); | 521 | wakeup_init(&nand_wkup); |
522 | system_enable_irq(DMA_IRQ(DMA_NAND_CHANNEL)); | ||
523 | #endif | ||
500 | 524 | ||
501 | inited = true; | 525 | inited = true; |
502 | } | 526 | } |