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authorLinus Nielsen Feltzing <linus@haxx.se>2004-10-26 06:55:13 +0000
committerLinus Nielsen Feltzing <linus@haxx.se>2004-10-26 06:55:13 +0000
commite5b141c43907d82de69b3cde93e655c135eb5d9c (patch)
tree4ef71d0d53eb6f4f159f955f03dcf5df1a6ee904
parent2a83ce5ddd7fbe3ff416549bff86e36f5f86ff1b (diff)
downloadrockbox-e5b141c43907d82de69b3cde93e655c135eb5d9c.tar.gz
rockbox-e5b141c43907d82de69b3cde93e655c135eb5d9c.zip
Wrong access mask for LCD and ATA registers
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5353 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/crt0.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/crt0.S b/firmware/crt0.S
index 207946bd2c..baa5361c4e 100644
--- a/firmware/crt0.S
+++ b/firmware/crt0.S
@@ -58,7 +58,7 @@ start:
58 /* Chip select 1 - LCD controller */ 58 /* Chip select 1 - LCD controller */
59 move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */ 59 move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */
60 move.l %d0,(0x08c,%a0) 60 move.l %d0,(0x08c,%a0)
61 move.l #0x0000007b,%d0 /* CSMR1 - 64K, Only data access */ 61 move.l #0x00000075,%d0 /* CSMR1 - 64K, Only data access */
62 move.l %d0,(0x090,%a0) 62 move.l %d0,(0x090,%a0)
63 move.l #0x00002180,%d0 /* CSCR1 - 8 wait states, 16 bits, no bursts */ 63 move.l #0x00002180,%d0 /* CSCR1 - 8 wait states, 16 bits, no bursts */
64 move.l %d0,(0x094,%a0) 64 move.l %d0,(0x094,%a0)
@@ -66,7 +66,7 @@ start:
66 /* Chip select 2 - ATA controller */ 66 /* Chip select 2 - ATA controller */
67 move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */ 67 move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */
68 move.l %d0,(0x098,%a0) 68 move.l %d0,(0x098,%a0)
69 move.l #0x0000007b,%d0 /* CSMR2 - 64K, Only data access */ 69 move.l #0x00000075,%d0 /* CSMR2 - 64K, Only data access */
70 move.l %d0,(0x09c,%a0) 70 move.l %d0,(0x09c,%a0)
71 move.l #0x00000180,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */ 71 move.l #0x00000180,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */
72 move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states. 72 move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states.