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authorAntonius Hellmann <toni@rockbox.org>2009-02-01 09:08:12 +0000
committerAntonius Hellmann <toni@rockbox.org>2009-02-01 09:08:12 +0000
commite55f2329c059434452c62af48903b4607e500e4e (patch)
tree1bcdf3188a89ef5593e1a23a61f4e1b2076e1294
parent8e2ff63a7e1f7c493d867c8b4982feacf6f781ca (diff)
downloadrockbox-e55f2329c059434452c62af48903b4607e500e4e.tar.gz
rockbox-e55f2329c059434452c62af48903b4607e500e4e.zip
First step in committing the results of FS#8663:
Introduce more descriptive register and bit definitions. No functional change here. Thanks to Martin Ritter for his investigations. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19893 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/target/arm/ata-sd-pp.c259
1 files changed, 165 insertions, 94 deletions
diff --git a/firmware/target/arm/ata-sd-pp.c b/firmware/target/arm/ata-sd-pp.c
index 3a095e1321..4711c98769 100644
--- a/firmware/target/arm/ata-sd-pp.c
+++ b/firmware/target/arm/ata-sd-pp.c
@@ -38,32 +38,90 @@
38#define SECTOR_SIZE 512 38#define SECTOR_SIZE 512
39#define BLOCKS_PER_BANK 0x7a7800 39#define BLOCKS_PER_BANK 0x7a7800
40 40
41#define STATUS_REG (*(volatile unsigned int *)(0x70008204)) 41/* Comparing documentations of various MMC/SD controllers revealed, */
42#define REG_1 (*(volatile unsigned int *)(0x70008208)) 42/* that this controller seems to be a mix of PXA27x, PXA255 and */
43#define UNKNOWN (*(volatile unsigned int *)(0x70008210)) 43/* some PP specific stuff. The register and bit definitions are */
44#define BLOCK_SIZE_REG (*(volatile unsigned int *)(0x7000821c)) 44/* taken from the 'PXA27x Developers Manual', as it appears to be */
45#define BLOCK_COUNT_REG (*(volatile unsigned int *)(0x70008220)) 45/* the closest match. Known differences and obscurities are commented.*/
46#define REG_5 (*(volatile unsigned int *)(0x70008224)) 46
47#define CMD_REG0 (*(volatile unsigned int *)(0x70008228)) 47#define MMC_STRPCL (*(volatile unsigned int *)(0x70008200))
48#define CMD_REG1 (*(volatile unsigned int *)(0x7000822c)) 48#define MMC_STAT (*(volatile unsigned int *)(0x70008204))
49#define CMD_REG2 (*(volatile unsigned int *)(0x70008230)) 49#define MMC_CLKRT (*(volatile unsigned int *)(0x70008208))
50#define RESPONSE_REG (*(volatile unsigned int *)(0x70008234)) 50#define MMC_SPI (*(volatile unsigned int *)(0x7000820c))
51#define SD_STATE_REG (*(volatile unsigned int *)(0x70008238)) 51#define MMC_CMDAT (*(volatile unsigned int *)(0x70008210))
52#define REG_11 (*(volatile unsigned int *)(0x70008240)) 52#define MMC_RESTO (*(volatile unsigned int *)(0x70008214))
53#define REG_12 (*(volatile unsigned int *)(0x70008244)) 53#define MMC_RDTO (*(volatile unsigned int *)(0x70008218))
54#define DATA_REG (*(volatile unsigned int *)(0x70008280)) 54#define MMC_BLKLEN (*(volatile unsigned int *)(0x7000821c))
55 55#define MMC_NUMBLK (*(volatile unsigned int *)(0x70008220))
56/* STATUS_REG bits */ 56#define MMC_I_MASK (*(volatile unsigned int *)(0x70008224))
57#define DATA_DONE (1 << 12) 57#define MMC_CMD (*(volatile unsigned int *)(0x70008228))
58#define CMD_DONE (1 << 13) 58#define MMC_ARGH (*(volatile unsigned int *)(0x7000822c))
59#define ERROR_BITS (0x3f) 59#define MMC_ARGL (*(volatile unsigned int *)(0x70008230))
60#define READY_FOR_DATA (1 << 8) 60#define MMC_RES (*(volatile unsigned int *)(0x70008234))
61#define FIFO_FULL (1 << 7) 61
62#define FIFO_EMPTY (1 << 6) 62/* PXA255/27x have separate RX/TX FIFOs with 32x8 bit */
63 63/* PP502x has a combined Data FIFO with 16x16 bit */
64#define CMD_OK 0x0 /* Command was successful */ 64#define MMC_DATA_FIFO (*(volatile unsigned int *)(0x70008280))
65#define CMD_ERROR_2 0x2 /* SD did not respond to command (either it doesn't 65
66 understand the command or is not inserted) */ 66/* PP specific registers, no other controller seem to have such. */
67#define MMC_SD_STATE (*(volatile unsigned int *)(0x70008238))
68#define MMC_INIT_1 (*(volatile unsigned int *)(0x70008240))
69#define MMC_INIT_2 (*(volatile unsigned int *)(0x70008244))
70
71/* MMC_STAT bits */
72#define STAT_SDIO_SUSPEND_ACK (1 << 16)
73#define STAT_SDIO_INT (1 << 15)
74#define STAT_RD_STALLED (1 << 14)
75#define STAT_END_CMD_RES (1 << 13)
76#define STAT_PRG_DONE (1 << 12)
77#define STAT_DATA_TRAN_DONE (1 << 11)
78#define STAT_SPI_WR_ERR (1 << 10)
79#define STAT_FLASH_ERR (1 << 9)
80#define STAT_CLK_EN (1 << 8)
81#define STAT_RECV_FIFO_FULL (1 << 7) /* taken from PXA255 */
82#define STAT_XMIT_FIFO_EMPTY (1 << 6) /* taken from PXA255 */
83#define STAT_RES_CRC_ERR (1 << 5)
84#define STAT_DAT_ERR_TOKEN (1 << 4)
85#define STAT_CRC_RD_ERR (1 << 3)
86#define STAT_CRC_WR_ERR (1 << 2)
87#define STAT_TIME_OUT_RES (1 << 1)
88#define STAT_TIME_OUT_READ (1)
89#define STAT_ERROR_BITS (0x3f)
90
91/* MMC_CMDAT bits */
92/* Some of the bits used by the OF don't make much sense with these */
93/* definitions. So they're probably different between PXA and PP502x */
94/* Bits 0-5 appear to match though. */
95#define CMDAT_SDIO_RESUME (1 << 13)
96#define CMDAT_SDIO_SUSPEND (1 << 12)
97#define CMDAT_SDIO_INT_EN (1 << 11)
98#define CMDAT_STOP_TRAN (1 << 10)
99#define CMDAT_SD_4DAT (1 << 8)
100#define CMDAT_DMA_EN (1 << 7)
101#define CMDAT_INIT (1 << 6)
102#define CMDAT_BUSY (1 << 5)
103#define CMDAT_STRM_BLK (1 << 4)
104#define CMDAT_WR_RD (1 << 3)
105#define CMDAT_DATA_EN (1 << 2)
106#define CMDAT_RES_TYPE3 (3)
107#define CMDAT_RES_TYPE2 (2)
108#define CMDAT_RES_TYPE1 (1)
109
110/* MMC_I_MASK bits */
111/* PP502x apparently only has bits 0-3 */
112#define I_MASK_SDIO_SUSPEND_ACK (1 << 12)
113#define I_MASK_SDIO_INT (1 << 11)
114#define I_MASK_RD_STALLED (1 << 10)
115#define I_MASK_RES_ERR (1 << 9)
116#define I_MASK_DAT_ERR (1 << 8)
117#define I_MASK_TINT (1 << 7)
118#define I_MASK_TXFIFO_WR_REQ (1 << 6)
119#define I_MASK_RXFIFO_RD_REQ (1 << 5)
120#define I_MASK_CLK_IS_OFF (1 << 4)
121#define I_MASK_STOP_CMD (1 << 3)
122#define I_MASK_END_CMD_RES (1 << 2)
123#define I_MASK_PRG_DONE (1 << 1)
124#define I_MASK_DATA_TRAN_DONE (1 << 0)
67 125
68#define FIFO_LEN 16 /* FIFO is 16 words deep */ 126#define FIFO_LEN 16 /* FIFO is 16 words deep */
69 127
@@ -144,7 +202,7 @@ static bool sd_poll_status(unsigned int trigger, long timeout)
144{ 202{
145 long t = USEC_TIMER; 203 long t = USEC_TIMER;
146 204
147 while ((STATUS_REG & trigger) == 0) 205 while ((MMC_STAT & trigger) == 0)
148 { 206 {
149 long time = USEC_TIMER; 207 long time = USEC_TIMER;
150 208
@@ -164,36 +222,36 @@ static bool sd_poll_status(unsigned int trigger, long timeout)
164} 222}
165 223
166static int sd_command(unsigned int cmd, unsigned long arg1, 224static int sd_command(unsigned int cmd, unsigned long arg1,
167 unsigned int *response, unsigned int type) 225 unsigned int *response, unsigned int cmdat)
168{ 226{
169 int i, words; /* Number of 16 bit words to read from RESPONSE_REG */ 227 int i, words; /* Number of 16 bit words to read from MMC_RES */
170 unsigned int data[9]; 228 unsigned int data[9];
171 229
172 CMD_REG0 = cmd; 230 MMC_CMD = cmd;
173 CMD_REG1 = (unsigned int)((arg1 & 0xffff0000) >> 16); 231 MMC_ARGH = (unsigned int)((arg1 & 0xffff0000) >> 16);
174 CMD_REG2 = (unsigned int)((arg1 & 0xffff)); 232 MMC_ARGL = (unsigned int)((arg1 & 0xffff));
175 UNKNOWN = type; 233 MMC_CMDAT = cmdat;
176 234
177 if (!sd_poll_status(CMD_DONE, 100000)) 235 if (!sd_poll_status(STAT_END_CMD_RES, 100000))
178 return -EC_COMMAND; 236 return -EC_COMMAND;
179 237
180 if ((STATUS_REG & ERROR_BITS) != CMD_OK) 238 if ((MMC_STAT & STAT_ERROR_BITS) != 0)
181 /* Error sending command */ 239 /* Error sending command */
182 return -EC_COMMAND - (STATUS_REG & ERROR_BITS)*100; 240 return -EC_COMMAND - (MMC_STAT & STAT_ERROR_BITS)*100;
183 241
184 if (cmd == SD_GO_IDLE_STATE) 242 if (cmd == SD_GO_IDLE_STATE)
185 return 0; /* no response here */ 243 return 0; /* no response here */
186 244
187 words = (type == 2) ? 9 : 3; 245 words = (cmdat == CMDAT_RES_TYPE2) ? 9 : 3;
188 246
189 for (i = 0; i < words; i++) /* RESPONSE_REG is read MSB first */ 247 for (i = 0; i < words; i++) /* MMC_RES is read MSB first */
190 data[i] = RESPONSE_REG; /* Read most significant 16-bit word */ 248 data[i] = MMC_RES; /* Read most significant 16-bit word */
191 249
192 if (response == NULL) 250 if (response == NULL)
193 { 251 {
194 /* response discarded */ 252 /* response discarded */
195 } 253 }
196 else if (type == 2) 254 else if (cmdat == CMDAT_RES_TYPE2)
197 { 255 {
198 /* Response type 2 has the following structure: 256 /* Response type 2 has the following structure:
199 * [135:135] Start Bit - '0' 257 * [135:135] Start Bit - '0'
@@ -252,7 +310,7 @@ static int sd_wait_for_state(unsigned int state, int id)
252 310
253 while (1) 311 while (1)
254 { 312 {
255 int ret = sd_command(SD_SEND_STATUS, currcard->rca, &response, 1); 313 int ret = sd_command(SD_SEND_STATUS, currcard->rca, &response, CMDAT_RES_TYPE1);
256 long us; 314 long us;
257 315
258 if (ret < 0) 316 if (ret < 0)
@@ -260,7 +318,7 @@ static int sd_wait_for_state(unsigned int state, int id)
260 318
261 if (((response >> 9) & 0xf) == state) 319 if (((response >> 9) & 0xf) == state)
262 { 320 {
263 SD_STATE_REG = state; 321 MMC_SD_STATE = state;
264 return 0; 322 return 0;
265 } 323 }
266 324
@@ -297,7 +355,7 @@ static inline void copy_read_sectors_fast(unsigned char **buf)
297 "orr r8, r8, r9, lsl #16 \r\n" 355 "orr r8, r8, r9, lsl #16 \r\n"
298 "stmia %[buf]!, { r2, r4, r6, r8 } \r\n" 356 "stmia %[buf]!, { r2, r4, r6, r8 } \r\n"
299 : [buf]"+&r"(*buf) 357 : [buf]"+&r"(*buf)
300 : [data]"r"(&DATA_REG) 358 : [data]"r"(&MMC_DATA_FIFO)
301 : "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9" 359 : "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9"
302 ); 360 );
303 break; 361 break;
@@ -335,7 +393,7 @@ static inline void copy_read_sectors_fast(unsigned char **buf)
335 "stmia %[buf]!, { r2, r4, r6, r8 } \r\n" 393 "stmia %[buf]!, { r2, r4, r6, r8 } \r\n"
336 "strb r10, [%[buf]], #1 \r\n" 394 "strb r10, [%[buf]], #1 \r\n"
337 : [buf]"+&r"(*buf) 395 : [buf]"+&r"(*buf)
338 : [data]"r"(&DATA_REG) 396 : [data]"r"(&MMC_DATA_FIFO)
339 : "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" 397 : "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10"
340 ); 398 );
341 break; 399 break;
@@ -355,7 +413,7 @@ static inline void copy_read_sectors_fast(unsigned char **buf)
355 "stmia %[buf]!, { r2, r3, r5, r7 } \r\n" 413 "stmia %[buf]!, { r2, r3, r5, r7 } \r\n"
356 "strh r10, [%[buf]], #2 \r\n" 414 "strh r10, [%[buf]], #2 \r\n"
357 : [buf]"+&r"(*buf) 415 : [buf]"+&r"(*buf)
358 : [data]"r"(&DATA_REG) 416 : [data]"r"(&MMC_DATA_FIFO)
359 : "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" 417 : "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10"
360 ); 418 );
361 break; 419 break;
@@ -393,7 +451,7 @@ static inline void copy_read_sectors_fast(unsigned char **buf)
393 "mov r10, r10, lsr #16 \r\n" 451 "mov r10, r10, lsr #16 \r\n"
394 "strb r10, [%[buf]], #1 \r\n" 452 "strb r10, [%[buf]], #1 \r\n"
395 : [buf]"+&r"(*buf) 453 : [buf]"+&r"(*buf)
396 : [data]"r"(&DATA_REG) 454 : [data]"r"(&MMC_DATA_FIFO)
397 : "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10" 455 : "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10"
398 ); 456 );
399 break; 457 break;
@@ -416,7 +474,7 @@ static inline void copy_read_sectors_slow(unsigned char** buf)
416 "bgt 1b \r\n" 474 "bgt 1b \r\n"
417 : [cnt]"+&r"(cnt), [buf]"+&r"(*buf), 475 : [cnt]"+&r"(cnt), [buf]"+&r"(*buf),
418 [t]"=&r"(t) 476 [t]"=&r"(t)
419 : [data]"r"(&DATA_REG) 477 : [data]"r"(&MMC_DATA_FIFO)
420 ); 478 );
421} 479}
422 480
@@ -430,7 +488,7 @@ static inline void copy_write_sectors(const unsigned char** buf)
430 { 488 {
431 t = *(*buf)++; 489 t = *(*buf)++;
432 t |= *(*buf)++ << 8; 490 t |= *(*buf)++ << 8;
433 DATA_REG = t; 491 MMC_DATA_FIFO = t;
434 } while (--cnt > 0); /* tail loop is faster */ 492 } while (--cnt > 0); /* tail loop is faster */
435} 493}
436 494
@@ -446,14 +504,15 @@ static int sd_select_bank(unsigned char bank)
446 if (ret < 0) 504 if (ret < 0)
447 return ret; 505 return ret;
448 506
449 BLOCK_SIZE_REG = 512; 507 MMC_BLKLEN = 512;
450 BLOCK_COUNT_REG = 1; 508 MMC_NUMBLK = 1;
451 509
452 ret = sd_command(35, 0, NULL, 0x1c0d); /* CMD35 is vendor specific */ 510 ret = sd_command(35, 0, NULL, /* CMD35 is vendor specific */
511 0x1c00 | CMDAT_WR_RD | CMDAT_DATA_EN | CMDAT_RES_TYPE1);
453 if (ret < 0) 512 if (ret < 0)
454 return ret; 513 return ret;
455 514
456 SD_STATE_REG = SD_PRG; 515 MMC_SD_STATE = SD_PRG;
457 516
458 card_data[0] = bank; 517 card_data[0] = bank;
459 518
@@ -462,7 +521,7 @@ static int sd_select_bank(unsigned char bank)
462 for (i = 0; i < BLOCK_SIZE/2; i += FIFO_LEN) 521 for (i = 0; i < BLOCK_SIZE/2; i += FIFO_LEN)
463 { 522 {
464 /* Wait for the FIFO to empty */ 523 /* Wait for the FIFO to empty */
465 if (sd_poll_status(FIFO_EMPTY, 10000)) 524 if (sd_poll_status(STAT_XMIT_FIFO_EMPTY, 10000))
466 { 525 {
467 copy_write_sectors(&write_buf); /* Copy one chunk of 16 words */ 526 copy_write_sectors(&write_buf); /* Copy one chunk of 16 words */
468 continue; 527 continue;
@@ -471,7 +530,7 @@ static int sd_select_bank(unsigned char bank)
471 return -EC_FIFO_SEL_BANK_EMPTY; 530 return -EC_FIFO_SEL_BANK_EMPTY;
472 } 531 }
473 532
474 if (!sd_poll_status(DATA_DONE, 10000)) 533 if (!sd_poll_status(STAT_PRG_DONE, 10000))
475 return -EC_FIFO_SEL_BANK_DONE; 534 return -EC_FIFO_SEL_BANK_DONE;
476 535
477 currcard->current_bank = bank; 536 currcard->current_bank = bank;
@@ -549,7 +608,7 @@ static void sd_init_device(int card_no)
549 int ret; 608 int ret;
550 609
551/* Enable and initialise controller */ 610/* Enable and initialise controller */
552 REG_1 = 6; 611 MMC_CLKRT = 6; /* switch to lowest clock rate */
553 612
554/* Initialise card data as blank */ 613/* Initialise card data as blank */
555 memset(currcard, 0, sizeof(*currcard)); 614 memset(currcard, 0, sizeof(*currcard));
@@ -558,22 +617,22 @@ static void sd_init_device(int card_no)
558 sd_card_mux(card_no); 617 sd_card_mux(card_no);
559 618
560/* Init NAND */ 619/* Init NAND */
561 REG_11 |= (1 << 15); 620 MMC_INIT_1 |= (1 << 15);
562 REG_12 |= (1 << 15); 621 MMC_INIT_2 |= (1 << 15);
563 REG_12 &= ~(3 << 12); 622 MMC_INIT_2 &= ~(3 << 12);
564 REG_12 |= (1 << 13); 623 MMC_INIT_2 |= (1 << 13);
565 REG_11 &= ~(3 << 12); 624 MMC_INIT_1 &= ~(3 << 12);
566 REG_11 |= (1 << 13); 625 MMC_INIT_1 |= (1 << 13);
567 626
568 DEV_EN |= DEV_ATA; /* Enable controller */ 627 DEV_EN |= DEV_ATA; /* Enable controller */
569 DEV_RS |= DEV_ATA; /* Reset controller */ 628 DEV_RS |= DEV_ATA; /* Reset controller */
570 DEV_RS &=~DEV_ATA; /* Clear Reset */ 629 DEV_RS &=~DEV_ATA; /* Clear Reset */
571 630
572 SD_STATE_REG = SD_TRAN; 631 MMC_SD_STATE = SD_TRAN;
573 632
574 REG_5 = 0xf; 633 MMC_I_MASK = 0xf; /* disable interrupts */
575 634
576 ret = sd_command(SD_GO_IDLE_STATE, 0, NULL, 256); 635 ret = sd_command(SD_GO_IDLE_STATE, 0, NULL, 0x100);
577 if (ret < 0) 636 if (ret < 0)
578 goto card_init_error; 637 goto card_init_error;
579 638
@@ -586,14 +645,15 @@ static void sd_init_device(int card_no)
586 - SDHC cards echo back the argument into the response. This is how we 645 - SDHC cards echo back the argument into the response. This is how we
587 tell if the card is SDHC. 646 tell if the card is SDHC.
588 */ 647 */
589 ret = sd_command(SD_SEND_IF_COND,0x1aa, &response,7); 648 ret = sd_command(SD_SEND_IF_COND,0x1aa, &response,
649 CMDAT_DATA_EN | CMDAT_RES_TYPE3);
590 if ( (ret < 0) && (ret!=-219) ) 650 if ( (ret < 0) && (ret!=-219) )
591 goto card_init_error; 651 goto card_init_error;
592#endif 652#endif
593 653
594 while ((currcard->ocr & (1 << 31)) == 0) /* until card is powered up */ 654 while ((currcard->ocr & (1 << 31)) == 0) /* until card is powered up */
595 { 655 {
596 ret = sd_command(SD_APP_CMD, currcard->rca, NULL, 1); 656 ret = sd_command(SD_APP_CMD, currcard->rca, NULL, CMDAT_RES_TYPE1);
597 if (ret < 0) 657 if (ret < 0)
598 goto card_init_error; 658 goto card_init_error;
599 659
@@ -602,13 +662,14 @@ static void sd_init_device(int card_no)
602 { 662 {
603 /* SDHC */ 663 /* SDHC */
604 ret = sd_command(SD_APP_OP_COND, (1<<30)|0x100000, 664 ret = sd_command(SD_APP_OP_COND, (1<<30)|0x100000,
605 &currcard->ocr, 3); 665 &currcard->ocr, CMDAT_RES_TYPE3);
606 } 666 }
607 else 667 else
608#endif /* HAVE_HOTSWAP */ 668#endif /* HAVE_HOTSWAP */
609 { 669 {
610 /* SD Standard */ 670 /* SD Standard */
611 ret = sd_command(SD_APP_OP_COND, 0x100000, &currcard->ocr, 3); 671 ret = sd_command(SD_APP_OP_COND, 0x100000, &currcard->ocr,
672 CMDAT_RES_TYPE3);
612 } 673 }
613 674
614 if (ret < 0) 675 if (ret < 0)
@@ -621,15 +682,15 @@ static void sd_init_device(int card_no)
621 } 682 }
622 } 683 }
623 684
624 ret = sd_command(SD_ALL_SEND_CID, 0, currcard->cid, 2); 685 ret = sd_command(SD_ALL_SEND_CID, 0, currcard->cid, CMDAT_RES_TYPE2);
625 if (ret < 0) 686 if (ret < 0)
626 goto card_init_error; 687 goto card_init_error;
627 688
628 ret = sd_command(SD_SEND_RELATIVE_ADDR, 0, &currcard->rca, 1); 689 ret = sd_command(SD_SEND_RELATIVE_ADDR, 0, &currcard->rca, CMDAT_RES_TYPE1);
629 if (ret < 0) 690 if (ret < 0)
630 goto card_init_error; 691 goto card_init_error;
631 692
632 ret = sd_command(SD_SEND_CSD, currcard->rca, currcard->csd, 2); 693 ret = sd_command(SD_SEND_CSD, currcard->rca, currcard->csd, CMDAT_RES_TYPE2);
633 if (ret < 0) 694 if (ret < 0)
634 goto card_init_error; 695 goto card_init_error;
635 696
@@ -656,34 +717,38 @@ static void sd_init_device(int card_no)
656 } 717 }
657#endif /* HAVE_HOTSWAP */ 718#endif /* HAVE_HOTSWAP */
658 719
659 REG_1 = 0; 720 MMC_CLKRT = 0; /* switch to highest clock rate */
660 721
661 ret = sd_command(SD_SELECT_CARD, currcard->rca, NULL, 129); 722 ret = sd_command(SD_SELECT_CARD, currcard->rca, NULL,
723 0x80 | CMDAT_RES_TYPE1);
662 if (ret < 0) 724 if (ret < 0)
663 goto card_init_error; 725 goto card_init_error;
664 726
665 ret = sd_command(SD_APP_CMD, currcard->rca, NULL, 1); 727 ret = sd_command(SD_APP_CMD, currcard->rca, NULL, CMDAT_RES_TYPE1);
666 if (ret < 0) 728 if (ret < 0)
667 goto card_init_error; 729 goto card_init_error;
668 730
669 ret = sd_command(SD_SET_BUS_WIDTH, currcard->rca | 2, NULL, 1); /* 4 bit */ 731 ret = sd_command(SD_SET_BUS_WIDTH, currcard->rca | 2, NULL,
732 CMDAT_RES_TYPE1); /* 4 bit */
670 if (ret < 0) 733 if (ret < 0)
671 goto card_init_error; 734 goto card_init_error;
672 735
673 ret = sd_command(SD_SET_BLOCKLEN, currcard->block_size, NULL, 1); 736 ret = sd_command(SD_SET_BLOCKLEN, currcard->block_size, NULL,
737 CMDAT_RES_TYPE1);
674 if (ret < 0) 738 if (ret < 0)
675 goto card_init_error; 739 goto card_init_error;
676 740
677 BLOCK_SIZE_REG = currcard->block_size; 741 MMC_BLKLEN = currcard->block_size;
678 742
679 /* If this card is >4GB & not SDHC, then we need to enable bank switching */ 743 /* If this card is >4GB & not SDHC, then we need to enable bank switching */
680 if( (currcard->numblocks >= BLOCKS_PER_BANK) && 744 if( (currcard->numblocks >= BLOCKS_PER_BANK) &&
681 ((currcard->ocr & (1<<30)) == 0) ) 745 ((currcard->ocr & (1<<30)) == 0) )
682 { 746 {
683 SD_STATE_REG = SD_TRAN; 747 MMC_SD_STATE = SD_TRAN;
684 BLOCK_COUNT_REG = 1; 748 MMC_NUMBLK = 1;
685 749
686 ret = sd_command(SD_SWITCH_FUNC, 0x80ffffef, NULL, 0x1c05); 750 ret = sd_command(SD_SWITCH_FUNC, 0x80ffffef, NULL,
751 0x1c00 | CMDAT_DATA_EN | CMDAT_RES_TYPE1);
687 if (ret < 0) 752 if (ret < 0)
688 goto card_init_error; 753 goto card_init_error;
689 754
@@ -694,7 +759,7 @@ static void sd_init_device(int card_no)
694 for (i = 0; i < BLOCK_SIZE/2; i += FIFO_LEN) 759 for (i = 0; i < BLOCK_SIZE/2; i += FIFO_LEN)
695 { 760 {
696 /* Wait for the FIFO to be full */ 761 /* Wait for the FIFO to be full */
697 if (sd_poll_status(FIFO_FULL, 100000)) 762 if (sd_poll_status(STAT_RECV_FIFO_FULL, 100000))
698 { 763 {
699 copy_read_sectors_slow(&dataptr); 764 copy_read_sectors_slow(&dataptr);
700 continue; 765 continue;
@@ -798,18 +863,20 @@ sd_read_retry:
798 if (ret < 0) 863 if (ret < 0)
799 goto sd_read_error; 864 goto sd_read_error;
800 865
801 BLOCK_COUNT_REG = incount; 866 MMC_NUMBLK = incount;
802 867
803#ifdef HAVE_HOTSWAP 868#ifdef HAVE_HOTSWAP
804 if(currcard->ocr & (1<<30) ) 869 if(currcard->ocr & (1<<30) )
805 { 870 {
806 /* SDHC */ 871 /* SDHC */
807 ret = sd_command(SD_READ_MULTIPLE_BLOCK, start, NULL, 0x1c25); 872 ret = sd_command(SD_READ_MULTIPLE_BLOCK, start, NULL,
873 0x1c00 | CMDAT_BUSY | CMDAT_DATA_EN | CMDAT_RES_TYPE1);
808 } 874 }
809 else 875 else
810#endif 876#endif
811 { 877 {
812 ret = sd_command(SD_READ_MULTIPLE_BLOCK, start * BLOCK_SIZE, NULL, 0x1c25); 878 ret = sd_command(SD_READ_MULTIPLE_BLOCK, start * BLOCK_SIZE, NULL,
879 0x1c00 | CMDAT_BUSY | CMDAT_DATA_EN | CMDAT_RES_TYPE1);
813 } 880 }
814 if (ret < 0) 881 if (ret < 0)
815 goto sd_read_error; 882 goto sd_read_error;
@@ -820,7 +887,7 @@ sd_read_retry:
820 for (buf = inbuf; buf < buf_end;) 887 for (buf = inbuf; buf < buf_end;)
821 { 888 {
822 /* Wait for the FIFO to be full */ 889 /* Wait for the FIFO to be full */
823 if (sd_poll_status(FIFO_FULL, 0x80000)) 890 if (sd_poll_status(STAT_RECV_FIFO_FULL, 0x80000))
824 { 891 {
825 copy_read_sectors_fast(&buf); /* Copy one chunk of 16 words */ 892 copy_read_sectors_fast(&buf); /* Copy one chunk of 16 words */
826 /* TODO: Switch bank if necessary */ 893 /* TODO: Switch bank if necessary */
@@ -833,7 +900,7 @@ sd_read_retry:
833 900
834 last_disk_activity = current_tick; 901 last_disk_activity = current_tick;
835 902
836 ret = sd_command(SD_STOP_TRANSMISSION, 0, NULL, 1); 903 ret = sd_command(SD_STOP_TRANSMISSION, 0, NULL, CMDAT_RES_TYPE1);
837 if (ret < 0) 904 if (ret < 0)
838 goto sd_read_error; 905 goto sd_read_error;
839 906
@@ -914,18 +981,22 @@ sd_write_retry:
914 if (ret < 0) 981 if (ret < 0)
915 goto sd_write_error; 982 goto sd_write_error;
916 983
917 BLOCK_COUNT_REG = count; 984 MMC_NUMBLK = count;
918 985
919#ifdef HAVE_HOTSWAP 986#ifdef HAVE_HOTSWAP
920 if(currcard->ocr & (1<<30) ) 987 if(currcard->ocr & (1<<30) )
921 { 988 {
922 /* SDHC */ 989 /* SDHC */
923 ret = sd_command(SD_WRITE_MULTIPLE_BLOCK, start, NULL, 0x1c2d); 990 ret = sd_command(SD_WRITE_MULTIPLE_BLOCK, start, NULL,
991 0x1c00 | CMDAT_BUSY | CMDAT_WR_RD |
992 CMDAT_DATA_EN | CMDAT_RES_TYPE1);
924 } 993 }
925 else 994 else
926#endif 995#endif
927 { 996 {
928 ret = sd_command(SD_WRITE_MULTIPLE_BLOCK, start*BLOCK_SIZE, NULL, 0x1c2d); 997 ret = sd_command(SD_WRITE_MULTIPLE_BLOCK, start*BLOCK_SIZE, NULL,
998 0x1c00 | CMDAT_BUSY | CMDAT_WR_RD |
999 CMDAT_DATA_EN | CMDAT_RES_TYPE1);
929 } 1000 }
930 if (ret < 0) 1001 if (ret < 0)
931 goto sd_write_error; 1002 goto sd_write_error;
@@ -936,14 +1007,14 @@ sd_write_retry:
936 { 1007 {
937 if (buf == buf_end) 1008 if (buf == buf_end)
938 { 1009 {
939 /* Set SD_STATE_REG to SD_PRG for the last buffer fill */ 1010 /* Set MMC_SD_STATE to SD_PRG for the last buffer fill */
940 SD_STATE_REG = SD_PRG; 1011 MMC_SD_STATE = SD_PRG;
941 } 1012 }
942 1013
943 udelay(2); /* needed here (loop is too fast :-) */ 1014 udelay(2); /* needed here (loop is too fast :-) */
944 1015
945 /* Wait for the FIFO to empty */ 1016 /* Wait for the FIFO to empty */
946 if (sd_poll_status(FIFO_EMPTY, 0x80000)) 1017 if (sd_poll_status(STAT_XMIT_FIFO_EMPTY, 0x80000))
947 { 1018 {
948 copy_write_sectors(&buf); /* Copy one chunk of 16 words */ 1019 copy_write_sectors(&buf); /* Copy one chunk of 16 words */
949 /* TODO: Switch bank if necessary */ 1020 /* TODO: Switch bank if necessary */
@@ -956,13 +1027,13 @@ sd_write_retry:
956 1027
957 last_disk_activity = current_tick; 1028 last_disk_activity = current_tick;
958 1029
959 if (!sd_poll_status(DATA_DONE, 0x80000)) 1030 if (!sd_poll_status(STAT_PRG_DONE, 0x80000))
960 { 1031 {
961 ret = -EC_FIFO_WR_DONE; 1032 ret = -EC_FIFO_WR_DONE;
962 goto sd_write_error; 1033 goto sd_write_error;
963 } 1034 }
964 1035
965 ret = sd_command(SD_STOP_TRANSMISSION, 0, NULL, 1); 1036 ret = sd_command(SD_STOP_TRANSMISSION, 0, NULL, CMDAT_RES_TYPE1);
966 if (ret < 0) 1037 if (ret < 0)
967 goto sd_write_error; 1038 goto sd_write_error;
968 1039