diff options
author | Bob Cousins <bobc@rockbox.org> | 2009-11-03 13:50:52 +0000 |
---|---|---|
committer | Bob Cousins <bobc@rockbox.org> | 2009-11-03 13:50:52 +0000 |
commit | deb1b0e51c59518a6152b9a4b1f24004545c5c57 (patch) | |
tree | 3feb40c5156b777fd5383669ab95f0caf6165bdf | |
parent | bb9808b8afe1e95b0d7734840e64a91a0da3fe9b (diff) | |
download | rockbox-deb1b0e51c59518a6152b9a4b1f24004545c5c57.tar.gz rockbox-deb1b0e51c59518a6152b9a4b1f24004545c5c57.zip |
Improvements to mini2440 audio; change CPU freq to 406MHz
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23495 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/drivers/audio/uda1341.c | 1 | ||||
-rw-r--r-- | firmware/export/config-mini2440.h | 7 | ||||
-rw-r--r-- | firmware/sound.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/crt0.S | 6 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c | 1 | ||||
-rw-r--r-- | firmware/target/arm/s3c2440/system-target.h | 22 |
6 files changed, 20 insertions, 21 deletions
diff --git a/firmware/drivers/audio/uda1341.c b/firmware/drivers/audio/uda1341.c index 0171169942..17d0475f2b 100644 --- a/firmware/drivers/audio/uda1341.c +++ b/firmware/drivers/audio/uda1341.c | |||
@@ -170,7 +170,6 @@ static void udacodec_reset(void) | |||
170 | /* [reserved, master clock rate] */ | 170 | /* [reserved, master clock rate] */ |
171 | static const unsigned char uda_freq_parms[HW_NUM_FREQ][2] = | 171 | static const unsigned char uda_freq_parms[HW_NUM_FREQ][2] = |
172 | { | 172 | { |
173 | [HW_FREQ_64] = { 0, UDA_SYSCLK_256FS }, | ||
174 | [HW_FREQ_44] = { 0, UDA_SYSCLK_384FS }, | 173 | [HW_FREQ_44] = { 0, UDA_SYSCLK_384FS }, |
175 | [HW_FREQ_22] = { 0, UDA_SYSCLK_256FS }, | 174 | [HW_FREQ_22] = { 0, UDA_SYSCLK_256FS }, |
176 | [HW_FREQ_11] = { 0, UDA_SYSCLK_256FS }, | 175 | [HW_FREQ_11] = { 0, UDA_SYSCLK_256FS }, |
diff --git a/firmware/export/config-mini2440.h b/firmware/export/config-mini2440.h index a477236d19..f08d4875ef 100644 --- a/firmware/export/config-mini2440.h +++ b/firmware/export/config-mini2440.h | |||
@@ -84,11 +84,8 @@ | |||
84 | 84 | ||
85 | /* Define DAC/Codec */ | 85 | /* Define DAC/Codec */ |
86 | #define HAVE_UDA1341 | 86 | #define HAVE_UDA1341 |
87 | /* ... tone controls, use the software ones */ | ||
88 | #define HAVE_SW_TONE_CONTROLS | ||
89 | 87 | ||
90 | #define HW_SAMPR_CAPS (SAMPR_CAP_64 | SAMPR_CAP_44 | SAMPR_CAP_22 | \ | 88 | #define HW_SAMPR_CAPS (SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11) |
91 | SAMPR_CAP_11) | ||
92 | 89 | ||
93 | /* Battery */ | 90 | /* Battery */ |
94 | #define BATTERY_CAPACITY_DEFAULT 1100 /* default battery capacity */ | 91 | #define BATTERY_CAPACITY_DEFAULT 1100 /* default battery capacity */ |
@@ -130,7 +127,7 @@ | |||
130 | #define CONFIG_CPU S3C2440 | 127 | #define CONFIG_CPU S3C2440 |
131 | 128 | ||
132 | /* Define this to the CPU frequency */ | 129 | /* Define this to the CPU frequency */ |
133 | #define CPU_FREQ 405000000 | 130 | #define CPU_FREQ 406000000 |
134 | #define MCK_FREQ (CPU_FREQ/4) | 131 | #define MCK_FREQ (CPU_FREQ/4) |
135 | #define SLOW_CLOCK 32768 | 132 | #define SLOW_CLOCK 32768 |
136 | 133 | ||
diff --git a/firmware/sound.c b/firmware/sound.c index b327e3839c..bd85ad17ce 100644 --- a/firmware/sound.c +++ b/firmware/sound.c | |||
@@ -205,7 +205,7 @@ static void set_prescaled_volume(void) | |||
205 | #if defined(HAVE_SW_TONE_CONTROLS) || !(defined(HAVE_WM8975) \ | 205 | #if defined(HAVE_SW_TONE_CONTROLS) || !(defined(HAVE_WM8975) \ |
206 | || defined(HAVE_WM8711) || defined(HAVE_WM8721) || defined(HAVE_WM8731) \ | 206 | || defined(HAVE_WM8711) || defined(HAVE_WM8721) || defined(HAVE_WM8731) \ |
207 | || defined(HAVE_WM8751) || defined(HAVE_WM8758) || defined(HAVE_WM8985)) \ | 207 | || defined(HAVE_WM8751) || defined(HAVE_WM8758) || defined(HAVE_WM8985)) \ |
208 | || defined(HAVE_TSC2100) | 208 | || defined(HAVE_TSC2100) || defined(HAVE_UDA1341) |
209 | 209 | ||
210 | prescale = MAX(current_bass, current_treble); | 210 | prescale = MAX(current_bass, current_treble); |
211 | if (prescale < 0) | 211 | if (prescale < 0) |
@@ -250,7 +250,7 @@ static void set_prescaled_volume(void) | |||
250 | #elif defined(HAVE_UDA1380) || defined(HAVE_WM8975) || defined(HAVE_WM8758) \ | 250 | #elif defined(HAVE_UDA1380) || defined(HAVE_WM8975) || defined(HAVE_WM8758) \ |
251 | || defined(HAVE_WM8711) || defined(HAVE_WM8721) || defined(HAVE_WM8731) \ | 251 | || defined(HAVE_WM8711) || defined(HAVE_WM8721) || defined(HAVE_WM8731) \ |
252 | || defined(HAVE_WM8751) || defined(HAVE_AS3514) || defined(HAVE_TSC2100) \ | 252 | || defined(HAVE_WM8751) || defined(HAVE_AS3514) || defined(HAVE_TSC2100) \ |
253 | || defined(HAVE_AK4537) | 253 | || defined(HAVE_AK4537) || defined(HAVE_UDA1341) |
254 | audiohw_set_master_vol(tenthdb2master(l), tenthdb2master(r)); | 254 | audiohw_set_master_vol(tenthdb2master(l), tenthdb2master(r)); |
255 | #if defined(HAVE_WM8975) || defined(HAVE_WM8758) \ | 255 | #if defined(HAVE_WM8975) || defined(HAVE_WM8758) \ |
256 | || (defined(HAVE_WM8751) && !defined(MROBE_100)) || defined(HAVE_WM8985) | 256 | || (defined(HAVE_WM8751) && !defined(MROBE_100)) || defined(HAVE_WM8985) |
diff --git a/firmware/target/arm/s3c2440/crt0.S b/firmware/target/arm/s3c2440/crt0.S index 3110c88be0..2188bc07da 100644 --- a/firmware/target/arm/s3c2440/crt0.S +++ b/firmware/target/arm/s3c2440/crt0.S | |||
@@ -138,13 +138,11 @@ | |||
138 | 138 | ||
139 | /* For Mini2440 board or compatible */ | 139 | /* For Mini2440 board or compatible */ |
140 | /* Clock and Power Management setup values */ | 140 | /* Clock and Power Management setup values */ |
141 | /* NB: clock settings must match values in s3c2440/system-target.h */ | ||
141 | #define VAL_CLKDIV 0x5 /* HCLK = FCLK/4, PCLK = HCLK/2 */ | 142 | #define VAL_CLKDIV 0x5 /* HCLK = FCLK/4, PCLK = HCLK/2 */ |
142 | #define VAL_UPLLCON 0x00038022 /* UCLK = 48 MHz */ | 143 | #define VAL_UPLLCON 0x00038022 /* UCLK = 48 MHz */ |
143 | #define VAL_MPLLCON 0x0007F021 /* FCLK = 405 MHz */ | 144 | #define VAL_MPLLCON 0x000C3041 /* FCLK = 406 MHz */ |
144 | 145 | ||
145 | #define FCLK 405000000 | ||
146 | #define HCLK (FCLK/4) /* = 101,250,000 */ | ||
147 | #define PCLK (HCLK/2) /* = 50,625,000 */ | ||
148 | 146 | ||
149 | /* Memory Controller setup */ | 147 | /* Memory Controller setup */ |
150 | #define VAL_BWSCON 0x22111112 | 148 | #define VAL_BWSCON 0x22111112 |
diff --git a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c index 9c898f88d9..7779639c8f 100644 --- a/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c +++ b/firmware/target/arm/s3c2440/mini2440/pcm-mini2440.c | |||
@@ -48,7 +48,6 @@ static struct | |||
48 | /* [prescaler, master clock rate] */ | 48 | /* [prescaler, master clock rate] */ |
49 | static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] = | 49 | static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] = |
50 | { | 50 | { |
51 | [HW_FREQ_64] = { 2, IISMOD_MASTER_CLOCK_256FS }, | ||
52 | [HW_FREQ_44] = { 2, IISMOD_MASTER_CLOCK_384FS }, | 51 | [HW_FREQ_44] = { 2, IISMOD_MASTER_CLOCK_384FS }, |
53 | [HW_FREQ_22] = { 8, IISMOD_MASTER_CLOCK_256FS }, | 52 | [HW_FREQ_22] = { 8, IISMOD_MASTER_CLOCK_256FS }, |
54 | [HW_FREQ_11] = { 17, IISMOD_MASTER_CLOCK_256FS }, | 53 | [HW_FREQ_11] = { 17, IISMOD_MASTER_CLOCK_256FS }, |
diff --git a/firmware/target/arm/s3c2440/system-target.h b/firmware/target/arm/s3c2440/system-target.h index cf3db301eb..7bb49c01c4 100644 --- a/firmware/target/arm/s3c2440/system-target.h +++ b/firmware/target/arm/s3c2440/system-target.h | |||
@@ -24,13 +24,18 @@ | |||
24 | #include "system-arm.h" | 24 | #include "system-arm.h" |
25 | #include "mmu-arm.h" | 25 | #include "mmu-arm.h" |
26 | 26 | ||
27 | /* TODO: Needs checking/porting */ | 27 | /* NB: These values must match the register settings in s3c2440/crt0.S */ |
28 | 28 | ||
29 | #ifdef GIGABEAT_F | 29 | #ifdef GIGABEAT_F |
30 | #define CPUFREQ_DEFAULT 98784000 | 30 | #define CPUFREQ_DEFAULT 98784000 |
31 | #define CPUFREQ_NORMAL 98784000 | 31 | #define CPUFREQ_NORMAL 98784000 |
32 | #define CPUFREQ_MAX 296352000 | 32 | #define CPUFREQ_MAX 296352000 |
33 | 33 | ||
34 | /* Uses 1:3:6 */ | ||
35 | #define FCLK CPUFREQ_MAX | ||
36 | #define HCLK (FCLK/3) /* = 98,784,000 */ | ||
37 | #define PCLK (HCLK/2) /* = 49,392,000 */ | ||
38 | |||
34 | #ifdef BOOTLOADER | 39 | #ifdef BOOTLOADER |
35 | /* All addresses within rockbox are in IRAM in the bootloader so | 40 | /* All addresses within rockbox are in IRAM in the bootloader so |
36 | are therefore uncached */ | 41 | are therefore uncached */ |
@@ -42,17 +47,18 @@ | |||
42 | 47 | ||
43 | #elif defined(MINI2440) | 48 | #elif defined(MINI2440) |
44 | 49 | ||
45 | #define CPUFREQ_DEFAULT 101250000 | 50 | /* Uses 1:4:8 */ |
46 | #define CPUFREQ_NORMAL 101250000 | 51 | #define FCLK 406000000 |
47 | #define CPUFREQ_MAX 405000000 | 52 | #define HCLK (FCLK/4) /* = 101,250,000 */ |
53 | #define PCLK (HCLK/2) /* = 50,625,000 */ | ||
54 | |||
55 | #define CPUFREQ_DEFAULT FCLK /* 406 MHz */ | ||
56 | #define CPUFREQ_NORMAL (FCLK/4)/* 101.25 MHz */ | ||
57 | #define CPUFREQ_MAX FCLK /* 406 MHz */ | ||
48 | 58 | ||
49 | #define UNCACHED_BASE_ADDR 0x30000000 | 59 | #define UNCACHED_BASE_ADDR 0x30000000 |
50 | #define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR )) | 60 | #define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR )) |
51 | 61 | ||
52 | #define FCLK 405000000 | ||
53 | #define HCLK (FCLK/4) /* = 101,250,000 */ | ||
54 | #define PCLK (HCLK/2) /* = 50,625,000 */ | ||
55 | |||
56 | #else | 62 | #else |
57 | #error Unknown target | 63 | #error Unknown target |
58 | #endif | 64 | #endif |