jz4760b/regtools: fix/rename some register fields, add clock analyzer to qeditor

Change-Id: I196414d6e4fc18c00b77903e334b7e6adfb7debc

3 files changed, 87 insertions, 6 deletions

diff --git a/utils/regtools/desc/regs-jz4760b.xml b/utils/regtools/desc/regs-jz4760b.xml
index 1d0df1bdd8..01e9d3febb 100644
--- a/utils/regtools/desc/regs-jz4760b.xml
+++ b/utils/regtools/desc/regs-jz4760b.xml
@@ -1017,14 +1017,14 @@
             </instance>
             <register>
                 <field>
-                    <name>SRC_SEL</name>
+                    <name>OUT_SEL</name>
                     <position>30</position>
                     <enum>
-                        <name>EXCLK</name>
+                        <name>LCD_PANEL</name>
                         <value>0x0</value>
                     </enum>
                     <enum>
-                        <name>PLL</name>
+                        <name>TV_ENC</name>
                         <value>0x1</value>
                     </enum>
                 </field>
@@ -1427,7 +1427,7 @@
         <node>
             <name>COUNTH_BUF</name>
             <instance>
-                <name>OSTCNTH_BUF</name>
+                <name>COUNTH_BUF</name>
                 <address>0xfc</address>
             </instance>
             <register/>
@@ -2222,7 +2222,7 @@
             <name>TRIGGER</name>
             <title>Trigger</title>
             <instance>
-                <name>TRG</name>
+                <name>TRIGGER</name>
                 <range>
                     <first>0</first>
                     <count>6</count>
diff --git a/utils/regtools/qeditor/std_analysers.cpp b/utils/regtools/qeditor/std_analysers.cpp
index 05a90f9d5b..bc64c518c8 100644
--- a/utils/regtools/qeditor/std_analysers.cpp
+++ b/utils/regtools/qeditor/std_analysers.cpp
@@ -84,7 +84,10 @@ QWidget *ClockAnalyser::GetWidget()
 
 bool ClockAnalyser::SupportSoc(const QString& soc_name)
 {
-    return (soc_name == "imx233" || soc_name == "rk27xx" || soc_name == "atj213x");
+    return soc_name == "imx233"
+        || soc_name == "rk27xx"
+        || soc_name == "atj213x"
+        || soc_name == "jz4760b";
 }
 
 QString ClockAnalyser::GetFreq(unsigned freq)
@@ -137,10 +140,87 @@ void ClockAnalyser::FillTree()
     if(m_soc.get()->name == "imx233") FillTreeIMX233();
     else if(m_soc.get()->name == "rk27xx") FillTreeRK27XX();
     else if(m_soc.get()->name == "atj213x") FillTreeATJ213X();
+    else if(m_soc.get()->name == "jz4760b") FillTreeJZ4760B();
     m_tree_widget->expandAll();
     m_tree_widget->resizeColumnToContents(0);
 }
 
+void ClockAnalyser::FillTreeJZ4760B()
+{
+    AddClock(0, "RTCLK", 32768);
+    // assume EXCLK is 12MHz, we have no way to knowing for sure but this is the
+    // recommended value anyway
+    QTreeWidgetItem *exclk = AddClock(0, "EXCLK", 12000000);
+    // PLL0
+    soc_word_t pllm, plln, pllod, pllbypass;
+    QTreeWidgetItem *pll0 = 0;
+    if(ReadFieldOld("CPM", "PLLCTRL0", "FEED_DIV", pllm) &&
+            ReadFieldOld("CPM", "PLLCTRL0", "IN_DIV", plln) &&
+            ReadFieldOld("CPM", "PLLCTRL0", "OUT_DIV", pllod) &&
+            ReadFieldOld("CPM", "PLLCTRL0", "BYPASS", pllbypass))
+    {
+        pll0 = AddClock(exclk, "PLL0", FROM_PARENT, pllbypass ? 1 : 2 * pllm,
+            pllbypass ? 1 : plln * (1 << pllod));
+    }
+    else
+        pll0 = AddClock(exclk, "PLL0", INVALID);
+    // PLL1
+    soc_word_t plldiv, src_sel;
+    QTreeWidgetItem *pll1 = 0;
+    if(ReadFieldOld("CPM", "PLLCTRL1", "FEED_DIV", pllm) &&
+            ReadFieldOld("CPM", "PLLCTRL1", "IN_DIV", plln) &&
+            ReadFieldOld("CPM", "PLLCTRL1", "OUT_DIV", pllod) &&
+            ReadFieldOld("CPM", "PLLCTRL1", "SRC_SEL", src_sel) &&
+            ReadFieldOld("CPM", "PLLCTRL1", "PLL0_DIV", plldiv))
+    {
+        pll1 = AddClock(src_sel ? pll0 : exclk, "PLL1", FROM_PARENT, 2 * pllm,
+            plln * (1 << pllod) * (src_sel ? plldiv : 1));
+    }
+    else
+        pll1 = AddClock(exclk, "PLL1", INVALID);
+    // system clocks
+    const int NR_SYSCLK = 6;
+    const char *sysclk[NR_SYSCLK] = { "CCLK", "SCLK", "PCLK", "HCLK", "H2CLK", "MCLK"};
+    for(int i = 0; i < NR_SYSCLK; i++)
+    {
+        soc_word_t div = 0;
+        std::string field = std::string(sysclk[i]) + "_DIV";
+        if(ReadFieldOld("CPM", "SYSCLK", field.c_str(), div))
+        {
+            switch(div)
+            {
+                case 0: div = 1; break;
+                case 1: div = 2; break;
+                case 2: div = 3; break;
+                case 3: div = 4; break;
+                case 4: div = 6; break;
+                case 5: div = 8; break;
+                default: div = 0; break;
+            }
+        }
+        if(div != 0)
+            AddClock(pll0, sysclk[i], FROM_PARENT, 1, div);
+        else
+            AddClock(pll0, sysclk[i], INVALID);
+    }
+    // common to msc, i2s, lcd, uhc, otg, ssi, pcm, gpu, gps
+    soc_word_t pll_div;
+    if(ReadFieldOld("CPM", "SYSCLK", "PLL_DIV", pll_div))
+        pll_div = pll_div ? 1 : 2;
+    else
+        pll_div = 1; // error
+    // lcd
+    soc_word_t pll_sel, div;
+    if(ReadFieldOld("CPM", "LCDCLK", "DIV", div) &&
+            ReadFieldOld("CPM", "LCDCLK", "PLL_SEL", pll_sel))
+    {
+        AddClock(pll_sel ? pll1 : pll0, "LCDCLK",
+            FROM_PARENT, 1, pll_div * (div + 1));
+    }
+    else
+        AddClock(exclk, "LCDCLK", INVALID);
+}
+
 void ClockAnalyser::FillTreeATJ213X()
 {
     soc_word_t pllbypass, pllclk, en, coreclks, tmp0, tmp1, tmp2, tmp3;
diff --git a/utils/regtools/qeditor/std_analysers.h b/utils/regtools/qeditor/std_analysers.h
index 030e010f58..3ab4735e0a 100644
--- a/utils/regtools/qeditor/std_analysers.h
+++ b/utils/regtools/qeditor/std_analysers.h
@@ -77,6 +77,7 @@ private:
     void FillTreeIMX233();
     void FillTreeRK27XX();
     void FillTreeATJ213X();
+    void FillTreeJZ4760B();
 
 private:
     QGroupBox *m_group;