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authorMaurus Cuelenaere <mcuelenaere@gmail.com>2008-10-07 20:24:41 +0000
committerMaurus Cuelenaere <mcuelenaere@gmail.com>2008-10-07 20:24:41 +0000
commitd07ac657a428754b177a894959fba03474b181a8 (patch)
tree1a5fffcafc14dacc8204e1ba5f2b15667c95129a
parent9003c116ca06e7a11f444dfe026075dd2a2ff8d9 (diff)
downloadrockbox-d07ac657a428754b177a894959fba03474b181a8.tar.gz
rockbox-d07ac657a428754b177a894959fba03474b181a8.zip
Forgot one ...
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18738 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/target/mips/ingenic_jz47xx/onda_vx767/lcd-ondavx767.c44
1 files changed, 22 insertions, 22 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/onda_vx767/lcd-ondavx767.c b/firmware/target/mips/ingenic_jz47xx/onda_vx767/lcd-ondavx767.c
index 010964f334..c8288a4450 100644
--- a/firmware/target/mips/ingenic_jz47xx/onda_vx767/lcd-ondavx767.c
+++ b/firmware/target/mips/ingenic_jz47xx/onda_vx767/lcd-ondavx767.c
@@ -23,15 +23,15 @@
23#include "jz4740.h" 23#include "jz4740.h"
24#include "lcd-target.h" 24#include "lcd-target.h"
25 25
26#define PIN_CS_N (32*1+17) /* Chip select */ 26#define PIN_CS_N (32*1+17) /* Chip select */
27#define PIN_RESET_N (32*1+18) /* Reset */ 27#define PIN_RESET_N (32*1+18) /* Reset */
28#define PIN_UNK_N (32*2+19) 28#define PIN_UNK_N (32*2+19)
29 29
30#define my__gpio_as_lcd_16bit() \ 30#define my__gpio_as_lcd_16bit() \
31do { \ 31do { \
32 REG_GPIO_PXFUNS(2) = 0x0014ffff; \ 32 REG_GPIO_PXFUNS(2) = 0x0014ffff; \
33 REG_GPIO_PXSELC(2) = 0x0014ffff; \ 33 REG_GPIO_PXSELC(2) = 0x0014ffff; \
34 REG_GPIO_PXPES(2) = 0x0014ffff; \ 34 REG_GPIO_PXPES(2) = 0x0014ffff; \
35} while (0) 35} while (0)
36 36
37 37
@@ -50,12 +50,12 @@ static void _display_pin_init(void)
50 __gpio_clear_pin(PIN_CS_N); 50 __gpio_clear_pin(PIN_CS_N);
51 DELAY; /* delay_ms(10); */ 51 DELAY; /* delay_ms(10); */
52 52
53 __gpio_set_pin(PIN_RESET_N); 53 __gpio_set_pin(PIN_RESET_N);
54 DELAY; /* delay_ms(10); */ 54 DELAY; /* delay_ms(10); */
55 __gpio_clear_pin(PIN_RESET_N); 55 __gpio_clear_pin(PIN_RESET_N);
56 DELAY; /* delay_ms(10); */ 56 DELAY; /* delay_ms(10); */
57 __gpio_set_pin(PIN_RESET_N); 57 __gpio_set_pin(PIN_RESET_N);
58 DELAY; /* delay_ms(10); */ 58 DELAY; /* delay_ms(10); */
59} 59}
60 60
61#define WAIT_ON_SLCD while(REG_SLCD_STATE & SLCD_STATE_BUSY); 61#define WAIT_ON_SLCD while(REG_SLCD_STATE & SLCD_STATE_BUSY);
@@ -150,7 +150,7 @@ static void _display_off(void)
150static void _set_lcd_bus(void) 150static void _set_lcd_bus(void)
151{ 151{
152 REG_LCD_CFG &= ~LCD_CFG_LCDPIN_MASK; 152 REG_LCD_CFG &= ~LCD_CFG_LCDPIN_MASK;
153 REG_LCD_CFG |= LCD_CFG_LCDPIN_SLCD; 153 REG_LCD_CFG |= LCD_CFG_LCDPIN_SLCD;
154 154
155 REG_SLCD_CFG = (SLCD_CFG_BURST_4_WORD | SLCD_CFG_DWIDTH_18 | SLCD_CFG_CWIDTH_18BIT 155 REG_SLCD_CFG = (SLCD_CFG_BURST_4_WORD | SLCD_CFG_DWIDTH_18 | SLCD_CFG_CWIDTH_18BIT
156 | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING 156 | SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING
@@ -161,17 +161,17 @@ static void _set_lcd_bus(void)
161 161
162static void _set_lcd_clock(void) 162static void _set_lcd_clock(void)
163{ 163{
164 unsigned int val; 164 unsigned int val;
165 int pll_div; 165 int pll_div;
166 166
167 __cpm_stop_lcd(); 167 __cpm_stop_lcd();
168 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source, 0:pllout/2 1: pllout */ 168 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source, 0:pllout/2 1: pllout */
169 pll_div = pll_div ? 1 : 2 ; 169 pll_div = pll_div ? 1 : 2 ;
170 val = ( __cpm_get_pllout()/pll_div ) / 336000000; 170 val = ( __cpm_get_pllout()/pll_div ) / 336000000;
171 val--; 171 val--;
172 if ( val > 0x1ff ) 172 if ( val > 0x1ff )
173 val = 0x1ff; /* CPM_LPCDR is too large, set it to 0x1ff */ 173 val = 0x1ff; /* CPM_LPCDR is too large, set it to 0x1ff */
174 __cpm_set_pixdiv(val); 174 __cpm_set_pixdiv(val);
175 __cpm_start_lcd(); 175 __cpm_start_lcd();
176} 176}
177 177