summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAndree Buschmann <AndreeBuschmann@t-online.de>2011-05-22 20:01:07 +0000
committerAndree Buschmann <AndreeBuschmann@t-online.de>2011-05-22 20:01:07 +0000
commitd038f89f3fc403f8a9ef03cd08461988f9c74c59 (patch)
tree820c3c9efc16ecf07f39320864e4068f425f5471
parent6117ffdde52b5ae31bdf3d36277b7a84aec133db (diff)
downloadrockbox-d038f89f3fc403f8a9ef03cd08461988f9c74c59.tar.gz
rockbox-d038f89f3fc403f8a9ef03cd08461988f9c74c59.zip
S5L870x is fast enough to play spc with gaussian interpolation and echo processing.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29914 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--apps/codecs/libspc/spc_codec.h1
-rw-r--r--apps/codecs/libspc/spc_dsp.c2
2 files changed, 2 insertions, 1 deletions
diff --git a/apps/codecs/libspc/spc_codec.h b/apps/codecs/libspc/spc_codec.h
index 391540cb19..caa6860088 100644
--- a/apps/codecs/libspc/spc_codec.h
+++ b/apps/codecs/libspc/spc_codec.h
@@ -51,6 +51,7 @@
51/* Only some targets are fast enough for gaussian and realtime BRR decode */ 51/* Only some targets are fast enough for gaussian and realtime BRR decode */
52#if CONFIG_CPU == S3C2440 || CONFIG_CPU == IMX31L || \ 52#if CONFIG_CPU == S3C2440 || CONFIG_CPU == IMX31L || \
53 CONFIG_CPU == AS3525 || CONFIG_CPU == AS3525v2 || \ 53 CONFIG_CPU == AS3525 || CONFIG_CPU == AS3525v2 || \
54 defined(CPU_S5L870X) || \
54 (CONFIG_PLATFORM & PLATFORM_HOSTED) || MEMORYSIZE <= 2 55 (CONFIG_PLATFORM & PLATFORM_HOSTED) || MEMORYSIZE <= 2
55 /* Don't cache BRR waves */ 56 /* Don't cache BRR waves */
56 #define SPC_BRRCACHE 0 57 #define SPC_BRRCACHE 0
diff --git a/apps/codecs/libspc/spc_dsp.c b/apps/codecs/libspc/spc_dsp.c
index 4b289caeda..c5833e21d6 100644
--- a/apps/codecs/libspc/spc_dsp.c
+++ b/apps/codecs/libspc/spc_dsp.c
@@ -766,7 +766,7 @@ void DSP_run_( struct Spc_Dsp* this, long count, int32_t* out_buf )
766 #if !SPC_NOINTERP 766 #if !SPC_NOINTERP
767 /* Interleved gauss table (to improve cache coherency). */ 767 /* Interleved gauss table (to improve cache coherency). */
768 /* gauss [i * 2 + j] = normal_gauss [(1 - j) * 256 + i] */ 768 /* gauss [i * 2 + j] = normal_gauss [(1 - j) * 256 + i] */
769 static short const gauss [512] ICONST_ATTR_SPC = 769 static short const gauss [512] ICONST_ATTR_SPC MEM_ALIGN_ATTR =
770 { 770 {
771370,1305, 366,1305, 362,1304, 358,1304, 354,1304, 351,1304, 347,1304, 343,1303, 771370,1305, 366,1305, 362,1304, 358,1304, 354,1304, 351,1304, 347,1304, 343,1303,
772339,1303, 336,1303, 332,1302, 328,1302, 325,1301, 321,1300, 318,1300, 314,1299, 772339,1303, 336,1303, 332,1302, 328,1302, 325,1301, 321,1300, 318,1300, 314,1299,