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authorMichael Sevakis <jethead71@rockbox.org>2008-05-16 06:21:11 +0000
committerMichael Sevakis <jethead71@rockbox.org>2008-05-16 06:21:11 +0000
commitcda664b701dcd97c3a05ff1a5fdcfb88f9524761 (patch)
tree05ffd1c395d145365fd73064d2cb25d9e3c836ad
parent16c8f060e6ec444f9af2d41f73543f2e92a016ca (diff)
downloadrockbox-cda664b701dcd97c3a05ff1a5fdcfb88f9524761.tar.gz
rockbox-cda664b701dcd97c3a05ff1a5fdcfb88f9524761.zip
MC13783 (Gigabeat S PMIC): Complete the header file. Distinguish status, sense and mask bit defines to avoid conflicts within the definitions. Much care taken but give a double check before making new use of anything.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17534 a1c6a512-1295-4272-9138-f99709370657
Diffstat
-rw-r--r--firmware/drivers/rtc/rtc_mc13783.c4
-rw-r--r--firmware/export/mc13783.h1419
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/adc-imx31.c2
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/mc13783-imx31.c37
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/usb-imx31.c4
5 files changed, 1064 insertions, 402 deletions
diff --git a/firmware/drivers/rtc/rtc_mc13783.c b/firmware/drivers/rtc/rtc_mc13783.c
index 9f922a10a6..9d2c50cf11 100644
--- a/firmware/drivers/rtc/rtc_mc13783.c
+++ b/firmware/drivers/rtc/rtc_mc13783.c
@@ -254,9 +254,9 @@ bool rtc_check_alarm_flag(void)
254bool rtc_enable_alarm(bool enable) 254bool rtc_enable_alarm(bool enable)
255{ 255{
256 if (enable) 256 if (enable)
257 mc13783_clear(MC13783_INTERRUPT_MASK1, MC13783_TODA); 257 mc13783_clear(MC13783_INTERRUPT_MASK1, MC13783_TODAM);
258 else 258 else
259 mc13783_set(MC13783_INTERRUPT_MASK1, MC13783_TODA); 259 mc13783_set(MC13783_INTERRUPT_MASK1, MC13783_TODAM);
260 260
261 return false; 261 return false;
262} 262}
diff --git a/firmware/export/mc13783.h b/firmware/export/mc13783.h
index 8f1b76cbd5..c8cf67bedb 100644
--- a/firmware/export/mc13783.h
+++ b/firmware/export/mc13783.h
@@ -21,251 +21,919 @@
21 21
22enum mc13783_regs_enum 22enum mc13783_regs_enum
23{ 23{
24 MC13783_INTERRUPT_STATUS0 = 0x00, 24 MC13783_INTERRUPT_STATUS0 = 0,
25 MC13783_INTERRUPT_MASK0, 25 MC13783_INTERRUPT_MASK0 = 1,
26 MC13783_INTERRUPT_SENSE0, 26 MC13783_INTERRUPT_SENSE0 = 2,
27 MC13783_INTERRUPT_STATUS1, 27 MC13783_INTERRUPT_STATUS1 = 3,
28 MC13783_INTERRUPT_MASK1, 28 MC13783_INTERRUPT_MASK1 = 4,
29 MC13783_INTERRUPT_SENSE1, 29 MC13783_INTERRUPT_SENSE1 = 5,
30 MC13783_POWER_UP_MODE_SENSE, 30 MC13783_POWER_UP_MODE_SENSE = 6,
31 MC13783_IDENTIFICATION, 31 MC13783_IDENTIFICATION = 7,
32 MC13783_SEMAPHORE, 32 MC13783_SEMAPHORE = 8,
33 MC13783_ARBITRATION_PERIPHERAL_AUDIO, 33 MC13783_ARBITRATION_PERIPHERAL_AUDIO = 9,
34 MC13783_ARBITRATION_SWITCHERS, 34 MC13783_ARBITRATION_SWITCHERS = 10,
35 MC13783_ARBITRATION_REGULATORS0, 35 MC13783_ARBITRATION_REGULATORS0 = 11,
36 MC13783_ARBITRATION_REGULATORS1, 36 MC13783_ARBITRATION_REGULATORS1 = 12,
37 MC13783_POWER_CONTROL0, 37 MC13783_POWER_CONTROL0 = 13,
38 MC13783_POWER_CONTROL1, 38 MC13783_POWER_CONTROL1 = 14,
39 MC13783_POWER_CONTROL2, 39 MC13783_POWER_CONTROL2 = 15,
40 MC13783_REGEN_ASSIGNMENT, 40 MC13783_REGEN_ASSIGNMENT = 16,
41 MC13783_CONTROL_SPARE, 41 MC13783_CONTROL_SPARE = 17, /* x */
42 MC13783_MEMORYA, 42 MC13783_MEMORYA = 18,
43 MC13783_MEMORYB, 43 MC13783_MEMORYB = 19,
44 MC13783_RTC_TIME, 44 MC13783_RTC_TIME = 20,
45 MC13783_RTC_ALARM, 45 MC13783_RTC_ALARM = 21,
46 MC13783_RTC_DAY, 46 MC13783_RTC_DAY = 22,
47 MC13783_RTC_DAY_ALARM, 47 MC13783_RTC_DAY_ALARM = 23,
48 MC13783_SWITCHERS0, 48 MC13783_SWITCHERS0 = 24,
49 MC13783_SWITCHERS1, 49 MC13783_SWITCHERS1 = 25,
50 MC13783_SWITCHERS2, 50 MC13783_SWITCHERS2 = 26,
51 MC13783_SWITCHERS3, 51 MC13783_SWITCHERS3 = 27,
52 MC13783_SWITCHERS4, 52 MC13783_SWITCHERS4 = 28,
53 MC13783_SWITCHERS5, 53 MC13783_SWITCHERS5 = 29,
54 MC13783_REGULATOR_SETTING0, 54 MC13783_REGULATOR_SETTING0 = 30,
55 MC13783_REGULATOR_SETTING1, 55 MC13783_REGULATOR_SETTING1 = 31,
56 MC13783_REGULATOR_MODE0, 56 MC13783_REGULATOR_MODE0 = 32,
57 MC13783_REGULATOR_MODE1, 57 MC13783_REGULATOR_MODE1 = 33,
58 MC13783_POWER_MISCELLANEOUS, 58 MC13783_POWER_MISCELLANEOUS = 34,
59 MC13783_POWER_SPARE, 59 MC13783_POWER_SPARE = 35, /* x */
60 MC13783_AUDIO_RX0, 60 MC13783_AUDIO_RX0 = 36,
61 MC13783_AUDIO_RX1, 61 MC13783_AUDIO_RX1 = 37,
62 MC13783_AUDIO_TX, 62 MC13783_AUDIO_TX = 38,
63 MC13783_SSI_NETWORK, 63 MC13783_SSI_NETWORK = 39,
64 MC13783_AUDIO_CODEC, 64 MC13783_AUDIO_CODEC = 40,
65 MC13783_AUDIO_STEREO_CODEC, 65 MC13783_AUDIO_STEREO_DAC = 41,
66 MC13783_AUDIO_SPARE, 66 MC13783_AUDIO_SPARE = 42, /* x */
67 MC13783_ADC0, 67 MC13783_ADC0 = 43,
68 MC13783_ADC1, 68 MC13783_ADC1 = 44,
69 MC13783_ADC2, 69 MC13783_ADC2 = 45,
70 MC13783_ADC3, 70 MC13783_ADC3 = 46,
71 MC13783_ADC4, 71 MC13783_ADC4 = 47,
72 MC13783_CHARGER, 72 MC13783_CHARGER = 48,
73 MC13783_USB0, 73 MC13783_USB0 = 49,
74 MC13783_CHARGER_USB1, 74 MC13783_CHARGER_USB1 = 50,
75 MC13783_LED_CONTROL0, 75 MC13783_LED_CONTROL0 = 51,
76 MC13783_LED_CONTROL1, 76 MC13783_LED_CONTROL1 = 52,
77 MC13783_LED_CONTROL2, 77 MC13783_LED_CONTROL2 = 53,
78 MC13783_LED_CONTROL3, 78 MC13783_LED_CONTROL3 = 54,
79 MC13783_LED_CONTROL4, 79 MC13783_LED_CONTROL4 = 55,
80 MC13783_LED_CONTROL5, 80 MC13783_LED_CONTROL5 = 56,
81 MC13783_SPARE, 81 MC13783_SPARE = 57, /* x */
82 MC13783_TRIM0, 82 MC13783_TRIM0 = 58, /* x */
83 MC13783_TRIM1, 83 MC13783_TRIM1 = 59, /* x */
84 MC13783_TEST0, 84 MC13783_TEST0 = 60, /* x */
85 MC13783_TEST1, 85 MC13783_TEST1 = 61, /* x */
86 MC13783_TEST2, 86 MC13783_TEST2 = 62, /* x */
87 MC13783_TEST3, 87 MC13783_TEST3 = 63, /* x */
88 MC13783_NUM_REGS, 88 MC13783_NUM_REGS = 64,
89}; 89};
90/* x = unused/reserved/not implemented */
90 91
91/* INTERRUPT_STATUS0, INTERRUPT_MASK0, INTERRUPT_SENSE0 */ 92/* INTERRUPT_STATUS0 (0) */
92#define MC13783_ADCDONE (1 << 0) /* x */ 93#define MC13783_ADCDONEI (0x1 << 0)
93#define MC13783_ADCBISDONE (1 << 1) /* x */ 94#define MC13783_ADCBISDONEI (0x1 << 1)
94#define MC13783_TS (1 << 2) /* x */ 95#define MC13783_TSI (0x1 << 2)
95#define MC13783_WHIGH (1 << 3) /* x */ 96#define MC13783_WHIGHI (0x1 << 3)
96#define MC13783_WLOW (1 << 4) /* x */ 97#define MC13783_WLOWI (0x1 << 4)
97#define MC13783_CHGDET (1 << 6) 98#define MC13783_CHGDETI (0x1 << 6)
98#define MC13783_CHGOV (1 << 7) 99#define MC13783_CHGOVI (0x1 << 7)
99#define MC13783_CHGREV (1 << 8) 100#define MC13783_CHGREVI (0x1 << 8)
100#define MC13783_CHGSHORT (1 << 9) 101#define MC13783_CHGSHORTI (0x1 << 9)
101#define MC13783_CCCV (1 << 10) 102#define MC13783_CCCVI (0x1 << 10)
102#define MC13783_CHGCURR (1 << 11) 103#define MC13783_CHGCURRI (0x1 << 11)
103#define MC13783_BPONI (1 << 12) 104#define MC13783_BPONII (0x1 << 12)
104#define MC13783_LOBATL (1 << 13) 105#define MC13783_LOBATLI (0x1 << 13)
105#define MC13783_LOBATH (1 << 14) 106#define MC13783_LOBATHI (0x1 << 14)
106#define MC13783_UDP (1 << 15) 107#define MC13783_UDPI (0x1 << 15)
107#define MC13783_USB4V4 (1 << 16) 108#define MC13783_USB4V4I (0x1 << 16)
108#define MC13783_USB2V0 (1 << 17) 109#define MC13783_USB2V0I (0x1 << 17)
109#define MC13783_USB0V8 (1 << 18) 110#define MC13783_USB0V8I (0x1 << 18)
110#define MC13783_IDFLOAT (1 << 19) 111#define MC13783_IDFLOATI (0x1 << 19)
111#define MC13783_SE1 (1 << 21) 112#define MC13783_SE1I (0x1 << 21)
112#define MC13783_CKDET (1 << 22) 113#define MC13783_CKDETI (0x1 << 22)
113#define MC13783_UDM (1 << 23) 114#define MC13783_UDMI (0x1 << 23)
114/* x = no sense bit */ 115
115 116/* INTERRUPT_MASK0 (1) */
116/* INTERRUPT_STATUS1, INTERRUPT_MASK1, INTERRUPT_SENSE1 */ 117#define MC13783_ADCDONEM (0x1 << 0)
117#define MC13783_1HZ (1 << 0) /* x */ 118#define MC13783_ADCBISDONEM (0x1 << 1)
118#define MC13783_TODA (1 << 1) /* x */ 119#define MC13783_TSM (0x1 << 2)
119#define MC13783_ONOFD1 (1 << 3) /* ON1B */ 120#define MC13783_WHIGHM (0x1 << 3)
120#define MC13783_ONOFD2 (1 << 4) /* ON2B */ 121#define MC13783_WLOWM (0x1 << 4)
121#define MC13783_ONOFD3 (1 << 5) /* ON3B */ 122#define MC13783_CHGDETM (0x1 << 6)
122#define MC13783_SYSRST (1 << 6) /* x */ 123#define MC13783_CHGOVM (0x1 << 7)
123#define MC13783_RTCRST (1 << 7) /* x */ 124#define MC13783_CHGREVM (0x1 << 8)
124#define MC13783_PCI (1 << 8) /* x */ 125#define MC13783_CHGSHORTM (0x1 << 9)
125#define MC13783_WARM (1 << 9) /* x */ 126#define MC13783_CCCVM (0x1 << 10)
126#define MC13783_MEMHLD (1 << 10) /* x */ 127#define MC13783_CHGCURRM (0x1 << 11)
127#define MC13783_PWRRDY (1 << 11) 128#define MC13783_BPONIM (0x1 << 12)
128#define MC13783_THWARNL (1 << 12) 129#define MC13783_LOBATLM (0x1 << 13)
129#define MC13783_THWARNH (1 << 13) 130#define MC13783_LOBATHM (0x1 << 14)
130#define MC13783_CLK (1 << 14) 131#define MC13783_UDPM (0x1 << 15)
131#define MC13783_SEMAF (1 << 15) /* x */ 132#define MC13783_USB4V4M (0x1 << 16)
132#define MC13783_MC2B (1 << 17) 133#define MC13783_USB2V0M (0x1 << 17)
133#define MC13783_HSDET (1 << 18) 134#define MC13783_USB0V8M (0x1 << 18)
134#define MC13783_HSL (1 << 19) 135#define MC13783_IDFLOATM (0x1 << 19)
135#define MC13783_ALSPTH (1 << 20) 136#define MC13783_SE1M (0x1 << 21)
136#define MC13783_AHSSHORT (1 << 21) 137#define MC13783_CKDETM (0x1 << 22)
137/* x = no sense bit */ 138#define MC13783_UDMM (0x1 << 23)
138 139
139/* POWER_UP_MODE_SENSE */ 140/* INTERRUPT_SENSE0 (2) */
140 141#define MC13783_CHGDETS (0x1 << 6)
141#define MC13783_ICTESTS (1 << 0) 142#define MC13783_CHGOVS (0x1 << 7)
142#define MC13783_CLKSELS (1 << 1) 143#define MC13783_CHGREVS (0x1 << 8)
143#define MC13783_PUMS1Sr(r) (((r) >> 2) & 0x3) 144#define MC13783_CHGSHORTS (0x1 << 9)
144#define MC13783_PUMS2S (((r) >> 4) & 0x3) 145#define MC13783_CCCVS (0x1 << 10)
145#define MC13783_PUMS3S (((r) >> 6) & 0x3) 146#define MC13783_CHGCURRS (0x1 << 11)
146 #define PUMS_LOW 0x0 147#define MC13783_BPONIS (0x1 << 12)
147 #define PUMS_OPEN 0x1 148#define MC13783_LOBATLS (0x1 << 13)
148 #define PUMS_HIGH 0x2 149#define MC13783_LOBATHS (0x1 << 14)
149#define MC13783_CHRGMOD0Sr(r) (((r) >> 8) & 0x3) 150#define MC13783_UDPS (0x1 << 15)
150#define MC13783_CHRGMOD1Sr(r) (((r) >> 10) & 0x3) 151#define MC13783_USB4V4S (0x1 << 16)
151 #define CHRGMOD_LOW 0x0 152#define MC13783_USB2V0S (0x1 << 17)
152 #define CHRGMOD_OPEN 0x1 153#define MC13783_USB0V8S (0x1 << 18)
153 #define CHRGMOD_HIGH 0x3 154#define MC13783_IDFLOATS (0x1 << 19)
154#define MC13783_UMODSr(r) (((r) >> 12) & 0x3) 155#define MC13783_SE1S (0x1 << 21)
155 #define UMODS0_LOW_UMODS1_LOW 0x0 156#define MC13783_CKDETS (0x1 << 22)
156 #define UMODS0_OPEN_UMODS1_LOW 0x1 157#define MC13783_UDMS (0x1 << 23)
157 #define UMODS0_DONTCARE_UMODS1_HIGH 0x2 158
158 #define UMODS0_HIGH_UMODS1_LOW 0x3 159/* INTERRUPT_STATUS1 (3) */
159#define MC13783_USBEN (1 << 14) 160#define MC13783_1HZI (0x1 << 0)
160#define MC13783_SW1ABS (1 << 15) 161#define MC13783_TODAI (0x1 << 1)
161#define MC13783_SW2ABS (1 << 16) 162#define MC13783_ONOFD1I (0x1 << 3) /* ON1B */
162 163#define MC13783_ONOFD2I (0x1 << 4) /* ON2B */
163/* IDENTIFICATION */ 164#define MC13783_ONOFD3I (0x1 << 5) /* ON3B */
164/* SEMAPHORE */ 165#define MC13783_SYSRSTI (0x1 << 6)
165/* ARBITRATION_PERIPHERAL_AUDIO */ 166#define MC13783_RTCRSTI (0x1 << 7)
166/* ARBITRATION_SWITCHERS */ 167#define MC13783_PCII (0x1 << 8)
167/* ARBITRATION_REGULATORS0 */ 168#define MC13783_WARMI (0x1 << 9)
168/* ARBITRATION_REGULATORS1 */ 169#define MC13783_MEMHLDI (0x1 << 10)
169 170#define MC13783_PWRRDYI (0x1 << 11)
170/* POWER_CONTROL0 */ 171#define MC13783_THWARNLI (0x1 << 12)
171#define MC13783_USEROFFSPI (1 << 3) 172#define MC13783_THWARNHI (0x1 << 13)
172 173#define MC13783_CLKI (0x1 << 14)
173/* POWER_CONTROL1 */ 174#define MC13783_SEMAFI (0x1 << 15)
174/* POWER_CONTROL2 */ 175#define MC13783_MC2BI (0x1 << 17)
175/* REGEN_ASSIGNMENT */ 176#define MC13783_HSDETI (0x1 << 18)
176/* MEMORYA */ 177#define MC13783_HSLI (0x1 << 19)
177/* MEMORYB */ 178#define MC13783_ALSPTHI (0x1 << 20)
178/* RTC_TIME */ 179#define MC13783_AHSSHORTI (0x1 << 21)
179/* RTC_ALARM */ 180
180/* RTC_DAY */ 181/* INTERRUPT_MASK1 (4) */
181/* RTC_DAY_ALARM */ 182#define MC13783_1HZM (0x1 << 0)
182/* SWITCHERS0 */ 183#define MC13783_TODAM (0x1 << 1)
183/* SWITCHERS1 */ 184#define MC13783_ONOFD1M (0x1 << 3) /* ON1B */
184/* SWITCHERS2 */ 185#define MC13783_ONOFD2M (0x1 << 4) /* ON2B */
185/* SWITCHERS3 */ 186#define MC13783_ONOFD3M (0x1 << 5) /* ON3B */
186/* SWITCHERS4 */ 187#define MC13783_SYSRSTM (0x1 << 6)
187/* SWITCHERS5 */ 188#define MC13783_RTCRSTM (0x1 << 7)
188/* REGULATOR_SETTING0 */ 189#define MC13783_PCIM (0x1 << 8)
189/* REGULATOR_SETTING1 */ 190#define MC13783_WARMM (0x1 << 9)
190/* REGULATOR_MODE0 */ 191#define MC13783_MEMHLDM (0x1 << 10)
191/* REGULATOR_MODE1 */ 192#define MC13783_PWRRDYM (0x1 << 11)
192/* POWER_MISCELLANEOUS */ 193#define MC13783_THWARNLM (0x1 << 12)
193/* AUDIO_RX0 */ 194#define MC13783_THWARNHM (0x1 << 13)
194/* AUDIO_RX1 */ 195#define MC13783_CLKM (0x1 << 14)
195/* AUDIO_TX */ 196#define MC13783_SEMAFM (0x1 << 15)
196/* SSI_NETWORK */ 197#define MC13783_MC2BM (0x1 << 17)
197/* AUDIO_CODEC */ 198#define MC13783_HSDETM (0x1 << 18)
198/* AUDIO_STEREO_CODEC */ 199#define MC13783_HSLM (0x1 << 19)
199 200#define MC13783_ALSPTHM (0x1 << 20)
200/* ADC0 */ 201#define MC13783_AHSSHORTM (0x1 << 21)
201#define MC13783_LICELLCON (1 << 0) 202
202#define MC13783_CHRGICON (1 << 1) 203/* INTERRUPT_SENSE1 (5) */
203#define MC13783_BATICON (1 << 2) 204#define MC13783_ONOFD1S (0x1 << 3) /* ON1B */
204#define MC13783_RTHEN (1 << 3) 205#define MC13783_ONOFD2S (0x1 << 4) /* ON2B */
205#define MC13783_DTHEN (1 << 4) 206#define MC13783_ONOFD3S (0x1 << 5) /* ON3B */
206#define MC13783_UIDEN (1 << 5) 207#define MC13783_PWRRDYS (0x1 << 11)
207#define MC13783_ADOUTEN (1 << 6) 208#define MC13783_THWARNLS (0x1 << 12)
208#define MC13783_ADOUTPER (1 << 7) 209#define MC13783_THWARNHS (0x1 << 13)
209#define MC13783_ADREFEN (1 << 10) 210#define MC13783_CLKS (0x1 << 14)
210#define MC13783_ADREFMODE (1 << 11) 211#define MC13783_MC2BS (0x1 << 17)
211#define MC13783_TSMODw(w) ((w) << 12) 212#define MC13783_HSDETS (0x1 << 18)
212#define MC13783_TSMODr(r) (((r) >> 12) & 0x3) 213#define MC13783_HSLS (0x1 << 19)
213#define MC13783_CHRGRAWDIV (1 << 15) 214#define MC13783_ALSPTHS (0x1 << 20)
214#define MC13783_ADINC1 (1 << 16) 215#define MC13783_AHSSHORTS (0x1 << 21)
215#define MC13783_ADINC2 (1 << 17) 216
216#define MC13783_WCOMP (1 << 18) 217/* POWER_UP_MODE_SENSE (6) */
217#define MC13783_ADCBIS0 (1 << 23) 218#define MC13783_ICTESTS (0x1 << 0)
218 219#define MC13783_CLKSELS (0x1 << 1)
219/* ADC1 */ 220#define MC13783_PUMS1S (0x3 << 2)
220#define MC13783_ADEN (1 << 0) 221 #define MC13783_PUMS1S_LOW (0x0 << 2)
221#define MC13783_RAND (1 << 1) 222 #define MC13783_PUMS1S_OPEN (0x1 << 2)
222#define MC13783_ADSEL (1 << 3) 223 #define MC13783_PUMS1S_HIGH (0x2 << 2)
223#define MC13783_TRIGMASK (1 << 4) 224#define MC13783_PUMS2S (0x3 << 4)
224#define MC13783_ADA1w(w) ((w) << 5) 225 #define MC13783_PUMS2S_LOW (0x0 << 4)
225#define MC13783_ADA1r(r) (((r) >> 5) & 0x3) 226 #define MC13783_PUMS2S_OPEN (0x1 << 4)
226#define MC13783_ADA2w(w) ((w) << 8) 227 #define MC13783_PUMS2S_HIGH (0x2 << 4)
227#define MC13783_ADA2r(r) (((r) >> 8) & 0x3) 228#define MC13783_PUMS3S (0x3 << 6)
228#define MC13783_ATOw(w) ((w) << 11) 229 #define MC13783_PUMS3S_LOW (0x0 << 6)
229#define MC13783_ATOr(r) (((r) >> 11) & 0xff) 230 #define MC13783_PUMS3S_OPEN (0x1 << 6)
230#define MC13783_ATOX (1 << 19) 231 #define MC13783_PUMS3S_HIGH (0x2 << 6)
231#define MC13783_ASC (1 << 20) 232#define MC13783_CHRGMOD0S (0x3 << 8)
232#define MC13783_ADTRIGIGN (1 << 21) 233 #define MC13783_CHRGMOD0S_LOW (0x0 << 8)
233#define MC13783_ADONESHOT (1 << 22) 234 #define MC13783_CHRGMOD0S_OPEN (0x1 << 8)
234#define MC13783_ADCBIS1 (1 << 23) 235 #define MC13783_CHRGMOD0S_HIGH (0x3 << 8)
235 236#define MC13783_CHRGMOD1S (0x3 << 10)
236/* ADC2 */ 237 #define MC13783_CHRGMOD1S_LOW (0x0 << 10)
237#define MC13783_ADD1r(r) (((r) >> 2) & 0x3ff) 238 #define MC13783_CHRGMOD1S_OPEN (0x1 << 10)
238#define MC13783_ADD2r(r) (((r) >> 14) & 0x3ff) 239 #define MC13783_CHRGMOD1S_HIGH (0x3 << 10)
239 240#define MC13783_UMODS (0x3 << 12)
240/* ADC3 */ 241 #define MC13783_UMODS_LOW_UMODS1_LOW (0x0 << 12)
241#define MC13783_WHIGHw(w) ((w) << 0) 242 #define MC13783_UMODS_OPEN_UMODS1_LOW (0x1 << 12)
242#define MC13783_WHIGHr(r) ((r) & 0x3f) 243 #define MC13783_UMODS_DONTCARE_UMODS1_HIGH (0x2 << 12)
243#define MC13783_ICIDr(r) (((r) >> 6) & 0x3) 244 #define MC13783_UMODS_HIGH_UMODS1_LOW (0x3 << 12)
244#define MC13783_WLOWw(w) ((w) << 9) 245#define MC13783_USBENS (0x1 << 14)
245#define MC13783_WLOWr(r) (((r) >> 9) & 0x3f) 246#define MC13783_SW1ABS (0x1 << 15)
246#define MC13783_ADCBIS2 (1 << 23) 247#define MC13783_SW2ABS (0x1 << 16)
247 248
248/* ADC4 */ 249/* IDENTIFICATION (7) */
249#define MC13783_ADCBIS1r(r) (((r) >> 2) & 0x3ff) 250#define MC13783_REVISION (0x1f << 0)
250#define MC13783_ADCBIS2r(r) (((r) >> 14) & 0x3ff) 251 #define MC13783_REVISIONr(x) (((x) & MC13783_REVISION) >> 0)
251 252#define MC13783_ICID (0x7 << 6)
252/* CHARGER */ 253 #define MC13783_ICIDr(x) (((x) & MC13783_ICID) >> 6)
253/* USB0 */ 254#define MC13783_FIN (0x3 << 9)
254/* CHARGER_USB1 */ 255 #define MC13783_FINr(x) (((x) & MC13783_FIN) >> 9))
255 256#define MC13783_FAB (0x3 << 12)
256/* LED_CONTROL0 */ 257 #define MC13783_FABr(x) (((x) & MC13783_FAB) >> 12))
257#define MC13783_LEDEN (0x1 << 0) 258
258#define MC13783_LEDMDRAMPUP (0x1 << 1) 259/* SEMAPHORE (8) */
259#define MC13783_LEDADRAMPUP (0x1 << 2) 260#define MC13783_SEMCTRLA (0x1 << 0)
260#define MC13783_LEDKDRAMPUP (0x1 << 3) 261#define MC13783_SEMCTRLB (0x1 << 2)
261#define MC13783_LEDMDRAMPDOWN (0x1 << 4) 262#define MC13783_SEMWRTA (0xf << 4)
262#define MC13783_LEDADRAMPDOWN (0x1 << 5) 263 #define MC13783_SEMWRTAw(x) (((x) << 4) & MC13783_SEMWRTA)
263#define MC13783_LEDKDRAMPDOWN (0x1 << 6) 264 #define MC13783_SEMWRTAr(x) (((x) & MC13783_SEMWRTA) >> 4)
264#define MC13783_TRIODEMD (0x1 << 7) 265#define MC13783_SEMWRTB (0x3f << 8)
265#define MC13783_TRIODEAD (0x1 << 8) 266 #define MC13783_SEMWRTBw(x) (((x) << 8) & MC13783_SEMWRTB)
266#define MC13783_TRIODEKD (0x1 << 9) 267 #define MC13783_SEMWRTBr(x) (((x) & MC13783_SEMWRTB) >> 8)
267#define MC13783_BOOSTEN (0x1 << 10) 268#define MC13783_SEMRDA (0xf << 14)
268#define MC13783_ABMODE (0x7 << 11) 269 #define MC13783_SEMRDAw(x) (((x) << 14) & MC13783_SEMRDA)
270 #define MC13783_SEMRDAr(x) (((x) & MC13783_SEMRDA) >> 14)
271#define MC13783_SEMRDB (0x3f << 18)
272 #define MC13783_SEMRDBw(x) (((x) << 18) & MC13783_SEMRDB)
273 #define MC13783_SEMRDBr(x) (((x) & MC13783_SEMRDB) >> 18)
274
275/* ARBITRATION_PERIPHERAL_AUDIO (9) */
276#define MC13783_AUDIOTXSEL (0x3 << 0)
277 #define MC13783_AUDIOTXSEL_PRI_SPI (0x0 << 0)
278 #define MC13783_AUDIOTXSEL_SEC_SPI (0x1 << 0)
279 #define MC13783_AUDIOTXSEL_OR_SPI (0x2 << 0)
280 #define MC13783_AUDIOTXSEL_AND_SPI (0x3 << 0)
281#define MC13783_TXGAINSEL (0x1 << 2)
282#define MC13783_AUDIORXSEL (0x3 << 3)
283 #define MC13783_AUDIORXSEL_PRI_SPI (0x0 << 3)
284 #define MC13783_AUDIORXSEL_SEC_SPI (0x1 << 3)
285 #define MC13783_AUDIORXSEL_OR_SPI (0x2 << 3)
286 #define MC13783_AUDIORXSEL_AND_SPI (0x3 << 3)
287#define MC13783_RXGAINSEL (0x1 << 5)
288#define MC13783_AUDIOCDCSEL (0x1 << 6)
289#define MC13783_AUDIOSTDCSEL (0x1 << 7)
290#define MC13783_BIASSEL (0x3 << 8)
291 #define MC13783_BIASSEL_PRI_SPI (0x0 << 8)
292 #define MC13783_BIASSEL_SEC_SPI (0x1 << 8)
293 #define MC13783_BIASSEL_OR_SPI (0x2 << 8)
294 #define MC13783_BIASSEL_AND_SPI (0x3 << 8)
295#define MC13783_RTCSEL (0x1 << 11)
296#define MC13783_ADCSEL (0x3 << 12)
297 #define MC13783_ADCSEL_PRI1_SEC1 (0x0 << 12)
298 #define MC13783_ADCSEL_PRI2_SEC0 (0x1 << 12)
299 #define MC13783_ADCSEL_PRI0_SEC2 (0x2 << 12)
300 /* 0x3 = same as 0x0 */
301#define MC13783_USBSEL (0x1 << 14)
302#define MC13783_CHRGSEL (0x1 << 15)
303#define MC13783_BLLEDSEL (0x1 << 16)
304#define MC13783_TCLEDSEL (0x1 << 17)
305#define MC13783_ADAPTSEL (0x1 << 18)
306
307/* ARBITRATION_SWITCHERS (10) */
308#define MC13783_SW1ASTBYAND (0x1 << 0)
309#define MC13783_SW1BSTBYAND (0x1 << 1)
310#define MC13783_SW2ASTBYAND (0x1 << 2)
311#define MC13783_SW2BSTBYAND (0x1 << 3)
312#define MC13783_SW3SEL0 (0x1 << 4)
313#define MC13783_SW1ABDVS (0x1 << 5)
314#define MC13783_SW2ABDVS (0x1 << 6)
315#define MC13783_SW1ASEL (0x1 << 7)
316#define MC13783_SW1BSEL (0x1 << 8)
317#define MC13783_SW2ASEL (0x1 << 9)
318#define MC13783_SW2BSEL (0x1 << 10)
319#define MC13783_PLLSEL (0x1 << 12)
320#define MC13783_PWGT1SEL (0x1 << 14)
321#define MC13783_PWGT2SEL (0x1 << 15)
322
323/* ARBITRATION_REGULATORS0 (11) */
324#define MC13783_VAUDIOSEL (0x3 << 0)
325 #define MC13783_VAUDIOSEL_PRI (0x0 << 0)
326#define MC13783_VIOHISEL (0x3 << 2)
327 #define MC13783_VIOHISEL_PRI (0x0 << 2)
328#define MC13783_VIOLOSEL (0x3 << 4)
329 #define MC13783_VIOLOSEL_PRI (0x0 << 4)
330#define MC13783_VDIGSEL (0x3 << 6)
331 #define MC13783_VDIGSEL_PRI (0x0 << 6)
332#define MC13783_VGENSEL (0x3 << 8)
333 #define MC13783_VGENSEL_PRI (0x0 << 8)
334#define MC13783_VRFDIGSEL (0x3 << 10)
335 #define MC13783_VRFDIGSEL_PRI (0x0 << 10)
336#define MC13783_VRFREFSEL (0x3 << 12)
337 #define MC13783_VRFREFSEL_PRI (0x0 << 12)
338#define MC13783_VRFCPSEL (0x3 << 14)
339 #define MC13783_VRFCPSEL_PRI (0x0 << 14)
340#define MC13783_VSIMSEL (0x3 << 16)
341 #define MC13783_VSIMSEL_PRI (0x0 << 16)
342#define MC13783_VESIMSEL (0x3 << 18)
343 #define MC13783_VESIMSEL_PRI (0x0 << 18)
344#define MC13783_VCAMSEL (0x3 << 20)
345 #define MC13783_VCAMSEL_PRI (0x0 << 20)
346#define MC13783_VRFBGSEL (0x3 << 22)
347 #define MC13783_VRFBGSEL_PRI (0x0 << 22)
348
349/* ARBITRATION_REGULATORS1 (12) */
350#define MC13783_VVIBSEL (0x3 << 0)
351 #define MC13783_VVIBSEL_PRI (0x0 << 0)
352#define MC13783_VRF1SEL (0x3 << 2)
353 #define MC13783_VRF1SEL_PRI (0x0 << 2)
354#define MC13783_VRF2SEL (0x3 << 4)
355 #define MC13783_VRF2SEL_PRI (0x0 << 4)
356#define MC13783_VMMC1SEL (0x3 << 6)
357 #define MC13783_VMMC1SEL_PRI (0x0 << 6)
358#define MC13783_VMMC2SEL (0x3 << 8)
359 #define MC13783_VMMC2SEL_PRI (0x0 << 8)
360#define MC13783_GPO1SEL (0x3 << 14)
361 #define MC13783_GPO1SEL_PRI (0x0 << 14)
362 #define MC13783_GPO1SEL_BOTH (0x1 << 14)
363 #define MC13783_GPO1SEL_AND (0x3 << 14)
364#define MC13783_GPO2SEL (0x3 << 16)
365 #define MC13783_GPO2SEL_PRI (0x0 << 16)
366 #define MC13783_GPO2SEL_BOTH (0x1 << 16)
367 #define MC13783_GPO2SEL_AND (0x3 << 16)
368#define MC13783_GPO3SEL (0x3 << 18)
369 #define MC13783_GPO3SEL_PRI (0x0 << 18)
370 #define MC13783_GPO3SEL_BOTH (0x1 << 18)
371 #define MC13783_GPO3SEL_AND (0x3 << 18)
372#define MC13783_GPO4SEL (0x3 << 20)
373 #define MC13783_GPO4SEL_PRI (0x0 << 20)
374 #define MC13783_GPO4SEL_BOTH (0x1 << 20)
375 #define MC13783_GPO4SEL_AND (0x3 << 20)
376
377/* POWER_CONTROL0 (13) */
378#define MC13783_PCEN (0x1 << 0)
379#define MC13783_PCCOUNTEN (0x1 << 1)
380#define MC13783_WARMEN (0x1 << 2)
381#define MC13783_USEROFFSPI (0x1 << 3)
382#define MC13783_USEROFFPC (0x1 << 4)
383#define MC13783_USEROFFCLK (0x1 << 5)
384#define MC13783_CLK32KMCUEN (0x1 << 6)
385#define MC13783_VBKUP2AUTOMH (0x1 << 7)
386#define MC13783_VBKUP1EN (0x1 << 8)
387#define MC13783_VBKUPAUTO (0x1 << 9)
388#define MC13783_VBKUP1 (0x3 << 10)
389 #define MC13783_VBKUP1_1_0V (0x0 << 10)
390 #define MC13783_VBKUP1_1_2V (0x1 << 10)
391 #define MC13783_VBKUP1_1_575V (0x2 << 10)
392 #define MC13783_VBKUP1_1_8V (0x3 << 10)
393#define MC13783_VBKUP2EN (0x1 << 12)
394#define MC13783_VBKUP2AUTO (0x1 << 13)
395#define MC13783_VBKUP2 (0x3 << 14)
396 #define MC13783_VBKUP2_1_0V (0x0 << 10)
397 #define MC13783_VBKUP2_1_2V (0x1 << 10)
398 #define MC13783_VBKUP2_1_5V (0x2 << 10)
399 #define MC13783_VBKUP2_1_8V (0x3 << 10)
400#define MC13783_BPDET (0x3 << 16)
401 /* 00: UVDET 2.6, LOBATL UVDET+0.2, LOBATH UVDET+0.4 BPON 3.2 */
402 #define MC13783_BPDET_2_4 (0x0 << 16)
403 /* 01: UVDET 2.6, LOBATL UVDET+0.3, LOBATH UVDET+0.5 BPON 3.2 */
404 #define MC13783_BPDET_3_5 (0x1 << 16)
405 /* 10: UVDET 2.6, LOBATL UVDET+0.4, LOBATH UVDET+0.7 BPON 3.2 */
406 #define MC13783_BPDET_4_7 (0x2 << 16)
407 /* 11: UVDET 2.6, LOBATL UVDET+0.5, LOBATH UVDET+0.8 BPON 3.2 */
408 #define MC13783_BPDET_5_8 (0x3 << 16)
409#define MC13783_EOLSEL (0x1 << 18)
410#define MC13783_BATTDETEN (0x1 << 19)
411#define MC13783_VCOIN (0x7 << 20)
412 #define MC13783_VCOIN_2_50V (0x0 << 20)
413 #define MC13783_VCOIN_2_70V (0x1 << 20)
414 #define MC13783_VCOIN_2_80V (0x2 << 20)
415 #define MC13783_VCOIN_2_90V (0x3 << 20)
416 #define MC13783_VCOIN_3_00V (0x4 << 20)
417 #define MC13783_VCOIN_3_10V (0x5 << 20)
418 #define MC13783_VCOIN_3_20V (0x6 << 20)
419 #define MC13783_VCOIN_3_30V (0x7 << 20)
420#define MC13783_COINCHEN (0x1 << 23)
421
422/* POWER_CONTROL1 (14) */
423#define MC13783_PCT (0xff << 0)
424 /* Up to 8 seconds */
425 #define MC13783_PCTw(x) (((x) << 0) & MC13783_PCT)
426 #define MC13783_PCTr(x) (((x) & MC13783_PCT) >> 0)
427#define MC13783_PCCOUNT (0xf << 8)
428 #define MC13783_PCCOUNTw(x) (((x) << 8) & MC13783_PCCOUNT)
429 #define MC13783_PCCOUNTr(x) (((x) & MC13783_PCCOUNT) >> 8)
430#define MC13783_PCMAXCNT (0xf << 12)
431 #define MC13783_PCMAXCNTw(x) (((x) << 12) & MC13783_PCMAXCNT)
432 #define MC13783_PCMAXCNTr(x) (((x) & MC13783_PCMAXCNT) >> 12)
433#define MC13783_MEMTMR (0xf << 16)
434 /* Up to 8 minutes with MEMALLON=0, <> 0 + MEMALLON=1: infinite */
435 #define MC13783_MEMTMRw(x) (((x) << 16) & MC13783_MEMTMR)
436 #define MC13783_MEMTMRr(x) (((x) & MC13783_MEMTMR) >> 16)
437#define MC13783_MEMALLON (0x1 << 20)
438
439/* POWER_CONTROL2 (15) */
440#define MC13783_RESTARTEN (0x1 << 0)
441#define MC13783_ON1BRSTEN (0x1 << 1)
442#define MC13783_ON2BRSTEN (0x1 << 2)
443#define MC13783_ON3BTSTEN (0x1 << 3)
444#define MC13783_ON1BDBNC (0x3 << 4)
445 #define MC13783_ON1BDBNC_0MS (0x0 << 4)
446 #define MC13783_ON1BDBNC_30MS (0x1 << 4)
447 #define MC13783_ON1BDBNC_150MS (0x2 << 4)
448 #define MC13783_ON1BDBNC_750MS (0x3 << 4)
449#define MC13783_ON2BDBNC (0x3 << 6)
450 #define MC13783_ON2BDBNC_0MS (0x0 << 6)
451 #define MC13783_ON2BDBNC_30MS (0x1 << 6)
452 #define MC13783_ON2BDBNC_150MS (0x2 << 6)
453 #define MC13783_ON2BDBNC_750MS (0x3 << 6)
454#define MC13783_ON3BDBNC (0x3 << 8)
455 #define MC13783_ON3BDBNC_0MS (0x0 << 8)
456 #define MC13783_ON3BDBNC_30MS (0x1 << 8)
457 #define MC13783_ON3BDBNC_150MS (0x2 << 8)
458 #define MC13783_ON3BDBNC_750MS (0x3 << 8)
459#define MC13783_STANDBYPRIINV (0x1 << 10)
460#define MC13783_STANDBYSECINV (0x1 << 11)
461
462/* REGEN_ASSIGNMENT (16) */
463#define MC13783_VAUDIOREGEN (0x1 << 0)
464#define MC13783_VIOHIREGEN (0x1 << 1)
465#define MC13783_VIOLOREGEN (0x1 << 2)
466#define MC13783_VDIGREGEN (0x1 << 3)
467#define MC13783_VGENREGEN (0x1 << 4)
468#define MC13783_VRFDIGREGEN (0x1 << 5)
469#define MC13783_VRFREFREGEN (0x1 << 6)
470#define MC13783_VRFCPREGEN (0x1 << 7)
471#define MC13783_VCAMREGEN (0x1 << 8)
472#define MC13783_VRFBGREGEN (0x1 << 9)
473#define MC13783_VRF1REGEN (0x1 << 10)
474#define MC13783_VRF2REGEN (0x1 << 11)
475#define MC13783_VMMC1REGEN (0x1 << 12)
476#define MC13783_VMMC2REGEN (0x1 << 13)
477#define MC13783_GPO1REGEN (0x1 << 16)
478#define MC13783_GPO2REGEN (0x1 << 17)
479#define MC13783_GPO3REGEN (0x1 << 18)
480#define MC13783_GPO4REGEN (0x1 << 19)
481#define MC13783_REGENINV (0x1 << 20)
482#define MC13783_VESIMESIMEN (0x1 << 21)
483#define MC13783_VMMC1ESIMEN (0x1 << 22)
484#define MC13783_VMMC2ESIMEN (0x1 << 23)
485
486/* MEMORYA (18) */
487#define MC13783_MEMORYA_MASK (0xffffff)
488
489/* MEMORYB (19) */
490#define MC13783_MEMORYB_MASK (0xffffff)
491
492/* RTC_TIME (20) */
493#define MC13783_RTC_TIME_MASK (0x1ffff)
494
495/* RTC_ALARM (21) */
496#define MC13783_RTC_ALARM_MASK (0x1ffff)
497
498/* RTC_DAY (22) */
499#define MC13783_RTC_DAY_MASK (0x7fff)
500
501/* RTC_DAY_ALARM (23) */
502#define MC13783_RTC_DAY_ALARM_MASK (0x7fff)
503
504/* SWITCHERS0 (24) */
505#define MC13783_SW1A (0x3f << 0)
506 #define MC13783_SW1Aw(x) (((x) << 0) & MC13783_SW1A)
507 #define MC13783_SW1Ar(x) (((x) & MC13783_SW1A) >> 0)
508#define MC13783_SW1ADVS (0x3f << 6)
509 #define MC13783_SW1ADVSw(x) (((x) << 6) & MC13783_SW1ADVS)
510 #define MC13783_SW1ADVSr(x) (((x) & MC13783_SW1ADVS) >> 6)
511#define MC13783_SW1ASTBY (0x3f << 12)
512 #define MC13783_SW1ASTBYw(x) (((x) << 12) & MC13783_SW1ASTBY)
513 #define MC13783_SW1ASTBYr(x) (((x) & MC13783_SW1ASTBY) >> 12)
514
515/* SWITCHERS1 (25) */
516#define MC13783_SW1B (0x3f << 0)
517 #define MC13783_SW1Bw(x) (((x) << 0) & MC13783_SW1B)
518 #define MC13783_SW1Br(x) (((x) & MC13783_SW1B) >> 0)
519#define MC13783_SW1BDVS (0x3f << 6)
520 #define MC13783_SW1BDVSw(x) (((x) << 6) & MC13783_SW1BDVS)
521 #define MC13783_SW1BDVSr(x) (((x) & MC13783_SW1BDVS) >> 6)
522#define MC13783_SW1BSTBY (0x3f << 12)
523 #define MC13783_SW1BSTBYw(x) (((x) << 12) & MC13783_SW1BSTBY)
524 #define MC13783_SW1BSTBYr(x) (((x) & MC13783_SW1BSTBY) >> 12)
525
526/* SWITCHERS2 (26) */
527#define MC13783_SW2A (0x3f << 0)
528 #define MC13783_SW2Aw(x) (((x) << 0) & MC13783_SW1A)
529 #define MC13783_SW2Ar(x) (((x) & MC13783_SW1A) >> 0)
530#define MC13783_SW2ADVS (0x3f << 6)
531 #define MC13783_SW2ADVSw(x) (((x) << 6) & MC13783_SW2ADVS)
532 #define MC13783_SW2ADVSr(x) (((x) & MC13783_SW2ADVS) >> 6)
533#define MC13783_SW2ASTBY (0x3f << 12)
534 #define MC13783_SW2ASTBYw(x) (((x) << 12) & MC13783_SW2ASTBY)
535 #define MC13783_SW2ASTBYr(x) (((x) & MC13783_SW2ASTBY) >> 12)
536
537/* SWITCHERS3 (27) */
538#define MC13783_SW2B (0x3f << 0)
539 #define MC13783_SW2Bw(x) (((x) << 0) & MC13783_SW2B)
540 #define MC13783_SW2Br(x) (((x) & MC13783_SW2B) >> 0)
541#define MC13783_SW2BDVS (0x3f << 6)
542 #define MC13783_SW2BDVSw(x) (((x) << 6) & MC13783_SW2BDVS)
543 #define MC13783_SW2BDVSr(x) (((x) & MC13783_SW2BDVS) >> 6)
544#define MC13783_SW2BSTBY (0x3f << 12)
545 #define MC13783_SW2BSTBYw(x) (((x) << 12) & MC13783_SW2BSTBY)
546 #define MC13783_SW2BSTBYr(x) (((x) & MC13783_SW2BSTBY) >> 12)
547
548/* SWITCHERS4 (28) */
549#define MC13783_SW1AMODE (0x3 << 0)
550#define MC13783_SW1ASTBYMODE (0x3 << 2)
551#define MC13783_SW1ADVSSPEED (0x3 << 6)
552#define MC13783_SW1APANIC (0x1 << 8)
553#define MC13783_SW1ASFST (0x1 << 9)
554#define MC13783_SW1BMODE (0x3 << 10)
555#define MC13783_SW1BSTBYMODE (0x3 << 12)
556#define MC13783_SW1BDVSSPEED (0x3 << 14)
557#define MC13783_SW1BPANIC (0x1 << 16)
558#define MC13783_SW1BSFST (0x1 << 17)
559#define MC13783_PLLEN (0x1 << 18)
560#define MC13783_PLLX (0x7 << 19)
561
562/* SWITCHERS5 (29) */
563#define MC13783_SW2AMODE (0x3 << 0)
564#define MC13783_SW2ASTBYMODE (0x3 << 2)
565#define MC13783_SW2ADVSSPEED (0x3 << 6)
566#define MC13783_SW2APANIC (0x1 << 8)
567#define MC13783_SW2ASFST (0x1 << 9)
568#define MC13783_SW2BMODE (0x3 << 10)
569#define MC13783_SW2BSTBYMODE (0x3 << 12)
570#define MC13783_SW2BDVSSPEED (0x3 << 14)
571#define MC13783_SW2BPANIC (0x1 << 16)
572#define MC13783_SW2BSFST (0x1 << 17)
573#define MC13783_SW3 (0x3 << 18)
574 #define MC13783_SW3_PRI_VOL_BOTH_OP (0x0 << 18)
575 #define MC13783_SW3_SEC_VOL_BOTH_OP (0x2 << 18)
576 #define MC13783_SW3_PRI_ONLY (0x3 << 18)
577#define MC13783_SW3EN (0x1 << 20)
578#define MC13783_SW3STBY (0x1 << 21)
579#define MC13783_SW3MODE (0x1 << 22)
580
581/* REGULATOR_SETTING0 (30) */
582#define MC13783_VIOLO (0x3 << 2)
583#define MC13783_VDIG (0x3 << 4)
584#define MC13783_VGEN (0x7 << 6)
585#define MC13783_VRFDIG (0x3 << 9)
586#define MC13783_VRFREF (0x3 << 11)
587#define MC13783_VRFCP (0x1 << 13)
588#define MC13783_VSIM (0x1 << 14)
589#define MC13783_VESIM (0x1 << 15)
590#define MC13783_VCAM (0x7 << 16)
591
592/* REGULATOR_SETTING1 (31) */
593#define MC13783_VVIB (0x3 << 0)
594#define MC13783_VRF1 (0x3 << 2)
595#define MC13783_VRF2 (0x3 << 4)
596#define MC13783_VMMC1 (0x7 << 6)
597#define MC13783_VMMC2 (0x7 << 9)
598
599/* REGULATOR_MODE0 (32) */
600#define MC13783_VAUDIOEN (0x1 << 0)
601#define MC13783_VAUDIOSTBY (0x1 << 1)
602#define MC13783_VAUDIOMODE (0x1 << 2)
603#define MC13783_VIOHIEN (0x1 << 3)
604#define MC13783_VIOHISTBY (0x1 << 4)
605#define MC13783_VIOHIMODE (0x1 << 5)
606#define MC13783_VIOLOEN (0x1 << 6)
607#define MC13783_VIOLOSTBY (0x1 << 7)
608#define MC13783_VIOLOMODE (0x1 << 8)
609#define MC13783_VDIGEN (0x1 << 9)
610#define MC13783_VDIGSTBY (0x1 << 10)
611#define MC13783_VDIGMODE (0x1 << 11)
612#define MC13783_VGENEN (0x1 << 12)
613#define MC13783_VGENSTBY (0x1 << 13)
614#define MC13783_VGENMODE (0x1 << 14)
615#define MC13783_VRFDIGEN (0x1 << 15)
616#define MC13783_VRFDIGSTBY (0x1 << 16)
617#define MC13783_VRFDIGMODE (0x1 << 17)
618#define MC13783_VRFREFEN (0x1 << 18)
619#define MC13783_VRFREFSTBY (0x1 << 19)
620#define MC13783_VRFREFMODE (0x1 << 20)
621#define MC13783_VRFCPEN (0x1 << 21)
622#define MC13783_VRFCPSTBY (0x1 << 22)
623#define MC13783_VRFCPMODE (0x1 << 23)
624
625/* REGULATOR_MODE1 (33) */
626#define MC13783_VSIMEN (0x1 << 0)
627#define MC13783_VSIMSTBY (0x1 << 1)
628#define MC13783_VSIMMODE (0x1 << 2)
629#define MC13783_VESIMEN (0x1 << 3)
630#define MC13783_VESIMSTBY (0x1 << 4)
631#define MC13783_VESIMMODE (0x1 << 5)
632#define MC13783_VCAMEN (0x1 << 6)
633#define MC13783_VCAMSTBY (0x1 << 7)
634#define MC13783_VCAMMODE (0x1 << 8)
635#define MC13783_VRFBGEN (0x1 << 9)
636#define MC13783_VRFBGSTBY (0x1 << 10)
637#define MC13783_VVIBEN (0x1 << 11)
638#define MC13783_VRF1EN (0x1 << 12)
639#define MC13783_VRF1STBY (0x1 << 13)
640#define MC13783_VRF1MODE (0x1 << 14)
641#define MC13783_VRF2EN (0x1 << 15)
642#define MC13783_VRF2STBY (0x1 << 16)
643#define MC13783_VRF2MODE (0x1 << 17)
644#define MC13783_VMMC1EN (0x1 << 18)
645#define MC13783_VMMC1STBY (0x1 << 19)
646#define MC13783_VMMC1MODE (0x1 << 20)
647#define MC13783_VMMC2EN (0x1 << 21)
648#define MC13783_VMMC2STBY (0x1 << 22)
649#define MC13783_VMMC2MODE (0x1 << 23)
650
651/* POWER_MISCELLANEOUS (34) */
652#define MC13783_GPO1EN (0x1 << 6)
653#define MC13783_GPO1STBY (0x1 << 7)
654#define MC13783_GPO2EN (0x1 << 8)
655#define MC13783_GPO2STBY (0x1 << 9)
656#define MC13783_GPO3EN (0x1 << 10)
657#define MC13783_GPO3STBY (0x1 << 11)
658#define MC13783_GPO4EN (0x1 << 12)
659#define MC13783_GPO4STBY (0x1 << 13)
660#define MC13783_VIBPINCTRL (0x1 << 14)
661#define MC13783_PWGT1SPIEN (0x1 << 15)
662#define MC13783_PWGT2SPIEN (0x1 << 16)
663
664/* AUDIO_RX0 (36) */
665#define MC13783_VAUDIOON (0x1 << 0)
666#define MC13783_BIASEN (0x1 << 1)
667#define MC13783_BIASSPEED (0x1 << 2)
668#define MC13783_ASPEN (0x1 << 3)
669#define MC13783_ASPSEL (0x1 << 4)
670#define MC13783_ALSPEN (0x1 << 5)
671#define MC13783_ALSPREF (0x1 << 6)
672#define MC13783_ALSPSEL (0x1 << 7)
673#define MC13783_LSPLEN (0x1 << 8)
674#define MC13783_AHSREN (0x1 << 9)
675#define MC13783_AHSLEN (0x1 << 10)
676#define MC13783_AHSSEL (0x1 << 11)
677#define MC13783_HSPGDIS (0x1 << 12)
678#define MC13783_HSDETEN (0x1 << 13)
679#define MC13783_HSDETAUTOB (0x1 << 14)
680#define MC13783_ARXOUTREN (0x1 << 15)
681#define MC13783_ARXOUTLEN (0x1 << 16)
682#define MC13783_ARXOUTSEL (0x1 << 17)
683#define MC13783_CDCOUTEN (0x1 << 18)
684#define MC13783_HSLDETEN (0x1 << 19)
685#define MC13783_ADDCDC (0x1 << 21)
686#define MC13783_ADDSTDC (0x1 << 22)
687#define MC13783_ADDRXIN (0x1 << 23)
688
689/* AUDIO_RX1 (37) */
690#define MC13783_PGARXEN (0x1 << 0)
691#define MC13783_PGARX (0xf << 1)
692#define MC13783_PGASTEN (0x1 << 5)
693#define MC13783_PGAST (0xf << 6)
694#define MC13783_ARXINEN (0x1 << 10)
695#define MC13783_ARXIN (0x1 << 11)
696#define MC13783_PGARXIN (0xf << 12)
697#define MC13783_MONO (0x3 << 16)
698#define MC13783_BAL (0x7 << 18)
699#define MC13783_BALLR (0x1 << 21)
700
701/* AUDIO_TX (38) */
702#define MC13783_MC1BEN (0x1 << 0)
703#define MC13783_MC2BEN (0x1 << 1)
704#define MC13783_MC2BDETDBNC (0x1 << 2)
705#define MC13783_MC2BDETEN (0x1 << 3)
706#define MC13783_AMC1REN (0x1 << 5)
707#define MC13783_AMC1RITOV (0x1 << 6)
708#define MC13783_AMC1LEN (0x1 << 7)
709#define MC13783_AMC1LITOV (0x1 << 8)
710#define MC13783_AMC2EN (0x1 << 9)
711#define MC13783_AMC2ITOV (0x1 << 10)
712#define MC13783_ATXINEN (0x1 << 11)
713#define MC13783_ATXOUTEN (0x1 << 12)
714#define MC13783_RXINREC (0x1 << 13)
715#define MC13783_PGATXR (0x1f << 14)
716#define MC13783_PGATXL (0x1f << 19)
717
718/* SSI_NETWORK (39) */
719#define MC13783_CDCTXRXSLOT (0x3 << 2)
720#define MC13783_CDCTXSECSLOT (0x3 << 4)
721#define MC13783_CDCRXSECSLOT (0x3 << 6)
722#define MC13783_CDCRXSECGAIN (0x3 << 8)
723#define MC13783_CDCSUMGAIN (0x1 << 10)
724#define MC13783_CDCFSDLY (0x1 << 11)
725#define MC13783_STDCSLOTS (0x3 << 12)
726#define MC13783_STDCRXSLOT (0x3 << 14)
727#define MC13783_STDCRXSECSLOT (0x3 << 16)
728#define MC13783_STDCRXSECGAIN (0x3 << 18)
729#define MC13783_STDSUMGAIN (0x1 << 20)
730
731/* AUDIO_CODEC (40) */
732#define MC13783_CDCSSISEL (0x1 << 0)
733#define MC13783_CDCCLKSEL (0x1 << 1)
734#define MC13783_CDCSM (0x1 << 2)
735#define MC13783_CDCBCLINV (0x1 << 3)
736#define MC13783_CDCFSINV (0x1 << 4)
737#define MC13783_CDCFS (0x3 << 5)
738#define MC13783_CDCCLK (0x7 << 7)
739#define MC13783_CDCFS8K16K (0x1 << 10)
740#define MC13783_CDCEN (0x1 << 11)
741#define MC13783_CDCCLKEN (0x1 << 12)
742#define MC13783_CDCTS (0x1 << 13)
743#define MC13783_CDCDITH (0x1 << 14)
744#define MC13783_CDCRESET (0x1 << 15)
745#define MC13783_CDCBYP (0x1 << 16)
746#define MC13783_CDCALM (0x1 << 17)
747#define MC13783_CDCDLM (0x1 << 18)
748#define MC13783_AUDIHPF (0x1 << 19)
749#define MC13783_AUDOHPF (0x1 << 20)
750
751/* AUDIO_STEREO_DAC (41) */
752#define MC13783_STDCSSISEL (0x1 << 0)
753#define MC13783_STDCCLKSEL (0x1 << 1)
754#define MC13783_STDCSM (0x1 << 2)
755#define MC13783_STDCBCLINV (0x1 << 3)
756#define MC13783_STDCFSINV (0x1 << 4)
757#define MC13783_STDCFS (0x3 << 5)
758#define MC13783_STDCCLK (0x7 << 7)
759#define MC13783_STDCFSDLYB (0x1 << 10)
760#define MC13783_STDCEN (0x1 << 11)
761#define MC13783_STDCCLKEN (0x1 << 12)
762#define MC13783_STDCRESET (0x1 << 15)
763#define MC13783_SPDIF (0x1 << 16)
764#define MC13783_SR (0xf << 17)
765
766/* ADC0 (43) */
767#define MC13783_LICELLCON (0x1 << 0)
768#define MC13783_CHRGICON (0x1 << 1)
769#define MC13783_BATICON (0x1 << 2)
770#define MC13783_RTHEN (0x1 << 3)
771#define MC13783_DTHEN (0x1 << 4)
772#define MC13783_UIDEN (0x1 << 5)
773#define MC13783_ADOUTEN (0x1 << 6)
774#define MC13783_ADOUTPER (0x1 << 7)
775#define MC13783_ADREFEN (0x1 << 10)
776#define MC13783_ADREFMODE (0x1 << 11)
777#define MC13783_TSMOD (0x7 << 12)
778 #define MC13783_TSMOD_INACTIVE (0x0 << 12)
779 #define MC13783_TSMOD_INTERRUPT (0x1 << 12)
780 #define MC13783_TSMOD_RESISTIVE (0x2 << 12)
781 #define MC13783_TSMOD_POSITION (0x3 << 12)
782 /* 0x4 - 0x7 = Inactive (same as 0x0) */
783#define MC13783_CHRGRAWDIV (0x1 << 15)
784#define MC13783_ADINC1 (0x1 << 16)
785#define MC13783_ADINC2 (0x1 << 17)
786#define MC13783_WCOMP (0x1 << 18)
787#define MC13783_ADCBIS0_ACCESS (0x1 << 23)
788
789/* ADC1 (44) */
790#define MC13783_ADEN (0x1 << 0)
791#define MC13783_RAND (0x1 << 1)
792#define MC13783_ADSEL (0x1 << 3)
793#define MC13783_TRIGMASK (0x1 << 4)
794#define MC13783_ADA1 (0x7 << 5)
795 #define MC13783_ADA1w(x) (((x) << 5) & MC13783_ADA1)
796 #define MC13783_ADA1r(x) (((x) & MC13783_ADA1) >> 5)
797#define MC13783_ADA2 (0x7 << 8)
798 #define MC13783_ADA2w(x) (((x) << 8) & MC13783_ADA2)
799 #define MC13783_ADA2r(x) (((x) & MC13783_ADA2) >> 8)
800#define MC13783_ATO (0xff << 11)
801 #define MC13783_ATOw(x) (((x) << 11) & MC13783_ATO)
802 #define MC13783_ATOr(x) (((x) & MC13783_ATO) >> 11)
803#define MC13783_ATOX (0x1 << 19)
804#define MC13783_ASC (0x1 << 20)
805#define MC13783_ADTRIGIGN (0x1 << 21)
806#define MC13783_ADONESHOT (0x1 << 22)
807#define MC13783_ADCBIS1_ACCESS (0x1 << 23)
808
809/* ADC2 (45) */
810#define MC13783_ADD1 (0x3ff << 2)
811 #define MC13783_ADD1r(x) (((x) >> 2) & MC13783_ADD1)
812#define MC13783_ADD2 (0x3ff << 14)
813 #define MC13783_ADD2r(x) (((x) >> 14) & MC13783_ADD2)
814
815/* ADC3 (46) */
816#define MC13783_WHIGH (0x3f << 0)
817 #define MC13783_WHIGHw(x) (((x) << 0) & MC13783_WHIGH)
818 #define MC13783_WHIGHr(x) (((x) & MC13783_WHIGH) >> 0)
819#define MC13783_ICID (0x7 << 6)
820 #define MC13783_ICIDr(x) (((x) & MC13783_ICID) >> 6)
821#define MC13783_WLOW (0x3f << 9)
822 #define MC13783_WLOWw(x) (((x) << 9) & MC13783_WLOW)
823 #define MC13783_WLOWr(x) (((x) & MC13783_WLOW) >> 9)
824#define MC13783_ADCBIS2_ACCESS (0x1 << 23)
825
826/* ADC4 (47) */
827#define MC13783_ADCBIS1 (0x3ff << 2)
828 #define MC13783_ADCBIS1r(x) (((x) & MC13783_ADCBIS1) >> 2)
829#define MC13783_ADCBIS2 (0x3ff << 14)
830 #define MC13783_ADCBIS2r(x) (((x) & MC13783_ADCBIS2) >> 14)
831
832/* CHARGER (48) */
833#define MC13783_VCHRG (0x7 << 0)
834 #define MC13783_VCHRG_4_050V (0x0 << 0)
835 #define MC13783_VCHRG_4_375V (0x1 << 0)
836 #define MC13783_VCHRG_4_150V (0x2 << 0)
837 #define MC13783_VCHRG_4_200V (0x3 << 0)
838 #define MC13783_VCHRG_4_250V (0x4 << 0)
839 #define MC13783_VCHRG_4_300V (0x5 << 0)
840 #define MC13783_VCHRG_3_800V (0x6 << 0)
841 #define MC13783_VCHRG_4_500V (0x7 << 0)
842#define MC13783_ICHRG (0xf << 3) /* Min Nom Max */
843 #define MC13783_ICHRG_0MA (0x0 << 3) /* 0 0 0 */
844 #define MC13783_ICHRG_70MA (0x1 << 3) /* 55 70 85 */
845 #define MC13783_ICHRG_177MA (0x2 << 3) /* 161 177 195 */
846 #define MC13783_ICHRG_266MA (0x3 << 3) /* 242 266 293 */
847 #define MC13783_ICHRG_355MA (0x4 << 3) /* 322 355 390 */
848 #define MC13783_ICHRG_443MA (0x5 << 3) /* 403 443 488 */
849 #define MC13783_ICHRG_532MA (0x6 << 3) /* 484 532 585 */
850 #define MC13783_ICHRG_621MA (0x7 << 3) /* 564 621 683 */
851 #define MC13783_ICHRG_709MA (0x8 << 3) /* 645 709 780 */
852 #define MC13783_ICHRG_798MA (0x9 << 3) /* 725 798 878 */
853 #define MC13783_ICHRG_886MA (0xa << 3) /* 806 886 975 */
854 #define MC13783_ICHRG_975MA (0xb << 3) /* 886 975 1073 */
855 #define MC13783_ICHRG_1064MA (0xc << 3) /* 967 1064 1170 */
856 #define MC13783_ICHRG_1152MA (0xd << 3) /* 1048 1152 1268 */
857 #define MC13783_ICHRG_1596MA (0xe << 3) /* 1450 1596 1755 */
858 #define MC13783_ICHRG_FULLY_ON (0xf << 3) /* Disallow HW FET turn on */
859#define MC13783_ICHRGTR (0x7 << 7) /* Min Nom Max */
860 #define MC13783_ICHRGTR_0MA (0x0 << 7) /* 0 0 0 */
861 #define MC13783_ICHRGTR_9MA (0x1 << 7) /* 6 9 12 */
862 #define MC13783_ICHRGTR_20MA (0x2 << 7) /* 14 20 26 */
863 #define MC13783_ICHRGTR_36MA (0x3 << 7) /* 25 36 47 */
864 #define MC13783_ICHRGTR_42MA (0x4 << 7) /* 29 42 55 */
865 #define MC13783_ICHRGTR_50MA (0x5 << 7) /* 35 50 65 */
866 #define MC13783_ICHRGTR_59MA (0x6 << 7) /* 41 59 77 */
867 #define MC13783_ICHRGTR_68MA (0x7 << 7) /* 50 68 86 */
868#define MC13783_FETOVRD (0x1 << 10)
869#define MC13783_FETCTRL (0x1 << 11)
870#define MC13783_RVRSMODE (0x1 << 13)
871#define MC13783_OVCTRL (0x3 << 15)
872 #define MC13783_OVCTRL_5_83V (0x0 << 15) /* Not for separate! */
873 #define MC13783_OVCTRL_6_90V (0x1 << 15)
874 #define MC13783_OVCTRL_9_80V (0x2 << 15)
875 #define MC13783_OVCTRL_19_6V (0x3 << 15)
876#define MC13783_UCHEN (0x1 << 17)
877#define MC13783_CHRGLEDEN (0x1 << 18)
878#define MC13783_CHRGRAWPDEN (0x1 << 19)
879
880/* USB0 (49) */
881#define MC13783_FSENB (0x1 << 0)
882#define MC13783_USBSUSPEND (0x1 << 1)
883#define MC13783_USBPU (0x1 << 2)
884#define MC13783_UDPPD (0x1 << 3)
885#define MC13783_UDMPD (0x1 << 4)
886#define MC13783_DP150KPU (0x1 << 5)
887#define MC13783_VBUS70KPDENB (0x1 << 6)
888#define MC13783_VBUSPULSETMR (0x7 << 7)
889 #define MC13783_VBUSPULSETMR_NA (0x0 << 7)
890 #define MC13783_VBUSPULSETMR_10MS (0x1 << 7)
891 #define MC13783_VBUSPULSETMR_20MS (0x2 << 7)
892 #define MC13783_VBUSPULSETMR_30MS (0x3 << 7)
893 #define MC13783_VBUSPULSETMR_40MS (0x4 << 7)
894 #define MC13783_VBUSPULSETMR_50MS (0x5 << 7)
895 #define MC13783_VBUSPULSETMR_60MS (0x6 << 7)
896 #define MC13783_VBUSPULSETMR_INF (0x7 << 7)
897#define MC13783_DLPSRP (0x1 << 10)
898#define MC13783_SE0CONN (0x1 << 11)
899#define MC13783_USBXCVREN (0x1 << 12)
900#define MC13783_CONMODE (0x7 << 14)
901 #define MC13783_CONMODE_USB (0x0 << 14)
902 #define MC13783_CONMODE_RS232 (0x1 << 14) /* and 0x2 */
903 #define MC13783_CONMODE_CEA_936_A (0x4 << 14) /* and 0x5...0x7 */
904#define MC13783_DATSE0 (0x1 << 17)
905#define MC13783_BIDIR (0x1 << 18)
906#define MC13783_USBCNTRL (0x1 << 19)
907#define MC13783_IDPD (0x1 << 20)
908#define MC13783_IDPULSE (0x1 << 21)
909#define MC13783_IDPUCNTRL (0x1 << 22)
910#define MC13783_DMPULSE (0x1 << 23)
911
912/* CHARGER_USB1 (50) */
913#define MC13783_USBIN (0x3 << 0)
914 #define MC13783_USBIN_BOOST_VINBUS (0x0 << 0)
915 #define MC13783_USBIN_VBUS (0x1 << 0) /* and 0x3 */
916 #define MC13783_USBIN_BP (0x2 << 0) /* VINVIB */
917#define MC13783_VUSB (0x1 << 2) /* 0=3.2V, 1=3.3V */
918#define MC13783_VUSBEN (0x1 << 3)
919#define MC13783_VBUSEN (0x1 << 5)
920#define MC13783_RSPOL (0x1 << 6)
921#define MC13783_RSTRI (0x1 << 7)
922#define MC13783_ID100KPU (0x1 << 8)
923
924/* LED_CONTROL0 (51) */
925#define MC13783_LEDEN (0x1 << 0)
926#define MC13783_LEDMDRAMPUP (0x1 << 1)
927#define MC13783_LEDADRAMPUP (0x1 << 2)
928#define MC13783_LEDKDRAMPUP (0x1 << 3)
929#define MC13783_LEDMDRAMPDOWN (0x1 << 4)
930#define MC13783_LEDADRAMPDOWN (0x1 << 5)
931#define MC13783_LEDKDRAMPDOWN (0x1 << 6)
932#define MC13783_TRIODEMD (0x1 << 7)
933#define MC13783_TRIODEAD (0x1 << 8)
934#define MC13783_TRIODEKD (0x1 << 9)
935#define MC13783_BOOSTEN (0x1 << 10)
936#define MC13783_ABMODE (0x7 << 11)
269 #define MC13783_ABMODE_ADAPTIVE_BOOST_DISABLED (0x0 << 11) 937 #define MC13783_ABMODE_ADAPTIVE_BOOST_DISABLED (0x0 << 11)
270 #define MC13783_ABMODE_MONCH_LEDMD1 (0x1 << 11) 938 #define MC13783_ABMODE_MONCH_LEDMD1 (0x1 << 11)
271 #define MC13783_ABMODE_MONCH_LEDMD12 (0x2 << 11) 939 #define MC13783_ABMODE_MONCH_LEDMD12 (0x2 << 11)
@@ -274,142 +942,135 @@ enum mc13783_regs_enum
274 #define MC13783_ABMODE_MONCH_LEDMD1234_LEADAD1 (0x5 << 11) 942 #define MC13783_ABMODE_MONCH_LEDMD1234_LEADAD1 (0x5 << 11)
275 #define MC13783_ABMODE_MONCH_LEDMD1234_LEADAD12 (0x6 << 11) 943 #define MC13783_ABMODE_MONCH_LEDMD1234_LEADAD12 (0x6 << 11)
276 #define MC13783_ABMODE_MONCH_LEDMD1_LEDAD_ACT (0x7 << 11) 944 #define MC13783_ABMODE_MONCH_LEDMD1_LEDAD_ACT (0x7 << 11)
277#define MC13783_ABREF (0x3 << 14) 945#define MC13783_ABREF (0x3 << 14)
278 #define MC13783_ABREF_200MV (0x0 << 14) 946 #define MC13783_ABREF_200MV (0x0 << 14)
279 #define MC13783_ABREF_400MV (0x1 << 14) 947 #define MC13783_ABREF_400MV (0x1 << 14)
280 #define MC13783_ABREF_600MV (0x2 << 14) 948 #define MC13783_ABREF_600MV (0x2 << 14)
281 #define MC13783_ABREF_800MV (0x3 << 14) 949 #define MC13783_ABREF_800MV (0x3 << 14)
282#define MC13783_FLPATTRN (0xf << 17) 950#define MC13783_FLPATTRN (0xf << 17)
283 #define MC13783_FLPATTRNw(x) (((x) << 17) & MC13783_FLPATTRN) 951 #define MC13783_FLPATTRNw(x) (((x) << 17) & MC13783_FLPATTRN)
284 #define MC13783_FLPATTRNr(x) (((x) & MC13783_FLPATTRN) >> 17) 952 #define MC13783_FLPATTRNr(x) (((x) & MC13783_FLPATTRN) >> 17)
285#define MC13783_FLBANK1 (0x1 << 21) 953#define MC13783_FLBANK1 (0x1 << 21)
286#define MC13783_FLBANK2 (0x1 << 22) 954#define MC13783_FLBANK2 (0x1 << 22)
287#define MC13783_FLBANK3 (0x1 << 23) 955#define MC13783_FLBANK3 (0x1 << 23)
288 956
289/* LED_CONTROL1 */ 957/* LED_CONTROL1 (52) */
290#define MC13783_LEDR1RAMPUP (0x1 << 0) 958#define MC13783_LEDR1RAMPUP (0x1 << 0)
291#define MC13783_LEDG1RAMPUP (0x1 << 1) 959#define MC13783_LEDG1RAMPUP (0x1 << 1)
292#define MC13783_LEDB1RAMPUP (0x1 << 2) 960#define MC13783_LEDB1RAMPUP (0x1 << 2)
293#define MC13783_LEDR1RAMPDOWN (0x1 << 3) 961#define MC13783_LEDR1RAMPDOWN (0x1 << 3)
294#define MC13783_LEDG1RAMPDOWN (0x1 << 4) 962#define MC13783_LEDG1RAMPDOWN (0x1 << 4)
295#define MC13783_LEDB1RAMPDOWN (0x1 << 5) 963#define MC13783_LEDB1RAMPDOWN (0x1 << 5)
296#define MC13783_LEDR2RAMPUP (0x1 << 6) 964#define MC13783_LEDR2RAMPUP (0x1 << 6)
297#define MC13783_LEDG2RAMPUP (0x1 << 7) 965#define MC13783_LEDG2RAMPUP (0x1 << 7)
298#define MC13783_LEDB2RAMPUP (0x1 << 8) 966#define MC13783_LEDB2RAMPUP (0x1 << 8)
299#define MC13783_LEDR2RAMPDOWN (0x1 << 9) 967#define MC13783_LEDR2RAMPDOWN (0x1 << 9)
300#define MC13783_LEDG2RAMPDOWN (0x1 << 10) 968#define MC13783_LEDG2RAMPDOWN (0x1 << 10)
301#define MC13783_LEDB2RAMPDOWN (0x1 << 11) 969#define MC13783_LEDB2RAMPDOWN (0x1 << 11)
302#define MC13783_LEDR3RAMPUP (0x1 << 12) 970#define MC13783_LEDR3RAMPUP (0x1 << 12)
303#define MC13783_LEDG3RAMPUP (0x1 << 13) 971#define MC13783_LEDG3RAMPUP (0x1 << 13)
304#define MC13783_LEDB3RAMPUP (0x1 << 14) 972#define MC13783_LEDB3RAMPUP (0x1 << 14)
305#define MC13783_LEDR3RAMPDOWN (0x1 << 15) 973#define MC13783_LEDR3RAMPDOWN (0x1 << 15)
306#define MC13783_LEDG3RAMPDOWN (0x1 << 16) 974#define MC13783_LEDG3RAMPDOWN (0x1 << 16)
307#define MC13783_LEDB3RAMPDOWN (0x1 << 17) 975#define MC13783_LEDB3RAMPDOWN (0x1 << 17)
308#define MC13783_TC1HALF (0x1 << 18) 976#define MC13783_TC1HALF (0x1 << 18)
309#define MC13783_SLEWLIMTC (0x1 << 23) 977#define MC13783_SLEWLIMTC (0x1 << 23)
310 978
311/* LED_CONTROL2 */ 979/* LED_CONTROL2 (53) */
312#define MC13783_LEDMD (0x7 << 0) 980#define MC13783_LEDMD (0x7 << 0)
313 #define MC13783_LEDMDw(x) (((x) << 0) & MC13783_LEDMD) 981 #define MC13783_LEDMDw(x) (((x) << 0) & MC13783_LEDMD)
314 #define MC13783_LEDMDr(x) (((x) & MC13783_LEDMD) >> 0) 982 #define MC13783_LEDMDr(x) (((x) & MC13783_LEDMD) >> 0)
315#define MC13783_LEDAD (0x7 << 3) 983#define MC13783_LEDAD (0x7 << 3)
316 #define MC13783_LEDADw(x) (((x) << 3) & MC13783_LEDAD) 984 #define MC13783_LEDADw(x) (((x) << 3) & MC13783_LEDAD)
317 #define MC13783_LEDADr(x) (((x) & MC13783_LEDAD) >> 3) 985 #define MC13783_LEDADr(x) (((x) & MC13783_LEDAD) >> 3)
318#define MC13783_LEDKP (0x7 << 6) 986#define MC13783_LEDKP (0x7 << 6)
319 #define MC13783_LEDKPw(x) (((x) << 6) & MC13783_LEDKP) 987 #define MC13783_LEDKPw(x) (((x) << 6) & MC13783_LEDKP)
320 #define MC13783_LEDKPr(x) (((x) & MC13783_LEDKP) >> 6) 988 #define MC13783_LEDKPr(x) (((x) & MC13783_LEDKP) >> 6)
321#define MC13783_LEDMDDC (0xf << 9) 989#define MC13783_LEDMDDC (0xf << 9)
322 #define MC13783_LEDMDDCw(x) (((x) << 9) & MC13783_LEDMDDC) 990 #define MC13783_LEDMDDCw(x) (((x) << 9) & MC13783_LEDMDDC)
323 #define MC13783_LEDMDDCr(x) (((x) & MC13783_LEDMDDC) >> 9) 991 #define MC13783_LEDMDDCr(x) (((x) & MC13783_LEDMDDC) >> 9)
324#define MC13783_LEDADDC (0xf << 13) 992#define MC13783_LEDADDC (0xf << 13)
325 #define MC13783_LEDADDCw(x) (((x) << 13) & MC13783_LEDADDC) 993 #define MC13783_LEDADDCw(x) (((x) << 13) & MC13783_LEDADDC)
326 #define MC13783_LEDADDCr(x) (((x) & MC13783_LEDADDC) >> 13) 994 #define MC13783_LEDADDCr(x) (((x) & MC13783_LEDADDC) >> 13)
327#define MC13783_LEDKPDC (0xf << 17) 995#define MC13783_LEDKPDC (0xf << 17)
328 #define MC13783_LEDKPDCw(x) (((x) << 17) & MC13783_LEDKPDC) 996 #define MC13783_LEDKPDCw(x) (((x) << 17) & MC13783_LEDKPDC)
329 #define MC13783_LEDKPDCr(x) (((x) & MC13783_LEDKPDC) >> 17) 997 #define MC13783_LEDKPDCr(x) (((x) & MC13783_LEDKPDC) >> 17)
330#define MC13783_BLPERIOD (0x1 << 21) 998#define MC13783_BLPERIOD (0x1 << 21)
331 #define MC13783_BLPERIODw(x) (((x) << 21) & MC13783_BLPERIOD) 999 #define MC13783_BLPERIODw(x) (((x) << 21) & MC13783_BLPERIOD)
332 #define MC13783_BLPERIODr(x) (((x) & MC13783_BLPERIOD) >> 21) 1000 #define MC13783_BLPERIODr(x) (((x) & MC13783_BLPERIOD) >> 21)
333#define MC13783_SLEWLIMBL (0x1 << 23) 1001#define MC13783_SLEWLIMBL (0x1 << 23)
334 1002
335/* LED_CONTROL3 */ 1003/* LED_CONTROL3 (54) */
336#define MC13783_LEDR1 (0x3 << 0) 1004#define MC13783_LEDR1 (0x3 << 0)
337 #define MC13783_LEDR1w(x) (((x) << 0) & MC13783_LEDR1) 1005 #define MC13783_LEDR1w(x) (((x) << 0) & MC13783_LEDR1)
338 #define MC13783_LEDR1r(x) (((x) & MC13783_LEDR1) >> 0) 1006 #define MC13783_LEDR1r(x) (((x) & MC13783_LEDR1) >> 0)
339#define MC13783_LEDG1 (0x3 << 2) 1007#define MC13783_LEDG1 (0x3 << 2)
340 #define MC13783_LEDG1w(x) (((x) << 2) & MC13783_LEDG1) 1008 #define MC13783_LEDG1w(x) (((x) << 2) & MC13783_LEDG1)
341 #define MC13783_LEDG1r(x) (((x) & MC13783_LEDG1) >> 2) 1009 #define MC13783_LEDG1r(x) (((x) & MC13783_LEDG1) >> 2)
342#define MC13783_LEDB1 (0x3 << 4) 1010#define MC13783_LEDB1 (0x3 << 4)
343 #define MC13783_LEDB1w(x) (((x) << 4) & MC13783_LEDB1) 1011 #define MC13783_LEDB1w(x) (((x) << 4) & MC13783_LEDB1)
344 #define MC13783_LEDB1r(x) (((x) & MC13783_LEDB1) >> 4) 1012 #define MC13783_LEDB1r(x) (((x) & MC13783_LEDB1) >> 4)
345#define MC13783_LEDR1DC (0x1f << 6) 1013#define MC13783_LEDR1DC (0x1f << 6)
346 #define MC13783_LEDR1DCw(x) (((x) << 6) & MC13783_LEDR1DC) 1014 #define MC13783_LEDR1DCw(x) (((x) << 6) & MC13783_LEDR1DC)
347 #define MC13783_LEDR1DCr(x) (((x) & MC13783_LEDR1DC) >> 6) 1015 #define MC13783_LEDR1DCr(x) (((x) & MC13783_LEDR1DC) >> 6)
348#define MC13783_LEDG1DC (0x1f << 11) 1016#define MC13783_LEDG1DC (0x1f << 11)
349 #define MC13783_LEDG1DCw(x) (((x) << 11) & MC13783_LEDG1DC) 1017 #define MC13783_LEDG1DCw(x) (((x) << 11) & MC13783_LEDG1DC)
350 #define MC13783_LEDG1DCr(x) (((x) & MC13783_LEDG1DC) >> 11) 1018 #define MC13783_LEDG1DCr(x) (((x) & MC13783_LEDG1DC) >> 11)
351#define MC13783_LEDB1DC (0x1f << 16) 1019#define MC13783_LEDB1DC (0x1f << 16)
352 #define MC13783_LEDB1DCw(x) (((x) << 16) & MC13783_LEDB1DC) 1020 #define MC13783_LEDB1DCw(x) (((x) << 16) & MC13783_LEDB1DC)
353 #define MC13783_LEDB1DCr(x) (((x) & MC13783_LEDB1DC) >> 16) 1021 #define MC13783_LEDB1DCr(x) (((x) & MC13783_LEDB1DC) >> 16)
354#define MC13783_TC1PERIOD (0x3 << 21) 1022#define MC13783_TC1PERIOD (0x3 << 21)
355 #define MC13783_TC1PERIODw(x) (((x) << 21) & MC13783_TC1PERIOD) 1023 #define MC13783_TC1PERIODw(x) (((x) << 21) & MC13783_TC1PERIOD)
356 #define MC13783_TC1PERIODr(x) (((x) & MC13783_TC1PERIOD) >> 21) 1024 #define MC13783_TC1PERIODr(x) (((x) & MC13783_TC1PERIOD) >> 21)
357#define MC13783_TC1TRIODE (0x1 << 23) 1025#define MC13783_TC1TRIODE (0x1 << 23)
358 1026
359/* LED_CONTROL4 */ 1027/* LED_CONTROL4 (55) */
360#define MC13783_LEDR2 (0x3 << 0) 1028#define MC13783_LEDR2 (0x3 << 0)
361 #define MC13783_LEDR2w(x) (((x) << 0) & MC13783_LEDR2) 1029 #define MC13783_LEDR2w(x) (((x) << 0) & MC13783_LEDR2)
362 #define MC13783_LEDR2r(x) (((x) & MC13783_LEDR2) >> 0) 1030 #define MC13783_LEDR2r(x) (((x) & MC13783_LEDR2) >> 0)
363#define MC13783_LEDG2 (0x3 << 2) 1031#define MC13783_LEDG2 (0x3 << 2)
364 #define MC13783_LEDG2w(x) (((x) << 2) & MC13783_LEDG2) 1032 #define MC13783_LEDG2w(x) (((x) << 2) & MC13783_LEDG2)
365 #define MC13783_LEDG2r(x) (((x) & MC13783_LEDG2) >> 2) 1033 #define MC13783_LEDG2r(x) (((x) & MC13783_LEDG2) >> 2)
366#define MC13783_LEDB2 (0x3 << 4) 1034#define MC13783_LEDB2 (0x3 << 4)
367 #define MC13783_LEDB2w(x) (((x) << 4) & MC13783_LEDB2) 1035 #define MC13783_LEDB2w(x) (((x) << 4) & MC13783_LEDB2)
368 #define MC13783_LEDB2r(x) (((x) & MC13783_LEDB2) >> 4) 1036 #define MC13783_LEDB2r(x) (((x) & MC13783_LEDB2) >> 4)
369#define MC13783_LEDR2DC (0x1f << 6) 1037#define MC13783_LEDR2DC (0x1f << 6)
370 #define MC13783_LEDR2DCw(x) (((x) << 6) & MC13783_LEDR2DC) 1038 #define MC13783_LEDR2DCw(x) (((x) << 6) & MC13783_LEDR2DC)
371 #define MC13783_LEDR2DCr(x) (((x) & MC13783_LEDR2DC) >> 6) 1039 #define MC13783_LEDR2DCr(x) (((x) & MC13783_LEDR2DC) >> 6)
372#define MC13783_LEDG2DC (0x1f << 11) 1040#define MC13783_LEDG2DC (0x1f << 11)
373 #define MC13783_LEDG2DCw(x) (((x) << 11) & MC13783_LEDG2DC) 1041 #define MC13783_LEDG2DCw(x) (((x) << 11) & MC13783_LEDG2DC)
374 #define MC13783_LEDG2DCr(x) (((x) & MC13783_LEDG2DC) >> 11) 1042 #define MC13783_LEDG2DCr(x) (((x) & MC13783_LEDG2DC) >> 11)
375#define MC13783_LEDB2DC (0x1f << 16) 1043#define MC13783_LEDB2DC (0x1f << 16)
376 #define MC13783_LEDB2DCw(x) (((x) << 16) & MC13783_LEDB2DC) 1044 #define MC13783_LEDB2DCw(x) (((x) << 16) & MC13783_LEDB2DC)
377 #define MC13783_LEDB2DCr(x) (((x) & MC13783_LEDB2DC) >> 16) 1045 #define MC13783_LEDB2DCr(x) (((x) & MC13783_LEDB2DC) >> 16)
378#define MC13783_TC2PERIOD (0x3 << 21) 1046#define MC13783_TC2PERIOD (0x3 << 21)
379 #define MC13783_TC2PERIODw(x) (((x) << 21) & MC13783_TC2PERIOD) 1047 #define MC13783_TC2PERIODw(x) (((x) << 21) & MC13783_TC2PERIOD)
380 #define MC13783_TC2PERIODr(x) (((x) & MC13783_TC2PERIOD) >> 21) 1048 #define MC13783_TC2PERIODr(x) (((x) & MC13783_TC2PERIOD) >> 21)
381#define MC13783_TC2TRIODE (0x1 << 23) 1049#define MC13783_TC2TRIODE (0x1 << 23)
382 1050
383/* LED_CONTROL5 */ 1051/* LED_CONTROL5 (56) */
384#define MC13783_LEDR3 (0x3 << 0) 1052#define MC13783_LEDR3 (0x3 << 0)
385 #define MC13783_LEDR3w(x) (((x) << 0) & MC13783_LEDR3) 1053 #define MC13783_LEDR3w(x) (((x) << 0) & MC13783_LEDR3)
386 #define MC13783_LEDR3r(x) (((x) & MC13783_LEDR3) >> 0) 1054 #define MC13783_LEDR3r(x) (((x) & MC13783_LEDR3) >> 0)
387#define MC13783_LEDG3 (0x3 << 2) 1055#define MC13783_LEDG3 (0x3 << 2)
388 #define MC13783_LEDG3w(x) (((x) << 2) & MC13783_LEDG3) 1056 #define MC13783_LEDG3w(x) (((x) << 2) & MC13783_LEDG3)
389 #define MC13783_LEDG3r(x) (((x) & MC13783_LEDG3) >> 2) 1057 #define MC13783_LEDG3r(x) (((x) & MC13783_LEDG3) >> 2)
390#define MC13783_LEDB3 (0x3 << 4) 1058#define MC13783_LEDB3 (0x3 << 4)
391 #define MC13783_LEDB3w(x) (((x) << 4) & MC13783_LEDB3) 1059 #define MC13783_LEDB3w(x) (((x) << 4) & MC13783_LEDB3)
392 #define MC13783_LEDB3r(x) (((x) & MC13783_LEDB3) >> 4) 1060 #define MC13783_LEDB3r(x) (((x) & MC13783_LEDB3) >> 4)
393#define MC13783_LEDR3DC (0x1f << 6) 1061#define MC13783_LEDR3DC (0x1f << 6)
394 #define MC13783_LEDR3DCw(x) (((x) << 6) & MC13783_LEDR3DC) 1062 #define MC13783_LEDR3DCw(x) (((x) << 6) & MC13783_LEDR3DC)
395 #define MC13783_LEDR3DCr(x) (((x) & MC13783_LEDR3DC) >> 6) 1063 #define MC13783_LEDR3DCr(x) (((x) & MC13783_LEDR3DC) >> 6)
396#define MC13783_LEDG3DC (0x1f << 11) 1064#define MC13783_LEDG3DC (0x1f << 11)
397 #define MC13783_LEDG3DCw(x) (((x) << 11) & MC13783_LEDG3DC) 1065 #define MC13783_LEDG3DCw(x) (((x) << 11) & MC13783_LEDG3DC)
398 #define MC13783_LEDG3DCr(x) (((x) & MC13783_LEDG3DC) >> 11) 1066 #define MC13783_LEDG3DCr(x) (((x) & MC13783_LEDG3DC) >> 11)
399#define MC13783_LEDB3DC (0x1f << 16) 1067#define MC13783_LEDB3DC (0x1f << 16)
400 #define MC13783_LEDB3DCw(x) (((x) << 16) & MC13783_LEDB3DC) 1068 #define MC13783_LEDB3DCw(x) (((x) << 16) & MC13783_LEDB3DC)
401 #define MC13783_LEDB3DCr(x) (((x) & MC13783_LEDB3DC) >> 16) 1069 #define MC13783_LEDB3DCr(x) (((x) & MC13783_LEDB3DC) >> 16)
402#define MC13783_TC3PERIOD (0x3 << 21) 1070#define MC13783_TC3PERIOD (0x3 << 21)
403 #define MC13783_TC3PERIODw(x) (((x) << 21) & MC13783_TC3PERIOD) 1071 #define MC13783_TC3PERIODw(x) (((x) << 21) & MC13783_TC3PERIOD)
404 #define MC13783_TC3PERIODr(x) (((x) & MC13783_TC3PERIOD) >> 21) 1072 #define MC13783_TC3PERIODr(x) (((x) & MC13783_TC3PERIOD) >> 21)
405#define MC13783_TC3TRIODE (0x1 << 23) 1073#define MC13783_TC3TRIODE (0x1 << 23)
406
407/* TRIM0 */
408/* TRIM1 */
409/* TEST0 */
410/* TEST1 */
411/* TEST2 */
412/* TEST3 */
413 1074
414void mc13783_init(void); 1075void mc13783_init(void);
415void mc13783_close(void); 1076void mc13783_close(void);
diff --git a/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c b/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c
index 27c6957184..d26d708da1 100644
--- a/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/adc-imx31.c
@@ -102,5 +102,5 @@ void adc_init(void)
102 mc13783_write(MC13783_ADC1, MC13783_ADEN); 102 mc13783_write(MC13783_ADC1, MC13783_ADEN);
103 /* Enable the ADCDONE interrupt - notifications are dispatched by 103 /* Enable the ADCDONE interrupt - notifications are dispatched by
104 * event handler. */ 104 * event handler. */
105 mc13783_clear(MC13783_INTERRUPT_MASK0, MC13783_ADCDONE); 105 mc13783_clear(MC13783_INTERRUPT_MASK0, MC13783_ADCDONEM);
106} 106}
diff --git a/firmware/target/arm/imx31/gigabeat-s/mc13783-imx31.c b/firmware/target/arm/imx31/gigabeat-s/mc13783-imx31.c
index ddf8d1360f..4f2bd9d931 100644
--- a/firmware/target/arm/imx31/gigabeat-s/mc13783-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/mc13783-imx31.c
@@ -74,18 +74,18 @@ static void mc13783_interrupt_thread(void)
74 74
75 gpio_enable_event(MC13783_GPIO_NUM, MC13783_EVENT_ID); 75 gpio_enable_event(MC13783_GPIO_NUM, MC13783_EVENT_ID);
76 76
77 if (pending[1] & MC13783_TODA) /* only needs to be polled on startup */ 77 if (pending[1] & MC13783_TODAI) /* only needs to be polled on startup */
78 mc13783_alarm_start(); 78 mc13783_alarm_start();
79 79
80 /* Check initial states for events with a sense bit */ 80 /* Check initial states for events with a sense bit */
81 value = mc13783_read(MC13783_INTERRUPT_SENSE0); 81 value = mc13783_read(MC13783_INTERRUPT_SENSE0);
82 usb_set_status(value & MC13783_USB4V4); 82 usb_set_status(value & MC13783_USB4V4S);
83 set_charger_inserted(value & MC13783_CHGDET); 83 set_charger_inserted(value & MC13783_CHGDETS);
84 84
85 value = mc13783_read(MC13783_INTERRUPT_SENSE1); 85 value = mc13783_read(MC13783_INTERRUPT_SENSE1);
86 button_power_set_state((value & MC13783_ONOFD1) == 0); 86 button_power_set_state((value & MC13783_ONOFD1S) == 0);
87#ifdef HAVE_HEADPHONE_DETECTION 87#ifdef HAVE_HEADPHONE_DETECTION
88 set_headphones_inserted((value & MC13783_ONOFD2) == 0); 88 set_headphones_inserted((value & MC13783_ONOFD2S) == 0);
89#endif 89#endif
90 90
91 pending[0] = pending[1] = 0xffffff; 91 pending[0] = pending[1] = 0xffffff;
@@ -93,8 +93,9 @@ static void mc13783_interrupt_thread(void)
93 93
94 /* Enable desired PMIC interrupts - some are unmasked in the drivers that 94 /* Enable desired PMIC interrupts - some are unmasked in the drivers that
95 * handle a specific task */ 95 * handle a specific task */
96 mc13783_clear(MC13783_INTERRUPT_MASK0, MC13783_CHGDET); 96 mc13783_clear(MC13783_INTERRUPT_MASK0, MC13783_CHGDETM);
97 mc13783_clear(MC13783_INTERRUPT_MASK1, MC13783_ONOFD1 | MC13783_ONOFD2); 97 mc13783_clear(MC13783_INTERRUPT_MASK1, MC13783_ONOFD1M |
98 MC13783_ONOFD2M);
98 99
99 while (1) 100 while (1)
100 { 101 {
@@ -116,20 +117,20 @@ static void mc13783_interrupt_thread(void)
116 /* Handle ...PENDING0 */ 117 /* Handle ...PENDING0 */
117 118
118 /* Handle interrupts without a sense bit */ 119 /* Handle interrupts without a sense bit */
119 if (pending[0] & MC13783_ADCDONE) 120 if (pending[0] & MC13783_ADCDONEI)
120 adc_done(); 121 adc_done();
121 122
122 /* Handle interrupts that have a sense bit that needs to 123 /* Handle interrupts that have a sense bit that needs to
123 * be checked */ 124 * be checked */
124 if (pending[0] & (MC13783_CHGDET | MC13783_USB4V4)) 125 if (pending[0] & (MC13783_CHGDETI | MC13783_USB4V4I))
125 { 126 {
126 value = mc13783_read(MC13783_INTERRUPT_SENSE0); 127 value = mc13783_read(MC13783_INTERRUPT_SENSE0);
127 128
128 if (pending[0] & MC13783_CHGDET) 129 if (pending[0] & MC13783_CHGDETI)
129 set_charger_inserted(value & MC13783_CHGDET); 130 set_charger_inserted(value & MC13783_CHGDETS);
130 131
131 if (pending[0] & MC13783_USB4V4) 132 if (pending[0] & MC13783_USB4V4I)
132 usb_set_status(value & MC13783_USB4V4); 133 usb_set_status(value & MC13783_USB4V4S);
133 } 134 }
134 } 135 }
135 136
@@ -142,15 +143,15 @@ static void mc13783_interrupt_thread(void)
142 143
143 /* Handle interrupts that have a sense bit that needs to 144 /* Handle interrupts that have a sense bit that needs to
144 * be checked */ 145 * be checked */
145 if (pending[1] & (MC13783_ONOFD1 | MC13783_ONOFD2)) 146 if (pending[1] & (MC13783_ONOFD1I | MC13783_ONOFD2I))
146 { 147 {
147 value = mc13783_read(MC13783_INTERRUPT_SENSE1); 148 value = mc13783_read(MC13783_INTERRUPT_SENSE1);
148 149
149 if (pending[1] & MC13783_ONOFD1) 150 if (pending[1] & MC13783_ONOFD1I)
150 button_power_set_state((value & MC13783_ONOFD1) == 0); 151 button_power_set_state((value & MC13783_ONOFD1S) == 0);
151#ifdef HAVE_HEADPHONE_DETECTION 152#ifdef HAVE_HEADPHONE_DETECTION
152 if (pending[1] & MC13783_ONOFD2) 153 if (pending[1] & MC13783_ONOFD2I)
153 set_headphones_inserted((value & MC13783_ONOFD2) == 0); 154 set_headphones_inserted((value & MC13783_ONOFD2S) == 0);
154#endif 155#endif
155 } 156 }
156 } 157 }
diff --git a/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c b/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c
index a90384d35e..f12fd8f0b1 100644
--- a/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c
+++ b/firmware/target/arm/imx31/gigabeat-s/usb-imx31.c
@@ -61,7 +61,7 @@ int usb_detect(void)
61/* Read the immediate state of the cable from the PMIC */ 61/* Read the immediate state of the cable from the PMIC */
62bool usb_plugged(void) 62bool usb_plugged(void)
63{ 63{
64 return mc13783_read(MC13783_INTERRUPT_SENSE0) & MC13783_USB4V4; 64 return mc13783_read(MC13783_INTERRUPT_SENSE0) & MC13783_USB4V4S;
65} 65}
66 66
67void usb_init_device(void) 67void usb_init_device(void)
@@ -73,7 +73,7 @@ void usb_init_device(void)
73 /* Module will be turned off later after firmware init */ 73 /* Module will be turned off later after firmware init */
74 usb_drv_startup(); 74 usb_drv_startup();
75 75
76 mc13783_clear(MC13783_INTERRUPT_MASK0, MC13783_USB4V4); 76 mc13783_clear(MC13783_INTERRUPT_MASK0, MC13783_USB4V4M);
77} 77}
78 78
79void usb_enable(bool on) 79void usb_enable(bool on)
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-12 20:53:25 +0000