diff options
author | Marcoen Hirschberg <marcoen@gmail.com> | 2008-03-27 11:29:24 +0000 |
---|---|---|
committer | Marcoen Hirschberg <marcoen@gmail.com> | 2008-03-27 11:29:24 +0000 |
commit | c7e5d78241699500b18ce783607af7ae52ee021f (patch) | |
tree | a6aaf5c7d59fedf18fe944956c4e2c3b72cbd638 | |
parent | be40427baeacb88e27a4d8117addd60ca1fbc4c7 (diff) | |
download | rockbox-c7e5d78241699500b18ce783607af7ae52ee021f.tar.gz rockbox-c7e5d78241699500b18ce783607af7ae52ee021f.zip |
initial Meizu M6SL port
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16844 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | apps/SOURCES | 2 | ||||
-rw-r--r-- | apps/keymaps/keymap-meizu-m6sl.c | 303 | ||||
-rw-r--r-- | bootloader/SOURCES | 2 | ||||
-rw-r--r-- | firmware/SOURCES | 7 | ||||
-rw-r--r-- | firmware/drivers/tuner/tea5760uk.c | 135 | ||||
-rw-r--r-- | firmware/export/config-meizu-m6sl.h | 170 | ||||
-rw-r--r-- | firmware/export/config.h | 15 | ||||
-rw-r--r-- | firmware/export/s5l8700.h | 536 | ||||
-rw-r--r-- | firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h | 33 | ||||
-rw-r--r-- | firmware/target/arm/s5l8700/meizu-m6sl/button-target.h | 52 | ||||
-rwxr-xr-x | tools/configure | 26 | ||||
-rw-r--r-- | tools/makesrc.inc | 3 | ||||
-rw-r--r-- | uisimulator/sdl/button.c | 31 | ||||
-rw-r--r-- | uisimulator/sdl/uisdl.h | 13 |
14 files changed, 1323 insertions, 5 deletions
diff --git a/apps/SOURCES b/apps/SOURCES index 96b5c0f825..7096d06a41 100644 --- a/apps/SOURCES +++ b/apps/SOURCES | |||
@@ -175,4 +175,6 @@ keymaps/keymap-mr500.c | |||
175 | keymaps/keymap-mr100.c | 175 | keymaps/keymap-mr100.c |
176 | #elif CONFIG_KEYPAD == COWOND2_PAD | 176 | #elif CONFIG_KEYPAD == COWOND2_PAD |
177 | keymaps/keymap-cowond2.c | 177 | keymaps/keymap-cowond2.c |
178 | #elif CONFIG_KEYPAD == MEIZU_M6SL_PAD | ||
179 | keymaps/keymap-meizu-m6sl.c | ||
178 | #endif | 180 | #endif |
diff --git a/apps/keymaps/keymap-meizu-m6sl.c b/apps/keymaps/keymap-meizu-m6sl.c new file mode 100644 index 0000000000..a473c88311 --- /dev/null +++ b/apps/keymaps/keymap-meizu-m6sl.c | |||
@@ -0,0 +1,303 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2006 Jonathan Gordon | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | |||
20 | /* Button Code Definitions for the toshiba gigabeat target */ | ||
21 | #include <stdio.h> | ||
22 | #include <string.h> | ||
23 | #include <stdlib.h> | ||
24 | |||
25 | #include "config.h" | ||
26 | #include "action.h" | ||
27 | #include "button.h" | ||
28 | #include "settings.h" | ||
29 | |||
30 | /* | ||
31 | * The format of the list is as follows | ||
32 | * { Action Code, Button code, Prereq button code } | ||
33 | * if there's no need to check the previous button's value, use BUTTON_NONE | ||
34 | * Insert LAST_ITEM_IN_LIST at the end of each mapping | ||
35 | */ | ||
36 | |||
37 | /* CONTEXT_CUSTOM's used in this file... | ||
38 | |||
39 | CONTEXT_CUSTOM|CONTEXT_TREE = the standard list/tree defines (without directions) | ||
40 | CONTEXT_CUSTOM|CONTEXT_SETTINGS = the direction keys for the eq/col picker screens | ||
41 | i.e where up/down is inc/dec | ||
42 | CONTEXT_SETTINGS = up/down is prev/next, l/r is inc/dec | ||
43 | |||
44 | */ | ||
45 | |||
46 | |||
47 | static const struct button_mapping button_context_standard[] = { | ||
48 | { ACTION_STD_PREV, BUTTON_UP, BUTTON_NONE }, | ||
49 | { ACTION_STD_PREVREPEAT, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, | ||
50 | { ACTION_STD_NEXT, BUTTON_DOWN, BUTTON_NONE }, | ||
51 | { ACTION_STD_NEXTREPEAT, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, | ||
52 | |||
53 | { ACTION_STD_CANCEL, BUTTON_LEFT, BUTTON_NONE }, | ||
54 | |||
55 | { ACTION_STD_CONTEXT, BUTTON_SELECT|BUTTON_REPEAT,BUTTON_SELECT }, | ||
56 | |||
57 | { ACTION_STD_QUICKSCREEN, BUTTON_MENU|BUTTON_REPEAT, BUTTON_MENU }, | ||
58 | { ACTION_STD_MENU, BUTTON_MENU|BUTTON_REL, BUTTON_MENU }, | ||
59 | |||
60 | { ACTION_STD_OK, BUTTON_SELECT|BUTTON_REL, BUTTON_SELECT }, | ||
61 | { ACTION_STD_OK, BUTTON_RIGHT, BUTTON_NONE }, | ||
62 | |||
63 | LAST_ITEM_IN_LIST | ||
64 | }; /* button_context_standard */ | ||
65 | |||
66 | |||
67 | static const struct button_mapping button_context_wps[] = { | ||
68 | { ACTION_WPS_PLAY, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY }, | ||
69 | { ACTION_WPS_STOP, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE }, | ||
70 | |||
71 | { ACTION_WPS_SKIPNEXT, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT }, | ||
72 | { ACTION_WPS_SKIPPREV, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT }, | ||
73 | |||
74 | { ACTION_WPS_SEEKBACK, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, | ||
75 | { ACTION_WPS_SEEKFWD, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, | ||
76 | { ACTION_WPS_STOPSEEK, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT|BUTTON_REPEAT }, | ||
77 | { ACTION_WPS_STOPSEEK, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT|BUTTON_REPEAT }, | ||
78 | |||
79 | { ACTION_WPS_ABSETB_NEXTDIR, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_NONE }, | ||
80 | { ACTION_WPS_ABSETA_PREVDIR, BUTTON_PLAY|BUTTON_LEFT, BUTTON_NONE }, | ||
81 | { ACTION_WPS_ABRESET, BUTTON_PLAY|BUTTON_SELECT, BUTTON_NONE }, | ||
82 | |||
83 | { ACTION_WPS_VOLDOWN, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, | ||
84 | { ACTION_WPS_VOLDOWN, BUTTON_DOWN, BUTTON_NONE }, | ||
85 | { ACTION_WPS_VOLUP, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, | ||
86 | { ACTION_WPS_VOLUP, BUTTON_UP, BUTTON_NONE }, | ||
87 | |||
88 | { ACTION_WPS_PITCHSCREEN, BUTTON_PLAY|BUTTON_UP, BUTTON_PLAY }, | ||
89 | { ACTION_WPS_PITCHSCREEN, BUTTON_PLAY|BUTTON_DOWN, BUTTON_PLAY }, | ||
90 | |||
91 | { ACTION_WPS_QUICKSCREEN, BUTTON_MENU|BUTTON_REPEAT, BUTTON_MENU }, | ||
92 | { ACTION_WPS_MENU, BUTTON_MENU|BUTTON_REL, BUTTON_MENU }, | ||
93 | { ACTION_WPS_CONTEXT, BUTTON_SELECT|BUTTON_REPEAT, BUTTON_SELECT }, | ||
94 | |||
95 | { ACTION_WPS_ID3SCREEN, BUTTON_PLAY|BUTTON_MENU, BUTTON_NONE }, | ||
96 | { ACTION_WPS_BROWSE, BUTTON_SELECT|BUTTON_REL, BUTTON_SELECT }, | ||
97 | |||
98 | LAST_ITEM_IN_LIST | ||
99 | }; /* button_context_wps */ | ||
100 | |||
101 | static const struct button_mapping button_context_list[] = { | ||
102 | { ACTION_LISTTREE_PGUP, BUTTON_PLAY|BUTTON_UP, BUTTON_PLAY }, | ||
103 | { ACTION_LISTTREE_PGUP, BUTTON_UP|BUTTON_REL, BUTTON_PLAY|BUTTON_UP }, | ||
104 | { ACTION_LISTTREE_PGUP, BUTTON_PLAY|BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, | ||
105 | { ACTION_LISTTREE_PGDOWN, BUTTON_PLAY|BUTTON_DOWN, BUTTON_PLAY }, | ||
106 | { ACTION_LISTTREE_PGDOWN, BUTTON_DOWN|BUTTON_REL, BUTTON_PLAY|BUTTON_DOWN }, | ||
107 | { ACTION_LISTTREE_PGDOWN, BUTTON_PLAY|BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, | ||
108 | |||
109 | LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD) | ||
110 | }; /* button_context_list */ | ||
111 | |||
112 | static const struct button_mapping button_context_tree[] = { | ||
113 | { ACTION_TREE_WPS, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY }, | ||
114 | { ACTION_TREE_STOP, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE }, | ||
115 | |||
116 | LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_LIST) | ||
117 | }; /* button_context_tree */ | ||
118 | |||
119 | static const struct button_mapping button_context_listtree_scroll_with_combo[] = { | ||
120 | { ACTION_NONE, BUTTON_PLAY, BUTTON_NONE }, | ||
121 | { ACTION_TREE_PGLEFT, BUTTON_PLAY|BUTTON_LEFT, BUTTON_PLAY }, | ||
122 | { ACTION_TREE_PGLEFT, BUTTON_LEFT|BUTTON_REL, BUTTON_PLAY|BUTTON_LEFT }, | ||
123 | { ACTION_TREE_PGLEFT, BUTTON_PLAY|BUTTON_LEFT, BUTTON_LEFT|BUTTON_REL }, | ||
124 | { ACTION_TREE_ROOT_INIT, BUTTON_PLAY|BUTTON_LEFT|BUTTON_REPEAT, BUTTON_PLAY|BUTTON_LEFT }, | ||
125 | { ACTION_TREE_PGLEFT, BUTTON_PLAY|BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, | ||
126 | { ACTION_TREE_PGRIGHT, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_PLAY }, | ||
127 | { ACTION_TREE_PGRIGHT, BUTTON_RIGHT|BUTTON_REL, BUTTON_PLAY|BUTTON_RIGHT }, | ||
128 | { ACTION_TREE_PGRIGHT, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_RIGHT|BUTTON_REL }, | ||
129 | { ACTION_TREE_PGRIGHT, BUTTON_PLAY|BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, | ||
130 | LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_TREE), | ||
131 | }; | ||
132 | |||
133 | static const struct button_mapping button_context_listtree_scroll_without_combo[] = { | ||
134 | { ACTION_NONE, BUTTON_LEFT, BUTTON_NONE }, | ||
135 | { ACTION_STD_CANCEL, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT }, | ||
136 | { ACTION_TREE_ROOT_INIT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_LEFT }, | ||
137 | { ACTION_TREE_PGLEFT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, | ||
138 | { ACTION_TREE_PGLEFT, BUTTON_LEFT|BUTTON_REL, BUTTON_LEFT|BUTTON_REPEAT }, | ||
139 | { ACTION_NONE, BUTTON_RIGHT, BUTTON_NONE }, | ||
140 | { ACTION_STD_OK, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT }, | ||
141 | { ACTION_TREE_PGRIGHT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, | ||
142 | { ACTION_TREE_PGRIGHT, BUTTON_RIGHT|BUTTON_REL, BUTTON_RIGHT|BUTTON_REPEAT }, | ||
143 | LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_TREE), | ||
144 | }; | ||
145 | |||
146 | static const struct button_mapping button_context_settings[] = { | ||
147 | { ACTION_SETTINGS_INC, BUTTON_UP, BUTTON_NONE }, | ||
148 | { ACTION_SETTINGS_INCREPEAT, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, | ||
149 | { ACTION_SETTINGS_DEC, BUTTON_DOWN, BUTTON_NONE }, | ||
150 | { ACTION_SETTINGS_DECREPEAT, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, | ||
151 | { ACTION_STD_PREV, BUTTON_LEFT, BUTTON_NONE }, | ||
152 | { ACTION_STD_PREVREPEAT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, | ||
153 | { ACTION_STD_NEXT, BUTTON_RIGHT, BUTTON_NONE }, | ||
154 | { ACTION_STD_NEXTREPEAT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, | ||
155 | { ACTION_SETTINGS_RESET, BUTTON_PLAY, BUTTON_NONE }, | ||
156 | |||
157 | LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD) | ||
158 | }; /* button_context_settings */ | ||
159 | |||
160 | static const struct button_mapping button_context_settings_right_is_inc[] = { | ||
161 | { ACTION_SETTINGS_INC, BUTTON_RIGHT, BUTTON_NONE }, | ||
162 | { ACTION_SETTINGS_INCREPEAT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, | ||
163 | { ACTION_SETTINGS_DEC, BUTTON_LEFT, BUTTON_NONE }, | ||
164 | { ACTION_SETTINGS_DECREPEAT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, | ||
165 | { ACTION_STD_PREV, BUTTON_UP, BUTTON_NONE }, | ||
166 | { ACTION_STD_PREVREPEAT, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, | ||
167 | { ACTION_STD_NEXT, BUTTON_DOWN, BUTTON_NONE }, | ||
168 | { ACTION_STD_NEXTREPEAT, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, | ||
169 | { ACTION_SETTINGS_RESET, BUTTON_PLAY, BUTTON_NONE }, | ||
170 | |||
171 | LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD) | ||
172 | }; /* button_context_settingsgraphical */ | ||
173 | |||
174 | static const struct button_mapping button_context_yesno[] = { | ||
175 | { ACTION_YESNO_ACCEPT, BUTTON_SELECT, BUTTON_NONE }, | ||
176 | LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD) | ||
177 | }; /* button_context_settings_yesno */ | ||
178 | |||
179 | static const struct button_mapping button_context_colorchooser[] = { | ||
180 | { ACTION_STD_OK, BUTTON_PLAY|BUTTON_REL, BUTTON_NONE }, | ||
181 | LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_SETTINGS), | ||
182 | }; /* button_context_colorchooser */ | ||
183 | |||
184 | static const struct button_mapping button_context_eq[] = { | ||
185 | { ACTION_STD_OK, BUTTON_SELECT|BUTTON_REL, BUTTON_NONE }, | ||
186 | LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_CUSTOM|CONTEXT_SETTINGS), | ||
187 | }; /* button_context_eq */ | ||
188 | |||
189 | /** Bookmark Screen **/ | ||
190 | static const struct button_mapping button_context_bmark[] = { | ||
191 | { ACTION_BMS_DELETE, BUTTON_PLAY, BUTTON_NONE }, | ||
192 | |||
193 | LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_LIST), | ||
194 | }; /* button_context_bmark */ | ||
195 | |||
196 | static const struct button_mapping button_context_time[] = { | ||
197 | { ACTION_STD_CANCEL, BUTTON_LEFT, BUTTON_NONE }, | ||
198 | { ACTION_STD_OK, BUTTON_PLAY, BUTTON_NONE }, | ||
199 | LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_SETTINGS), | ||
200 | }; /* button_context_time */ | ||
201 | |||
202 | static const struct button_mapping button_context_quickscreen[] = { | ||
203 | { ACTION_QS_DOWNINV, BUTTON_UP, BUTTON_NONE }, | ||
204 | { ACTION_QS_DOWNINV, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, | ||
205 | { ACTION_QS_DOWN, BUTTON_DOWN, BUTTON_NONE }, | ||
206 | { ACTION_QS_DOWN, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, | ||
207 | { ACTION_QS_LEFT, BUTTON_LEFT, BUTTON_NONE }, | ||
208 | { ACTION_QS_LEFT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, | ||
209 | { ACTION_QS_RIGHT, BUTTON_RIGHT, BUTTON_NONE }, | ||
210 | { ACTION_QS_RIGHT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, | ||
211 | { ACTION_STD_CANCEL, BUTTON_MENU, BUTTON_NONE }, | ||
212 | |||
213 | LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD) | ||
214 | }; /* button_context_quickscreen */ | ||
215 | |||
216 | static const struct button_mapping button_context_pitchscreen[] = { | ||
217 | { ACTION_PS_INC_SMALL, BUTTON_UP, BUTTON_NONE }, | ||
218 | { ACTION_PS_INC_BIG, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, | ||
219 | { ACTION_PS_DEC_SMALL, BUTTON_DOWN, BUTTON_NONE }, | ||
220 | { ACTION_PS_DEC_BIG, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, | ||
221 | { ACTION_PS_NUDGE_LEFT, BUTTON_LEFT, BUTTON_NONE }, | ||
222 | { ACTION_PS_NUDGE_LEFTOFF, BUTTON_LEFT|BUTTON_REL, BUTTON_NONE }, | ||
223 | { ACTION_PS_NUDGE_RIGHT, BUTTON_RIGHT, BUTTON_NONE }, | ||
224 | { ACTION_PS_NUDGE_RIGHTOFF, BUTTON_RIGHT|BUTTON_REL, BUTTON_NONE }, | ||
225 | { ACTION_PS_TOGGLE_MODE, BUTTON_MENU, BUTTON_NONE }, | ||
226 | { ACTION_PS_RESET, BUTTON_PLAY, BUTTON_NONE }, | ||
227 | { ACTION_PS_EXIT, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE }, | ||
228 | |||
229 | LAST_ITEM_IN_LIST__NEXTLIST(CONTEXT_STD) | ||
230 | }; /* button_context_pitchcreen */ | ||
231 | |||
232 | static const struct button_mapping button_context_keyboard[] = { | ||
233 | { ACTION_KBD_LEFT, BUTTON_LEFT, BUTTON_NONE }, | ||
234 | { ACTION_KBD_LEFT, BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, | ||
235 | { ACTION_KBD_RIGHT, BUTTON_RIGHT, BUTTON_NONE }, | ||
236 | { ACTION_KBD_RIGHT, BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, | ||
237 | { ACTION_KBD_CURSOR_LEFT, BUTTON_PLAY|BUTTON_LEFT, BUTTON_NONE }, | ||
238 | { ACTION_KBD_CURSOR_LEFT, BUTTON_PLAY|BUTTON_LEFT|BUTTON_REPEAT, BUTTON_NONE }, | ||
239 | { ACTION_KBD_CURSOR_RIGHT, BUTTON_PLAY|BUTTON_RIGHT, BUTTON_NONE }, | ||
240 | { ACTION_KBD_CURSOR_RIGHT, BUTTON_PLAY|BUTTON_RIGHT|BUTTON_REPEAT, BUTTON_NONE }, | ||
241 | { ACTION_KBD_SELECT, BUTTON_SELECT, BUTTON_NONE }, | ||
242 | { ACTION_KBD_PAGE_FLIP, BUTTON_PLAY|BUTTON_MENU, BUTTON_NONE }, | ||
243 | { ACTION_KBD_DONE, BUTTON_PLAY|BUTTON_REL, BUTTON_PLAY }, | ||
244 | { ACTION_KBD_ABORT, BUTTON_PLAY|BUTTON_REPEAT, BUTTON_NONE }, | ||
245 | { ACTION_KBD_BACKSPACE, BUTTON_MENU, BUTTON_NONE }, | ||
246 | { ACTION_KBD_BACKSPACE, BUTTON_MENU|BUTTON_REPEAT, BUTTON_NONE }, | ||
247 | { ACTION_KBD_UP, BUTTON_UP, BUTTON_NONE }, | ||
248 | { ACTION_KBD_UP, BUTTON_UP|BUTTON_REPEAT, BUTTON_NONE }, | ||
249 | { ACTION_KBD_DOWN, BUTTON_DOWN, BUTTON_NONE }, | ||
250 | { ACTION_KBD_DOWN, BUTTON_DOWN|BUTTON_REPEAT, BUTTON_NONE }, | ||
251 | // { ACTION_KBD_MORSE_INPUT, BUTTON_PLAY|BUTTON_POWER, BUTTON_NONE }, | ||
252 | { ACTION_KBD_MORSE_SELECT, BUTTON_SELECT|BUTTON_REL, BUTTON_NONE }, | ||
253 | |||
254 | LAST_ITEM_IN_LIST | ||
255 | }; /* button_context_keyboard */ | ||
256 | |||
257 | |||
258 | const struct button_mapping* get_context_mapping(int context) | ||
259 | { | ||
260 | switch (context) | ||
261 | { | ||
262 | case CONTEXT_STD: | ||
263 | return button_context_standard; | ||
264 | case CONTEXT_WPS: | ||
265 | return button_context_wps; | ||
266 | |||
267 | case CONTEXT_LIST: | ||
268 | return button_context_list; | ||
269 | case CONTEXT_MAINMENU: | ||
270 | case CONTEXT_TREE: | ||
271 | if (global_settings.hold_lr_for_scroll_in_list) | ||
272 | return button_context_listtree_scroll_without_combo; | ||
273 | else | ||
274 | return button_context_listtree_scroll_with_combo; | ||
275 | case CONTEXT_CUSTOM|CONTEXT_TREE: | ||
276 | return button_context_tree; | ||
277 | |||
278 | case CONTEXT_SETTINGS: | ||
279 | return button_context_settings; | ||
280 | case CONTEXT_CUSTOM|CONTEXT_SETTINGS: | ||
281 | return button_context_settings_right_is_inc; | ||
282 | |||
283 | case CONTEXT_SETTINGS_COLOURCHOOSER: | ||
284 | return button_context_colorchooser; | ||
285 | case CONTEXT_SETTINGS_EQ: | ||
286 | return button_context_eq; | ||
287 | |||
288 | case CONTEXT_SETTINGS_TIME: | ||
289 | return button_context_time; | ||
290 | |||
291 | case CONTEXT_YESNOSCREEN: | ||
292 | return button_context_yesno; | ||
293 | case CONTEXT_BOOKMARKSCREEN: | ||
294 | return button_context_bmark; | ||
295 | case CONTEXT_QUICKSCREEN: | ||
296 | return button_context_quickscreen; | ||
297 | case CONTEXT_PITCHSCREEN: | ||
298 | return button_context_pitchscreen; | ||
299 | case CONTEXT_KEYBOARD: | ||
300 | return button_context_keyboard; | ||
301 | } | ||
302 | return button_context_standard; | ||
303 | } | ||
diff --git a/bootloader/SOURCES b/bootloader/SOURCES index 9e961eeb29..2854878084 100644 --- a/bootloader/SOURCES +++ b/bootloader/SOURCES | |||
@@ -27,4 +27,6 @@ iriver_h300.c | |||
27 | mrobe500.c | 27 | mrobe500.c |
28 | #elif defined(CPU_TCC77X) || defined(CPU_TCC780X) | 28 | #elif defined(CPU_TCC77X) || defined(CPU_TCC780X) |
29 | telechips.c | 29 | telechips.c |
30 | #elif defined(MEIZU_M6SL) | ||
31 | meizu_m6sl.c | ||
30 | #endif | 32 | #endif |
diff --git a/firmware/SOURCES b/firmware/SOURCES index 8fe5661759..4937e6e6c6 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES | |||
@@ -924,3 +924,10 @@ target/arm/tcc780x/cowond2/pcm-cowond2.c | |||
924 | #endif /* BOOTLOADER */ | 924 | #endif /* BOOTLOADER */ |
925 | #endif /* SIMULATOR */ | 925 | #endif /* SIMULATOR */ |
926 | #endif /* COWON_D2 */ | 926 | #endif /* COWON_D2 */ |
927 | |||
928 | #ifdef MEIZU_M6SL | ||
929 | #ifndef SIMULATOR | ||
930 | #ifndef BOOTLOADER | ||
931 | #endif /* BOOTLOADER */ | ||
932 | #endif /* SIMULATOR */ | ||
933 | #endif /* MEIZU_M6SL */ | ||
diff --git a/firmware/drivers/tuner/tea5760uk.c b/firmware/drivers/tuner/tea5760uk.c new file mode 100644 index 0000000000..8ac6cb2dbc --- /dev/null +++ b/firmware/drivers/tuner/tea5760uk.c | |||
@@ -0,0 +1,135 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * Tuner "middleware" for Philips TEA5760 chip | ||
10 | * | ||
11 | * Copyright (C) 2004 Jörg Hohensohn | ||
12 | * | ||
13 | * All files in this archive are subject to the GNU General Public License. | ||
14 | * See the file COPYING in the source tree root for full license agreement. | ||
15 | * | ||
16 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
17 | * KIND, either express or implied. | ||
18 | * | ||
19 | ****************************************************************************/ | ||
20 | #include "config.h" | ||
21 | #include <stdbool.h> | ||
22 | #include <string.h> | ||
23 | #include <stdlib.h> | ||
24 | #include "kernel.h" | ||
25 | #include "tuner.h" /* tuner abstraction interface */ | ||
26 | #include "fmradio.h" | ||
27 | #include "fmradio_i2c.h" /* physical interface driver */ | ||
28 | |||
29 | #define I2C_ADR 0xC0 | ||
30 | static unsigned char write_bytes[7] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; | ||
31 | |||
32 | static void tea5760uk_set_clear(int byte, unsigned char bits, int set) | ||
33 | { | ||
34 | write_bytes[byte] &= ~bits; | ||
35 | if (set) | ||
36 | write_bytes[byte] |= bits; | ||
37 | } | ||
38 | |||
39 | /* tuner abstraction layer: set something to the tuner */ | ||
40 | int tea5760uk_set(int setting, int value) | ||
41 | { | ||
42 | switch(setting) | ||
43 | { | ||
44 | case RADIO_SLEEP: | ||
45 | /* init values */ | ||
46 | write_bytes[0] |= (1<<7); /* mute */ | ||
47 | #if CONFIG_TUNER_XTAL == 32768 | ||
48 | /* 32.768kHz, soft mute, stereo noise cancelling */ | ||
49 | write_bytes[3] |= (1<<4) | (1<<3) | (1<<1); | ||
50 | #else | ||
51 | /* soft mute, stereo noise cancelling */ | ||
52 | write_bytes[3] |= (1<<3) | (1<<1); | ||
53 | #endif | ||
54 | /* sleep / standby mode */ | ||
55 | tea5760uk_set_clear(3, (1<<6), value); | ||
56 | break; | ||
57 | |||
58 | case RADIO_FREQUENCY: | ||
59 | { | ||
60 | int n; | ||
61 | #if CONFIG_TUNER_XTAL == 32768 | ||
62 | n = (4 * (value - 225000) + 16384) / 32768; | ||
63 | #else | ||
64 | n = (4 * (value - 225000)) / 50000; | ||
65 | #endif | ||
66 | write_bytes[6] = (write_bytes[6] & 0xC0) | (n >> 8); | ||
67 | write_bytes[7] = n; | ||
68 | } | ||
69 | break; | ||
70 | |||
71 | case RADIO_SCAN_FREQUENCY: | ||
72 | tea5760uk_set(RADIO_FREQUENCY, value); | ||
73 | sleep(HZ/30); | ||
74 | return tea5760uk_get(RADIO_TUNED); | ||
75 | |||
76 | case RADIO_MUTE: | ||
77 | tea5760uk_set_clear(3, (1<<2), value); | ||
78 | break; | ||
79 | |||
80 | case RADIO_REGION: | ||
81 | { | ||
82 | const struct tea5760uk_region_data *rd = | ||
83 | &tea5760uk_region_data[value]; | ||
84 | |||
85 | tea5760uk_set_clear(4, (1<<1), rd->deemphasis); | ||
86 | tea5760uk_set_clear(3, (1<<5), rd->band); | ||
87 | break; | ||
88 | } | ||
89 | case RADIO_FORCE_MONO: | ||
90 | tea5760uk_set_clear(4, (1<<3), value); | ||
91 | break; | ||
92 | default: | ||
93 | return -1; | ||
94 | } | ||
95 | |||
96 | fmradio_i2c_write(I2C_ADR, write_bytes, sizeof(write_bytes)); | ||
97 | return 1; | ||
98 | } | ||
99 | |||
100 | /* tuner abstraction layer: read something from the tuner */ | ||
101 | int tea5760uk_get(int setting) | ||
102 | { | ||
103 | unsigned char read_bytes[16]; | ||
104 | int val = -1; /* default for unsupported query */ | ||
105 | |||
106 | fmradio_i2c_read(I2C_ADR, read_bytes, sizeof(read_bytes)); | ||
107 | |||
108 | switch(setting) | ||
109 | { | ||
110 | case RADIO_PRESENT: | ||
111 | val = 1; /* true */ | ||
112 | break; | ||
113 | |||
114 | case RADIO_TUNED: | ||
115 | val = 0; | ||
116 | if (read_bytes[0] & (1<<4)) /* IF count correct */ | ||
117 | { | ||
118 | val = read_bytes[8] >> 1; /* IF counter */ | ||
119 | val = (abs(val - 0x36) < 2); /* close match */ | ||
120 | } | ||
121 | break; | ||
122 | |||
123 | case RADIO_STEREO: | ||
124 | val = read_bytes[9] >> 2; | ||
125 | break; | ||
126 | } | ||
127 | |||
128 | return val; | ||
129 | } | ||
130 | |||
131 | void tea5760uk_dbg_info(struct tea5760uk_dbg_info *info) | ||
132 | { | ||
133 | fmradio_i2c_read(I2C_ADR, info->read_regs, 5); | ||
134 | memcpy(info->write_regs, write_bytes, 5); | ||
135 | } | ||
diff --git a/firmware/export/config-meizu-m6sl.h b/firmware/export/config-meizu-m6sl.h new file mode 100644 index 0000000000..1c3b5f8a23 --- /dev/null +++ b/firmware/export/config-meizu-m6sl.h | |||
@@ -0,0 +1,170 @@ | |||
1 | /* | ||
2 | * This config file is for iAudio X5 | ||
3 | */ | ||
4 | #define TARGET_TREE /* this target is using the target tree system */ | ||
5 | |||
6 | /* For Rolo and boot loader */ | ||
7 | #define MODEL_NUMBER 1 | ||
8 | |||
9 | /* define this if you have recording possibility */ | ||
10 | //#define HAVE_RECORDING | ||
11 | |||
12 | /* Define bitmask of input sources - recordable bitmask can be defined | ||
13 | explicitly if different */ | ||
14 | #define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN | SRC_CAP_FMRADIO) | ||
15 | |||
16 | /* define the bitmask of hardware sample rates */ | ||
17 | #define HW_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11) | ||
18 | |||
19 | /* define the bitmask of recording sample rates */ | ||
20 | #define REC_SAMPR_CAPS (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11) | ||
21 | |||
22 | /* define this if you have a bitmap LCD display */ | ||
23 | #define HAVE_LCD_BITMAP | ||
24 | |||
25 | /* define this if you can flip your LCD */ | ||
26 | //#define HAVE_LCD_FLIP | ||
27 | |||
28 | /* define this if you have a colour LCD */ | ||
29 | #define HAVE_LCD_COLOR | ||
30 | |||
31 | /* define this if you want album art for this target */ | ||
32 | #define HAVE_ALBUMART | ||
33 | |||
34 | /* define this if you can invert the colours on your LCD */ | ||
35 | //#define HAVE_LCD_INVERT | ||
36 | |||
37 | /* define this if you have access to the quickscreen */ | ||
38 | #define HAVE_QUICKSCREEN | ||
39 | |||
40 | /* define this if you have access to the pitchscreen */ | ||
41 | #define HAVE_PITCHSCREEN | ||
42 | |||
43 | /* define this if you would like tagcache to build on this target */ | ||
44 | #define HAVE_TAGCACHE | ||
45 | |||
46 | /* define this if you have a flash memory storage */ | ||
47 | #define HAVE_FLASH_STORAGE | ||
48 | |||
49 | /* LCD dimensions */ | ||
50 | #define LCD_WIDTH 320 | ||
51 | #define LCD_HEIGHT 240 | ||
52 | #define LCD_DEPTH 16 /* pseudo 262.144 colors */ | ||
53 | #define LCD_PIXELFORMAT RGB565 /* rgb565 */ | ||
54 | |||
55 | /* Define this if your LCD can be enabled/disabled */ | ||
56 | //#define HAVE_LCD_ENABLE | ||
57 | |||
58 | /* Define this if your LCD can be put to sleep. HAVE_LCD_ENABLE | ||
59 | should be defined as well. */ | ||
60 | //#define HAVE_LCD_SLEEP | ||
61 | |||
62 | #define CONFIG_KEYPAD MEIZU_M6SL_PAD | ||
63 | |||
64 | //#define AB_REPEAT_ENABLE 1 | ||
65 | //#define ACTION_WPSAB_SINGLE ACTION_WPS_BROWSE | ||
66 | |||
67 | /* Define this if you do software codec */ | ||
68 | #define CONFIG_CODEC SWCODEC | ||
69 | |||
70 | /* define this if you have a real-time clock */ | ||
71 | #define CONFIG_RTC RTC_S5L8700 | ||
72 | //#define CONFIG_RTC RTC_S35390A | ||
73 | |||
74 | #define CONFIG_LCD LCD_S6D0129 | ||
75 | |||
76 | /* Define this for LCD backlight available */ | ||
77 | #define HAVE_BACKLIGHT | ||
78 | #define HAVE_BACKLIGHT_BRIGHTNESS | ||
79 | |||
80 | /* Define this if you have a software controlled poweroff */ | ||
81 | #define HAVE_SW_POWEROFF | ||
82 | |||
83 | /* The number of bytes reserved for loadable codecs */ | ||
84 | #define CODEC_SIZE 0x80000 | ||
85 | |||
86 | /* The number of bytes reserved for loadable plugins */ | ||
87 | #define PLUGIN_BUFFER_SIZE 0x80000 | ||
88 | |||
89 | /* FM Tuner */ | ||
90 | #define CONFIG_TUNER TEA5760 | ||
91 | #define CONFIG_TUNER_XTAL 32768 | ||
92 | |||
93 | //#define HAVE_TLV320 | ||
94 | |||
95 | /* TLV320 has no tone controls, so we use the software ones */ | ||
96 | #define HAVE_SW_TONE_CONTROLS | ||
97 | |||
98 | #define BATTERY_CAPACITY_DEFAULT 700 /* default battery capacity */ | ||
99 | #define BATTERY_CAPACITY_MIN 500 /* min. capacity selectable */ | ||
100 | #define BATTERY_CAPACITY_MAX 2250 /* max. capacity selectable */ | ||
101 | #define BATTERY_CAPACITY_INC 50 /* capacity increment */ | ||
102 | #define BATTERY_TYPES_COUNT 1 /* only one type */ | ||
103 | |||
104 | /* Hardware controlled charging? FIXME */ | ||
105 | #define CONFIG_CHARGING CHARGING_SIMPLE | ||
106 | |||
107 | #ifndef SIMULATOR | ||
108 | |||
109 | /* Define this if your LCD can set contrast */ | ||
110 | //#define HAVE_LCD_CONTRAST | ||
111 | |||
112 | /* Define this if you have a Motorola SCF5250 */ | ||
113 | #define CONFIG_CPU S5L8700 | ||
114 | |||
115 | /* Define this if you want to use coldfire's i2c interface */ | ||
116 | #define CONFIG_I2C I2C_S5L8700 | ||
117 | |||
118 | /* define this if the hardware can be powered off while charging */ | ||
119 | #define HAVE_POWEROFF_WHILE_CHARGING | ||
120 | |||
121 | /* The size of the flash ROM */ | ||
122 | #define FLASH_SIZE 0x400000 | ||
123 | |||
124 | /* Define this to the CPU frequency */ | ||
125 | #define CPU_FREQ 11289600 | ||
126 | |||
127 | /* Define this if you have ATA power-off control */ | ||
128 | //#define HAVE_ATA_POWER_OFF | ||
129 | |||
130 | /* Virtual LED (icon) */ | ||
131 | #define CONFIG_LED LED_VIRTUAL | ||
132 | |||
133 | /* Offset ( in the firmware file's header ) to the file CRC */ | ||
134 | #define FIRMWARE_OFFSET_FILE_CRC 0 | ||
135 | |||
136 | /* Offset ( in the firmware file's header ) to the real data */ | ||
137 | #define FIRMWARE_OFFSET_FILE_DATA 8 | ||
138 | |||
139 | /* USB On-the-go */ | ||
140 | //#define CONFIG_USBOTG USBOTG_M5636 | ||
141 | |||
142 | /* Define this if you have adjustable CPU frequency */ | ||
143 | #define HAVE_ADJUSTABLE_CPU_FREQ | ||
144 | |||
145 | #define BOOTFILE_EXT "meizu" | ||
146 | #define BOOTFILE "rockbox." BOOTFILE_EXT | ||
147 | #define BOOTDIR "/.rockbox" | ||
148 | |||
149 | #define BOOTLOADER_ENTRYPOINT 0x001F0000 | ||
150 | #define FLASH_ENTRYPOINT 0x00001000 | ||
151 | #define FLASH_MAGIC 0xfbfbfbf1 | ||
152 | |||
153 | #endif /* SIMULATOR */ | ||
154 | |||
155 | /* Define this for FM radio input available */ | ||
156 | #define HAVE_FMRADIO_IN | ||
157 | |||
158 | /** Port-specific settings **/ | ||
159 | |||
160 | /* Main LCD contrast range and defaults */ | ||
161 | #define MIN_CONTRAST_SETTING 1 | ||
162 | #define MAX_CONTRAST_SETTING 30 | ||
163 | #define DEFAULT_CONTRAST_SETTING 19 /* Match boot contrast */ | ||
164 | |||
165 | /* Main LCD backlight brightness range and defaults */ | ||
166 | /* PCF50506 can output 0%-100% duty cycle but D305A expects %15-100%. */ | ||
167 | #define MIN_BRIGHTNESS_SETTING 1 /* 15/16 (93.75%) */ | ||
168 | #define MAX_BRIGHTNESS_SETTING 13 /* 3/16 (18.75%) */ | ||
169 | #define DEFAULT_BRIGHTNESS_SETTING 8 /* 8/16 (50.00%) = x5 boot default */ | ||
170 | |||
diff --git a/firmware/export/config.h b/firmware/export/config.h index 1a288dd590..4746506c99 100644 --- a/firmware/export/config.h +++ b/firmware/export/config.h | |||
@@ -31,6 +31,8 @@ | |||
31 | #define TEA5767 0x02 /* Philips */ | 31 | #define TEA5767 0x02 /* Philips */ |
32 | #define LV24020LP 0x04 /* Sanyo */ | 32 | #define LV24020LP 0x04 /* Sanyo */ |
33 | #define SI4700 0x08 /* Silicon Labs */ | 33 | #define SI4700 0x08 /* Silicon Labs */ |
34 | #define TEA5760 0x10 /* Philips */ | ||
35 | #define LV240000 0x20 /* Sanyo */ | ||
34 | 36 | ||
35 | /* CONFIG_CODEC */ | 37 | /* CONFIG_CODEC */ |
36 | #define MAS3587F 3587 | 38 | #define MAS3587F 3587 |
@@ -54,6 +56,7 @@ | |||
54 | #define TCC771L 771 | 56 | #define TCC771L 771 |
55 | #define TCC773L 773 | 57 | #define TCC773L 773 |
56 | #define TCC7801 7801 | 58 | #define TCC7801 7801 |
59 | #define S5L8700 8700 | ||
57 | 60 | ||
58 | /* CONFIG_KEYPAD */ | 61 | /* CONFIG_KEYPAD */ |
59 | #define PLAYER_PAD 1 | 62 | #define PLAYER_PAD 1 |
@@ -79,6 +82,7 @@ | |||
79 | #define IAUDIO67_PAD 21 | 82 | #define IAUDIO67_PAD 21 |
80 | #define COWOND2_PAD 22 | 83 | #define COWOND2_PAD 22 |
81 | #define IAUDIO_M3_PAD 23 | 84 | #define IAUDIO_M3_PAD 23 |
85 | #define MEIZU_M6SL_PAD 24 | ||
82 | 86 | ||
83 | /* CONFIG_REMOTE_KEYPAD */ | 87 | /* CONFIG_REMOTE_KEYPAD */ |
84 | #define H100_REMOTE 1 | 88 | #define H100_REMOTE 1 |
@@ -117,6 +121,7 @@ | |||
117 | #define LCD_CREATIVEZVM 22 /* as used by Creative Zen Vision:M */ | 121 | #define LCD_CREATIVEZVM 22 /* as used by Creative Zen Vision:M */ |
118 | #define LCD_TL0350A 23 /* as used by the iAudio M3 remote, treated as main LCD */ | 122 | #define LCD_TL0350A 23 /* as used by the iAudio M3 remote, treated as main LCD */ |
119 | #define LCD_COWOND2 24 /* as used by Cowon D2 - LTV250QV, TCC7801 driver */ | 123 | #define LCD_COWOND2 24 /* as used by Cowon D2 - LTV250QV, TCC7801 driver */ |
124 | #define LCD_S6D0129 25 /* as used by the Meizu M6SP and M6SL - S6D0129 */ | ||
120 | 125 | ||
121 | /* LCD_PIXELFORMAT */ | 126 | /* LCD_PIXELFORMAT */ |
122 | #define HORIZONTAL_PACKING 1 | 127 | #define HORIZONTAL_PACKING 1 |
@@ -143,6 +148,7 @@ | |||
143 | #define I2C_IMX31L 9 | 148 | #define I2C_IMX31L 9 |
144 | #define I2C_TCC77X 10 | 149 | #define I2C_TCC77X 10 |
145 | #define I2C_TCC780X 11 | 150 | #define I2C_TCC780X 11 |
151 | #define I2C_S5L8700 12 | ||
146 | 152 | ||
147 | /* CONFIG_LED */ | 153 | /* CONFIG_LED */ |
148 | #define LED_REAL 1 /* SW controlled LED (Archos recorders, player) */ | 154 | #define LED_REAL 1 /* SW controlled LED (Archos recorders, player) */ |
@@ -165,6 +171,8 @@ | |||
165 | #define RTC_TCC77X 10 | 171 | #define RTC_TCC77X 10 |
166 | #define RTC_TCC780X 11 | 172 | #define RTC_TCC780X 11 |
167 | #define RTC_MR100 12 | 173 | #define RTC_MR100 12 |
174 | #define RTC_S5L8700 13 | ||
175 | #define RTC_S35390A 14 | ||
168 | 176 | ||
169 | /* USB On-the-go */ | 177 | /* USB On-the-go */ |
170 | #define USBOTG_ISP1362 1362 /* iriver H300 */ | 178 | #define USBOTG_ISP1362 1362 /* iriver H300 */ |
@@ -246,6 +254,8 @@ | |||
246 | #include "config-cowond2.h" | 254 | #include "config-cowond2.h" |
247 | #elif defined(CREATIVE_ZVM) | 255 | #elif defined(CREATIVE_ZVM) |
248 | #include "config-creativezvm.h" | 256 | #include "config-creativezvm.h" |
257 | #elif defined(MEIZU_M6SL) | ||
258 | #include "config-meizu-m6sl.h" | ||
249 | #else | 259 | #else |
250 | /* no known platform */ | 260 | /* no known platform */ |
251 | #endif | 261 | #endif |
@@ -382,7 +392,7 @@ | |||
382 | #endif | 392 | #endif |
383 | 393 | ||
384 | #if defined(CPU_PP) || (CONFIG_CPU == PNX0101) || (CONFIG_CPU == S3C2440) \ | 394 | #if defined(CPU_PP) || (CONFIG_CPU == PNX0101) || (CONFIG_CPU == S3C2440) \ |
385 | || (CONFIG_CPU == DSC25) || (CONFIG_CPU == DM320) | 395 | || (CONFIG_CPU == DSC25) || (CONFIG_CPU == DM320) || (CONFIG_CPU == S5L8700) |
386 | #define CPU_ARM | 396 | #define CPU_ARM |
387 | #define ARM_ARCH 4 /* ARMv4 */ | 397 | #define ARM_ARCH 4 /* ARMv4 */ |
388 | #endif | 398 | #endif |
@@ -411,7 +421,8 @@ | |||
411 | defined(CPU_PP) || /* PortalPlayer: core, plugins, codecs */ \ | 421 | defined(CPU_PP) || /* PortalPlayer: core, plugins, codecs */ \ |
412 | defined(CPU_TCC77X) || /* Telechips: core, plugins, codecs */ \ | 422 | defined(CPU_TCC77X) || /* Telechips: core, plugins, codecs */ \ |
413 | defined(CPU_TCC780X) || /* Telechips: core, plugins, codecs */ \ | 423 | defined(CPU_TCC780X) || /* Telechips: core, plugins, codecs */ \ |
414 | (CONFIG_CPU == PNX0101)) | 424 | (CONFIG_CPU == PNX0101) || \ |
425 | (CONFIG_CPU == S5L8700)) | ||
415 | #define ICODE_ATTR __attribute__ ((section(".icode"))) | 426 | #define ICODE_ATTR __attribute__ ((section(".icode"))) |
416 | #define ICONST_ATTR __attribute__ ((section(".irodata"))) | 427 | #define ICONST_ATTR __attribute__ ((section(".irodata"))) |
417 | #define IDATA_ATTR __attribute__ ((section(".idata"))) | 428 | #define IDATA_ATTR __attribute__ ((section(".idata"))) |
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h new file mode 100644 index 0000000000..d0956c4f26 --- /dev/null +++ b/firmware/export/s5l8700.h | |||
@@ -0,0 +1,536 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id: S5L8700X.h 2008-03-24 A4 $ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Bart van Adrichem | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | |||
20 | /* Copied from imx31l.h */ | ||
21 | #define REG8_PTR_T volatile unsigned char * | ||
22 | #define REG16_PTR_T volatile unsigned short * | ||
23 | #define REG32_PTR_T volatile unsigned long * | ||
24 | |||
25 | /* Base Adresses chapter in datasheet | ||
26 | */ | ||
27 | #define ARM_BASE_ADDR 0x38000000 | ||
28 | #define MIU_BASE_ADDR 0x38200000 //07 | ||
29 | #define IODMA_BASE_ADDR 0x38400000 //08 | ||
30 | #define USB_H11_BASE_ADDR 0x38600000 //22 | ||
31 | #define USB_F20_BASE_ADDR 0x38800000 //21 | ||
32 | #define USB_H20_BASE_ADDR 0x38A00000 | ||
33 | #define ATA_BASE_ADDR 0x38E00000 //28 | ||
34 | #define ADM_BASE_ADDR 0x39000000 //04 | ||
35 | #define LCD_CTRL_BASE_ADDR 0x39200000 //27 | ||
36 | #define ICU_BASE_ADDR 0x39C00000 //06 | ||
37 | #define EEC_BASE_ADDR 0x39E00000 //16 | ||
38 | #define APB_BRIDGE_BASE_ADDR 0x3C000000 | ||
39 | #define LCD_IF_BASE_ADDR 0x3C100000 //26 | ||
40 | #define FMC_BASE_ADDR 0x3C200000 //12 | ||
41 | #define MMC_SD_BASE_ADDR 0x3C300000 //13 | ||
42 | #define USB_PHY_BASE_ADDR 0x3C400000 //23 | ||
43 | #define CLCK_GEN_BASE_ADDR 0x3C500000 //05 | ||
44 | #define MS_BASE_ADDR 0x3C600000 //14 | ||
45 | #define TIMER_BASE_ADDR 0x3C700000 //11 | ||
46 | #define WDT_BASE_ADDR 0x3C800000 //09 | ||
47 | #define IIC_BASE_ADDR 0x3C900000 //18 | ||
48 | #define IIS_BASE_ADDR 0x3CA00000 //17 | ||
49 | #define SPDIF_OUT_BASE_ADDR 0x3CB00000 //15 | ||
50 | #define UART0_BASE_ADDR 0x3CC00000 //25 | ||
51 | #define UART1_BASE_ADDR 0x3CC08000 //25 | ||
52 | #define SPI_BASE_ADDR 0x3CD00000 //19 | ||
53 | #define ADC_BASE_ADDR 0x3CE00000 //20 | ||
54 | #define GPIO_BASE_ADDR 0x3CF00000 //24 | ||
55 | #define CHIP_ID_BASE_ADDR 0x3D100000 //29 | ||
56 | #define RTC_BASE_ADDR 0x3D200000 //10 | ||
57 | |||
58 | |||
59 | /* 04. CALMADM2E */ | ||
60 | //Following registers are mapped on IO Area in data memory area of Calm. | ||
61 | //TODO: not sure if the following list is correct concerning the 'h' added to the adresses in the datasheet | ||
62 | //#DEFINE 7BIT OFFSET OR IS REG16_PTR_T CORRECT?? | ||
63 | #define CALM_BASE 0x3F0000 //7 BITS LONG | ||
64 | #define CALM_CONFIG0 (*(REG16_PTR_T)(ADM_BASE_+0x00)) | ||
65 | #define CALM_CONFIG1 (*(REG16_PTR_T)(ADM_BASE_+0x02)) | ||
66 | #define CALM_COMMUN (*(REG16_PTR_T)(ADM_BASE_+0x04)) | ||
67 | #define CALM_DDATA0 (*(REG16_PTR_T)(ADM_BASE_+0x06)) | ||
68 | #define CALM_DDATA1 (*(REG16_PTR_T)(ADM_BASE_+0x08)) | ||
69 | #define CALM_DDATA2 (*(REG16_PTR_T)(ADM_BASE_+0x0A)) | ||
70 | #define CALM_DDATA3 (*(REG16_PTR_T)(ADM_BASE_+0x0C)) | ||
71 | #define CALM_DDATA4 (*(REG16_PTR_T)(ADM_BASE_+0x0E)) | ||
72 | #define CALM_DDATA5 (*(REG16_PTR_T)(ADM_BASE_+0x10)) | ||
73 | #define CALM_DDATA6 (*(REG16_PTR_T)(ADM_BASE_+0x12)) | ||
74 | #define CALM_DDATA7 (*(REG16_PTR_T)(ADM_BASE_+0x14)) | ||
75 | #define CALM_UDATA0 (*(REG16_PTR_T)(ADM_BASE_+0x16)) | ||
76 | #define CALM_UDATA1 (*(REG16_PTR_T)(ADM_BASE_+0x18)) | ||
77 | #define CALM_UDATA2 (*(REG16_PTR_T)(ADM_BASE_+0x1A)) | ||
78 | #define CALM_UDATA3 (*(REG16_PTR_T)(ADM_BASE_+0x1C)) | ||
79 | #define CALM_UDATA4 (*(REG16_PTR_T)(ADM_BASE_+0x1E)) | ||
80 | #define CALM_UDATA5 (*(REG16_PTR_T)(ADM_BASE_+0x20)) | ||
81 | #define CALM_UDATA6 (*(REG16_PTR_T)(ADM_BASE_+0x22)) | ||
82 | #define CALM_UDATA7 (*(REG16_PTR_T)(ADM_BASE_+0x24)) | ||
83 | #define CALM_IBASE_H (*(REG16_PTR_T)(ADM_BASE_+0x26)) | ||
84 | #define CALM_IBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x28)) | ||
85 | #define CALM_DBASE_H (*(REG16_PTR_T)(ADM_BASE_+0x2A)) | ||
86 | #define CALM_DBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x2C)) | ||
87 | #define CALM_XBASE_H (*(REG16_PTR_T)(ADM_BASE_+0x2E)) | ||
88 | #define CALM_XBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x30)) | ||
89 | #define CALM_YBASE_H (*(REG16_PTR_T)(ADM_BASE_+0x32)) | ||
90 | #define CALM_YBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x34)) | ||
91 | #define CALM_S0BASE_H (*(REG16_PTR_T)(ADM_BASE_+0x36)) | ||
92 | #define CALM_SOBASE_L (*(REG16_PTR_T)(ADM_BASE_+0x38)) | ||
93 | #define CALM_S1BASE_H (*(REG16_PTR_T)(ADM_BASE_+0x3A)) | ||
94 | #define CALM_S1BASE_L (*(REG16_PTR_T)(ADM_BASE_+0x3C)) | ||
95 | #define CALM_CACHECON (*(REG16_PTR_T)(ADM_BASE_+0x3E)) | ||
96 | #define CALM_CACHESTAT (*(REG16_PTR_T)(ADM_BASE_+0x40)) | ||
97 | #define CALM_SBFCON (*(REG16_PTR_T)(ADM_BASE_+0x42)) | ||
98 | #define CALM_SBFSTAT (*(REG16_PTR_T)(ADM_BASE_+0x44)) | ||
99 | #define CALM_SBL0OFF_H (*(REG16_PTR_T)(ADM_BASE_+0x46)) | ||
100 | #define CALM_SBL0OFF_L (*(REG16_PTR_T)(ADM_BASE_+0x48)) | ||
101 | #define CALM_SBL1OFF_H (*(REG16_PTR_T)(ADM_BASE_+0x4A)) | ||
102 | #define CALM_SBL1OFF_H (*(REG16_PTR_T)(ADM_BASE_+0x4C)) | ||
103 | #define CALM_SBL0BEGIN_H (*(REG16_PTR_T)(ADM_BASE_+0x4E)) | ||
104 | #define CALM_SBL0BEGIN_L (*(REG16_PTR_T)(ADM_BASE_+0x50)) | ||
105 | #define CALM_SBL1BEGIN_H (*(REG16_PTR_T)(ADM_BASE_+0x52)) | ||
106 | #define CALM_SBL1BEGIN_L (*(REG16_PTR_T)(ADM_BASE_+0x54)) | ||
107 | #define CALM_SBL0END_H (*(REG16_PTR_T)(ADM_BASE_+0x56)) | ||
108 | #define CALM_SBL0END_L (*(REG16_PTR_T)(ADM_BASE_+0x58)) | ||
109 | #define CALM_SBL0END_H (*(REG16_PTR_T)(ADM_BASE_+0x5A)) | ||
110 | #define CALM_SBL0END_L (*(REG16_PTR_T)(ADM_BASE_+0x5C)) | ||
111 | //Following registers are components of SFRS of the target system | ||
112 | #define ADM_CONFIG (*(REG32_PTR_T)(ADM_BASE_ADDR+0x00)) | ||
113 | #define ADM_COMMUN (*(REG32_PTR_T)(ADM_BASE_ADDR+0x04)) | ||
114 | #define ADM_DDATA0 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x10)) | ||
115 | #define ADM_DDATA1 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x14)) | ||
116 | #define ADM_DDATA2 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x18)) | ||
117 | #define ADM_DDATA3 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x2C)) | ||
118 | #define ADM_DDATA4 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x20)) | ||
119 | #define ADM_DDATA5 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x24)) | ||
120 | #define ADM_DDATA6 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x28)) | ||
121 | #define ADM_DDATA7 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x2C)) | ||
122 | #define ADM_UDATA0 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x30)) | ||
123 | #define ADM_UDATA1 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x34)) | ||
124 | #define ADM_UDATA2 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x38)) | ||
125 | #define ADM_UDATA3 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x3C)) | ||
126 | #define ADM_UDATA4 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x40)) | ||
127 | #define ADM_UDATA5 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x44)) | ||
128 | #define ADM_UDATA6 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x48)) | ||
129 | #define ADM_UDATA7 (*(REG32_PTR_T)(ADM_BASE_ADDR+0x4C)) | ||
130 | #define ADM_IBASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x50)) | ||
131 | #define ADM_DBASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x54)) | ||
132 | #define ADM_XBASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x58)) | ||
133 | #define ADM_YBASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x5C)) | ||
134 | #define ADM_S0BASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x60)) | ||
135 | #define ADM_S1BASE (*(REG32_PTR_T)(ADM_BASE_ADDR+0x64)) | ||
136 | |||
137 | /* 05. CLOCK & POWER MANAGEMENT */ | ||
138 | #define CLK_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x00)) | ||
139 | #define PLL_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x24)) | ||
140 | #define PLL0_PMS (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x04)) | ||
141 | #define PLL1_PMS (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x08)) | ||
142 | #define PLL0_CNT (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x14)) | ||
143 | #define PLL1_CNT (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x18)) | ||
144 | #define PLL_LOCK (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x20)) | ||
145 | #define PWR_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x28)) | ||
146 | #define PWR_MODE (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x2C)) | ||
147 | #define SWR_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x30)) | ||
148 | #define RST_SR (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x34)) | ||
149 | #define DSP_CLK_MD (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x38)) | ||
150 | #define CLK_CON (*(REG32_PTR_T)(CLCK_GEN_BASE_ADDR+0x3C)) | ||
151 | |||
152 | /* 06. INTERRUPT CONTROLLER UNIT */ | ||
153 | #define ICU_SRC_PND (*(REG32_PTR_T)(ICU_BASE_ADDR+0x00)) | ||
154 | #define ICU_INT_MOD (*(REG32_PTR_T)(ICU_BASE_ADDR+0x04)) | ||
155 | #define ICU_INT_MSK (*(REG32_PTR_T)(ICU_BASE_ADDR+0x08)) | ||
156 | #define ICU_PRIORITY (*(REG32_PTR_T)(ICU_BASE_ADDR+0x0C)) | ||
157 | #define ICU_INT_PND (*(REG32_PTR_T)(ICU_BASE_ADDR+0x10)) | ||
158 | #define ICU_INT_OFFSET (*(REG32_PTR_T)(ICU_BASE_ADDR+0x14)) | ||
159 | #define ICU_EINT_POL (*(REG32_PTR_T)(ICU_BASE_ADDR+0x18)) | ||
160 | #define ICU_EINT_PEND (*(REG32_PTR_T)(ICU_BASE_ADDR+0x1C)) | ||
161 | #define ICU_EINT_MSK (*(REG32_PTR_T)(ICU_BASE_ADDR+0x20)) | ||
162 | |||
163 | /* 07. MEMORY INTERFACE UNIT (MIU) */ | ||
164 | #define MIU_CON (*(REG32_PTR_T)(MIU_BASE_ADDR+0x00)) | ||
165 | #define MIU_COM (*(REG32_PTR_T)(MIU_BASE_ADDR+0x04)) | ||
166 | #define MIU_AREF (*(REG32_PTR_T)(MIU_BASE_ADDR+0x08)) | ||
167 | #define MIU_MRS (*(REG32_PTR_T)(MIU_BASE_ADDR+0x0C)) | ||
168 | #define MIU_SDPARA (*(REG32_PTR_T)(MIU_BASE_ADDR+0x10)) | ||
169 | |||
170 | #define MIU_MEM_CONF (*(REG32_PTR_T)(MIU_BASE_ADDR+0x020H)) // 9 BIT ADRESS IN DATASHEET???????? | ||
171 | #define MIU_USR_CMD (*(REG32_PTR_T)(MIU_BASE_ADDR+0x024H)) | ||
172 | #define MIU_AREF (*(REG32_PTR_T)(MIU_BASE_ADDR+0x028H)) | ||
173 | #define MIU_MRS (*(REG32_PTR_T)(MIU_BASE_ADDR+0x02CH)) | ||
174 | #define MIU_DPARAM (*(REG32_PTR_T)(MIU_BASE_ADDR+0x030H)) | ||
175 | #define MIU_SMEM_CONF (*(REG32_PTR_T)(MIU_BASE_ADDR+0x034H)) | ||
176 | #define MIU_S01PARA (*(REG32_PTR_T)(MIU_BASE_ADDR+0x038H)) | ||
177 | #define MIU_S23PARA (*(REG32_PTR_T)(MIU_BASE_ADDR+0x03CH)) | ||
178 | /* TODO: | ||
179 | #define MIU_ORG | ||
180 | #define MIU_DLYDQS | ||
181 | #define MIU_DLYCLK | ||
182 | #define MIU_DSS_SEL_B | ||
183 | #define MIU_DSS_SEL_O | ||
184 | #define MIU_PAD_DSS_SEL_NOR | ||
185 | #define MIU_PAD_DSS_SEL_ATA | ||
186 | #define MIU_SSTL2_PAD_ON | ||
187 | */ | ||
188 | |||
189 | /* 08. IODMA CONTROLLER */ | ||
190 | #define DMA_BASE0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x00)) | ||
191 | #define DMA_BASE1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x20)) | ||
192 | #define DMA_BASE2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x40)) | ||
193 | #define DMA_BASE3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x60)) | ||
194 | #define DMA_CNT0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x08)) | ||
195 | #define DMA_CNT1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x28)) | ||
196 | #define DMA_CNT2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x48)) | ||
197 | #define DMA_CNT3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x68)) | ||
198 | #define DMA_CADDR0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x0C)) | ||
199 | #define DMA_CADDR1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x2C)) | ||
200 | #define DMA_CADDR2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x4C)) | ||
201 | #define DMA_CADDR3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x6C)) | ||
202 | #define DMA_CON0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x04)) | ||
203 | #define DMA_CON1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x24)) | ||
204 | #define DMA_CON2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x44)) | ||
205 | #define DMA_CON3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x64)) | ||
206 | #define DMA_CTCNT0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x10)) | ||
207 | #define DMA_CTCNT1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x30)) | ||
208 | #define DMA_CTCNT2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x50)) | ||
209 | #define DMA_CTCNT3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x70)) | ||
210 | #define DMA_COM0 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x14)) | ||
211 | #define DMA_COM1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x34)) | ||
212 | #define DMA_COM2 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x54)) | ||
213 | #define DMA_COM3 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x74)) | ||
214 | #define DMA_OFF1 (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x18)) | ||
215 | #define DMA_ALLST (*(REG32_PTR_T)(IODMA_BASE_ADDR+0x0100)) | ||
216 | |||
217 | /* 10. REAL TIMER CLOCK (RTC) */ | ||
218 | #define RTC_CON (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00)) | ||
219 | #define RTC_RST (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04)) | ||
220 | #define RTC_ALM_CON (*(REG32_PTR_T)(RTC_BASE_ADDR+0x08)) | ||
221 | #define RTC_ALM_SEC (*(REG32_PTR_T)(RTC_BASE_ADDR+0x0C)) | ||
222 | #define RTC_ALM_MIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x10)) | ||
223 | #define RTC_ALM_HOUR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x14)) | ||
224 | #define RTC_ALM_DATE (*(REG32_PTR_T)(RTC_BASE_ADDR+0x18)) | ||
225 | #define RTC_ALM_DAY (*(REG32_PTR_T)(RTC_BASE_ADDR+0x1C)) | ||
226 | #define RTC_ALM_MON (*(REG32_PTR_T)(RTC_BASE_ADDR+0x20)) | ||
227 | #define RTC_AML_YEAR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x24)) | ||
228 | #define RTC_SEC (*(REG32_PTR_T)(RTC_BASE_ADDR+0x28)) | ||
229 | #define RTC_MIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x2C)) | ||
230 | #define RTC_HOUR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x30)) | ||
231 | #define RTC_DATE (*(REG32_PTR_T)(RTC_BASE_ADDR+0x34)) | ||
232 | #define RTC_DAY (*(REG32_PTR_T)(RTC_BASE_ADDR+0x38)) | ||
233 | #define RTC_MON (*(REG32_PTR_T)(RTC_BASE_ADDR+0x3C)) | ||
234 | #define RTC_YEAR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x40)) | ||
235 | #define RTC_IM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x44)) | ||
236 | #define RTC_PEND (*(REG32_PTR_T)(RTC_BASE_ADDR+0x48)) | ||
237 | |||
238 | /* 09. WATCHDOG TIMER*/ | ||
239 | #define WDT_CON (*(REG32_PTR_T)(WDT_BASE_ADDR+0x00)) | ||
240 | #define WDT_CNT (*(REG32_PTR_T)(WDT_BASE_ADDR+0x04)) | ||
241 | |||
242 | /* 11. 16 BIT TIMER */ | ||
243 | #define TA_CON (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x00)) | ||
244 | #define TA_CMD (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x04)) | ||
245 | #define TA_DATA0 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x08)) | ||
246 | #define TA_DATA1 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x0C)) | ||
247 | #define TA_PRE (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x10)) | ||
248 | #define TA_CNT (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x14)) | ||
249 | #define TB_CON (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x20)) | ||
250 | #define TB_CMD (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x24)) | ||
251 | #define TB_DATA0 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x28)) | ||
252 | #define TB_DATA1 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x2C)) | ||
253 | #define TB_PRE (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x30)) | ||
254 | #define TB_CNT (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x34)) | ||
255 | #define TC_CON (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x40)) | ||
256 | #define TC_CMD (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x44)) | ||
257 | #define TC_DATA0 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x48)) | ||
258 | #define TC_DATA1 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x4C)) | ||
259 | #define TC_PRE (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x50)) | ||
260 | #define TC_CNT (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x54)) | ||
261 | #define TD_CON (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x60)) | ||
262 | #define TD_CMD (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x64)) | ||
263 | #define TD_DATA0 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x68)) | ||
264 | #define TD_DATA1 (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x6C)) | ||
265 | #define TD_PRE (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x70)) | ||
266 | #define TD_CNT (*(REG32_PTR_T)(TIMER_BASE_ADDR+0x74)) | ||
267 | |||
268 | /* 12. NAND FLASH CONTROLER */ | ||
269 | // TODO: FIFO | ||
270 | #define FM_CTRL0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0000)) | ||
271 | #define FM_CTRL1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0004)) | ||
272 | #define FM_CMD (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0008)) | ||
273 | #define FM_ADR0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x000C)) | ||
274 | #define FM_ADR1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0010)) | ||
275 | #define FM_ADR2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0014)) | ||
276 | #define FM_ADR3 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0018)) | ||
277 | #define FM_ADR4 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x001C)) | ||
278 | #define FM_ADR5 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0020)) | ||
279 | #define FM_ADR6 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0024)) | ||
280 | #define FM_ADR7 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0028)) | ||
281 | #define FM_ANUM (*(REG32_PTR_T)(FMC_BASE_ADDR+0x002C)) | ||
282 | #define FM_DNUM (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0030)) | ||
283 | #define FM_DATAW0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0034)) | ||
284 | #define FM_DATAW1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0038)) | ||
285 | #define FM_DATAW2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x003C)) | ||
286 | #define FM_DATAW3 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0040)) | ||
287 | #define FM_CSTAT (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0048)) | ||
288 | #define FM_SYND0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x004C)) | ||
289 | #define FM_SYND1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0050)) | ||
290 | #define FM_SYND2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0054)) | ||
291 | #define FM_SYND3 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0058)) | ||
292 | #define FM_SYND4 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x005C)) | ||
293 | #define FM_SYND5 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0060)) | ||
294 | #define FM_SYND6 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0064)) | ||
295 | #define FM_SYND7 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0068)) | ||
296 | #define FM_FIFO (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0080)) // UNTILL (INCLUDING) 0x00FC <-- | ||
297 | #define RS_CTRL (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0100)) | ||
298 | #define RS_PAITY0-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0110)) | ||
299 | #define RS_PAITY0-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0114)) | ||
300 | #define RS_PAITY0-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0118)) | ||
301 | #define RS_PAITY1-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0120)) | ||
302 | #define RS_PAITY1-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0124)) | ||
303 | #define RS_PAITY1-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0128)) | ||
304 | #define RS_PAITY2-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0130)) | ||
305 | #define RS_PAITY2-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0134)) | ||
306 | #define RS_PAITY2-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0138)) | ||
307 | #define RS_PAITY3-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0140)) | ||
308 | #define RS_PAITY3-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0144)) | ||
309 | #define RS_PAITY3-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0148)) | ||
310 | #define RS_SYND0-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0150)) | ||
311 | #define RS_SYND0-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0154)) | ||
312 | #define RS_SYND0-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0158)) | ||
313 | #define RS_SYND1-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0160)) | ||
314 | #define RS_SYND1-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0164)) | ||
315 | #define RS_SYND1-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0168)) | ||
316 | #define RS_SYND2-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0170)) | ||
317 | #define RS_SYND2-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0174)) | ||
318 | #define RS_SYND2-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0178)) | ||
319 | #define RS_SYND3-0 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0180)) | ||
320 | #define RS_SYND3-1 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0184)) | ||
321 | #define RS_SYND3-2 (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0188)) | ||
322 | #define FLAG_SYND (*(REG32_PTR_T)(FMC_BASE_ADDR+0x0190)) | ||
323 | |||
324 | /* 13. SECURE DIGITAL CARD INTERFACE (SDCI) */ | ||
325 | // TODO | ||
326 | |||
327 | /* 14. MEMORY STICK HOST CONTROLLER */ | ||
328 | //TODO | ||
329 | |||
330 | /* 15. SPDIF TRANSMITTER (SPDIFOUT) */ | ||
331 | #define SPD_CLKCON (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x00)) | ||
332 | #define SPD_CON (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x04)) | ||
333 | #define SPD_BSTAS (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x08)) | ||
334 | #define SPD_CSTAS (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x0C)) | ||
335 | #define SPD_DAT (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x10)) | ||
336 | #define SPD_CNT (*(REG32_PTR_T)(SPDIF_OUT_BASE_ADDR+0x14)) | ||
337 | |||
338 | /* 16. REED-SOLOMON ECC CODEC */ | ||
339 | //TODO | ||
340 | |||
341 | /* 17. IIS Tx/Rx INTERFACE */ | ||
342 | #define I2S_CLK_CON (*(REG32_PTR_T)(IIS_BASE_ADDR+0x00)) | ||
343 | #define I2S_TX_CON (*(REG32_PTR_T)(IIS_BASE_ADDR+0x04)) | ||
344 | #define I2S_TX_COM (*(REG32_PTR_T)(IIS_BASE_ADDR+0x08)) | ||
345 | #define I2S_TX_DB (*(REG32_PTR_T)(IIS_BASE_ADDR+0x10)) | ||
346 | #define I2S_RX_CON (*(REG32_PTR_T)(IIS_BASE_ADDR+0x30)) | ||
347 | #define I2S_RX_COM (*(REG32_PTR_T)(IIS_BASE_ADDR+0x34)) | ||
348 | #define I2S_RX_DB (*(REG32_PTR_T)(IIS_BASE_ADDR+0x38)) | ||
349 | #define I2S_STATUS (*(REG32_PTR_T)(IIS_BASE_ADDR+0x3C)) | ||
350 | |||
351 | /* 18. IIC BUS INTERFACE */ | ||
352 | #define IIC_CON (*(REG32_PTR_T)(IIC_BASE_ADDR+0x00)) | ||
353 | #define IIC_STST (*(REG32_PTR_T)(IIC_BASE_ADDR+0x04)) | ||
354 | #define IIC_ADD (*(REG32_PTR_T)(IIC_BASE_ADDR+0x08)) | ||
355 | #define IIC_DS (*(REG32_PTR_T)(IIC_BASE_ADDR+0x0C)) | ||
356 | |||
357 | /* 19. SPI (SERIAL PERHIPERAL INTERFACE) */ | ||
358 | #define SP_CLK_CON (*(REG32_PTR_T)(SPI_BASE_ADDR+0x00)) | ||
359 | #define SP_CON (*(REG32_PTR_T)(SPI_BASE_ADDR+0x04)) | ||
360 | #define SP_STA (*(REG32_PTR_T)(SPI_BASE_ADDR+0x08)) | ||
361 | #define SP_PIN (*(REG32_PTR_T)(SPI_BASE_ADDR+0x0C)) | ||
362 | #define SP_TDAT (*(REG32_PTR_T)(SPI_BASE_ADDR+0x10)) | ||
363 | #define SP_RDAT (*(REG32_PTR_T)(SPI_BASE_ADDR+0x14)) | ||
364 | #define SP_PRE (*(REG32_PTR_T)(SPI_BASE_ADDR+0x18)) | ||
365 | |||
366 | /* 20. ADC CONTROLLER */ | ||
367 | #define ADC_CON (*(REG32_PTR_T)(ADC_BASE_ADDR+0x00)) | ||
368 | #define ADC_TSC (*(REG32_PTR_T)(ADC_BASE_ADDR+0x04)) | ||
369 | #define ADC_DLY (*(REG32_PTR_T)(ADC_BASE_ADDR+0x08)) | ||
370 | #define ADC_DAT0 (*(REG32_PTR_T)(ADC_BASE_ADDR+0x0C)) | ||
371 | #define ADC_DAT1 (*(REG32_PTR_T)(ADC_BASE_ADDR+0x10)) | ||
372 | #define ADC_UPDN (*(REG32_PTR_T)(ADC_BASE_ADDR+0x14)) | ||
373 | |||
374 | /* 21. USB 2.0 FUNCTION CONTROLER SPECIAL REGISTER */ | ||
375 | #define USB2_IN (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x00)) | ||
376 | #define USB2_EIR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x04)) | ||
377 | #define USB2_EIER (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x08)) | ||
378 | #define USB2_FAR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x0C)) | ||
379 | #define USB2_FNR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x10)) | ||
380 | #define USB2_EDR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x14)) | ||
381 | #define USB2_TR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x18)) | ||
382 | #define USB2_SSR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x1C)) | ||
383 | #define USB2_SCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x20)) | ||
384 | #define USB2_EP0SR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x24)) | ||
385 | #define USB2_EP0CR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x28)) | ||
386 | #define USB2_EP0BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x60)) | ||
387 | #define USB2_EP1BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x64)) | ||
388 | #define USB2_EP2BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x68)) | ||
389 | #define USB2_EP3BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x6C)) | ||
390 | #define USB2_EP4BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x70)) | ||
391 | #define USB2_EP5BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x74)) | ||
392 | #define USB2_EP6BR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x78)) | ||
393 | #define USB2_ESR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x2C)) | ||
394 | #define USB2_ECR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x30)) | ||
395 | #define USB2_BRCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x34)) | ||
396 | #define USB2_BSCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x38)) | ||
397 | #define USB2_MPR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x3C)) | ||
398 | #define USB2_MCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x40)) | ||
399 | #define USB2_MTCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x44)) | ||
400 | #define USB2_MFCR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x48)) | ||
401 | #define USB2_MTTCR1 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x4C)) | ||
402 | #define USB2_MTTCR2 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x50)) | ||
403 | #define USB2_MICR (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x84)) | ||
404 | #define USB2_MBAR1 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x88)) | ||
405 | #define USB2_MBAR2 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x8C)) | ||
406 | #define USB2_MCAR1 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x94)) | ||
407 | #define USB2_MCAR2 (*(REG32_PTR_T)(USB_F20_BASE_ADDR+0x98)) | ||
408 | |||
409 | /* 22. USB 1.1 HOST CONTROLER SPECIAL REGISTER */ | ||
410 | #define HC_REV (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x00)) | ||
411 | #define HC_CON (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x04)) | ||
412 | #define HC_COMSTAT (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x08)) | ||
413 | #define HC_INTSTAT (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x0C)) | ||
414 | #define HC_INTEN (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x10)) | ||
415 | #define HC_INTDIS (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x14)) | ||
416 | #define HC_HCCA (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x18)) | ||
417 | #define HC_PCED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x1C)) | ||
418 | #define HC_CHED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x20)) | ||
419 | #define HC_CCED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x24)) | ||
420 | #define HC_BHED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x28)) | ||
421 | #define HC_BCED (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x2C)) | ||
422 | #define HC_DH (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x30)) | ||
423 | #define HC_FMI (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x34)) | ||
424 | #define HC_FMR (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x38)) | ||
425 | #define HC_FMNR (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x3C)) | ||
426 | #define HC_PS (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x40)) | ||
427 | #define HC_LSTRESH (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x44)) | ||
428 | #define HC_RHSECA (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x48)) | ||
429 | #define HC_RHDESB (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x4C)) | ||
430 | #define HC_STAT (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x50)) | ||
431 | #define HC_PSTAT (*(REG32_PTR_T)(USB_H11_BASE_ADDR+0x54)) | ||
432 | |||
433 | /* 23. USB 2.0 PHY CONTROL */ | ||
434 | #define PHY_CTRL (*(REG32_PTR_T)(USB_PHY_BASE_ADDR+0x00)) | ||
435 | #define ULCK_CON (*(REG32_PTR_T)(USB_PHY_BASE_ADDR+0x04)) | ||
436 | #define URST_CON (*(REG32_PTR_T)(USB_PHY_BASE_ADDR+0x08)) | ||
437 | |||
438 | /* 24. GPIO PORT CONTROLL */ | ||
439 | #define GPIO_PCON0 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x00)) | ||
440 | #define GPIO_PDAT0 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x04)) | ||
441 | #define GPIO_PCON1 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x10)) | ||
442 | #define GPIO_PDAT1 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x14)) | ||
443 | #define GPIO_PCON2 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x20)) | ||
444 | #define GPIO_PDAT2 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x24)) | ||
445 | #define GPIO_PCON3 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x30)) | ||
446 | #define GPIO_PDAT3 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x34)) | ||
447 | #define GPIO_PCON4 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x40)) | ||
448 | #define GPIO_PDAT4 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x44)) | ||
449 | #define GPIO_PCON5 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x50)) | ||
450 | #define GPIO_PDAT5 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x54)) | ||
451 | #define GPIO_PCON6 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x60)) | ||
452 | #define GPIO_PDAT6 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x64)) | ||
453 | #define GPIO_PCON7 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x70)) | ||
454 | #define GPIO_PDAT7 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0x74)) | ||
455 | #define GPIO_PCON10 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xA0)) | ||
456 | #define GPIO_PDAT10 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xA4)) | ||
457 | #define GPIO_PCON11 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xF8)) | ||
458 | #define GPIO_PDAT11 (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xFC)) | ||
459 | #define GPIO_PCON_ASRAM (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xF0)) | ||
460 | #define GPIO_PCON_SDRAM (*(REG32_PTR_T)(GPIO_BASE_ADDR+0xF4)) | ||
461 | |||
462 | /* 25. UART */ | ||
463 | #define UART0_LCON (*(REG32_PTR_T)(UART0_BASE_ADDR+0x00)) | ||
464 | #define UART0_CON (*(REG32_PTR_T)(UART0_BASE_ADDR+0x04)) | ||
465 | #define UART0_FCON (*(REG32_PTR_T)(UART0_BASE_ADDR+0x08)) | ||
466 | #define UART0_MCON (*(REG32_PTR_T)(UART0_BASE_ADDR+0x0C)) | ||
467 | #define UART0_TRSTAT (*(REG32_PTR_T)(UART0_BASE_ADDR+0x10)) | ||
468 | #define UART0_ERSTAT (*(REG32_PTR_T)(UART0_BASE_ADDR+0x14)) | ||
469 | #define UART0_FSTAT (*(REG32_PTR_T)(UART0_BASE_ADDR+0x18)) | ||
470 | #define UART0_MSTAT (*(REG32_PTR_T)(UART0_BASE_ADDR+0x1C)) | ||
471 | #define UART0_TXH (*(REG32_PTR_T)(UART0_BASE_ADDR+0x10)) | ||
472 | #define UART0_RXH (*(REG32_PTR_T)(UART0_BASE_ADDR+0x24)) | ||
473 | #define UART0_BRDIV (*(REG32_PTR_T)(UART0_BASE_ADDR+0x28)) | ||
474 | |||
475 | #define UART1_LCON (*(REG32_PTR_T)(UART1_BASE_ADDR+0x00)) | ||
476 | #define UART1_CON (*(REG32_PTR_T)(UART1_BASE_ADDR+0x04)) | ||
477 | #define UART1_FCON (*(REG32_PTR_T)(UART1_BASE_ADDR+0x08)) | ||
478 | #define UART1_MCON (*(REG32_PTR_T)(UART1_BASE_ADDR+0x0C)) | ||
479 | #define UART1_TRSTAT (*(REG32_PTR_T)(UART1_BASE_ADDR+0x10)) | ||
480 | #define UART1_ERSTAT (*(REG32_PTR_T)(UART1_BASE_ADDR+0x14)) | ||
481 | #define UART1_FSTAT (*(REG32_PTR_T)(UART1_BASE_ADDR+0x18)) | ||
482 | #define UART1_MSTAT (*(REG32_PTR_T)(UART1_BASE_ADDR+0x1C)) | ||
483 | #define UART1_TXH (*(REG32_PTR_T)(UART1_BASE_ADDR+0x10)) | ||
484 | #define UART1_RXH (*(REG32_PTR_T)(UART1_BASE_ADDR+0x24)) | ||
485 | #define UART1_BRDIV (*(REG32_PTR_T)(UART1_BASE_ADDR+0x28)) | ||
486 | |||
487 | /* 26. LCD INTERFACE CONTROLLER */ | ||
488 | // TODO: WDATA | ||
489 | #define LCD_CON (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x00)) | ||
490 | #define LCD_WCMD (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x04)) | ||
491 | #define LCD_RCMD (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x0C)) | ||
492 | #define LCD_RDATA (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x10)) | ||
493 | #define LCD_DBUFF (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x14)) | ||
494 | #define LCD_INTCON (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x18)) | ||
495 | #define LCD_STATUS (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x1C)) | ||
496 | #define LCD_PHTIME (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x20)) | ||
497 | #define LCD_RST_TIME (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x24)) | ||
498 | #define LCD_DRV_RST (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x28)) | ||
499 | #define LCD_WDATA (*(REG32_PTR_T)(LCD_IF_BASE_ADDR+0x40)) // UNTILL (INCLUDING) 0x5C <-- | ||
500 | |||
501 | /* 27. CLCD CONTROLLER */ | ||
502 | #define CLCD_CON1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x00)) | ||
503 | #define CLCD_CON2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x04)) | ||
504 | #define CLCD_TCON1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x08)) | ||
505 | #define CLCD_TCON2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x0C)) | ||
506 | #define CLCD_TCON3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x10)) | ||
507 | #define CLCD_OSD1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x14)) | ||
508 | #define CLCD_OSD2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x18)) | ||
509 | #define CLCD_OSD3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x1C)) | ||
510 | #define CLCD_B1SADDR1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x20)) | ||
511 | #define CLCD_B2SADDR1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x24)) | ||
512 | #define CLCD_F1SADDR1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x28)) | ||
513 | #define CLCD_F2SADDR1 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x2C)) | ||
514 | #define CLCD_B1SADDR2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x30)) | ||
515 | #define CLCD_B2SADDR2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x34)) | ||
516 | #define CLCD_F1SADDR2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x38)) | ||
517 | #define CLCD_F2SADDR2 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x3C)) | ||
518 | #define CLCD_B1SADDR3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x40)) | ||
519 | #define CLCD_B2SADDR3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x44)) | ||
520 | #define CLCD_F1SADDR3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x48)) | ||
521 | #define CLCD_F2SADDR3 (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x4C)) | ||
522 | #define CLCD_INTCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x50)) | ||
523 | #define CLCD_KEYCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x54)) | ||
524 | #define CLCD_KEYVAL (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x58)) | ||
525 | #define CLCD_BGCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x5C)) | ||
526 | #define CLCD_FGCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x60)) | ||
527 | #define CLCD_DITHCON (*(REG32_PTR_T)(LCD_CTRL_BASE_ADDR+0x64)) | ||
528 | |||
529 | /* 28. ATA CONTROLLER */ | ||
530 | // TODO | ||
531 | |||
532 | /* 29. CHIP ID */ | ||
533 | |||
534 | #define REG_ONE (*(REG32_PTR_T)(CHIP_ID_BASE_ADDR+0x00)) | ||
535 | #define REG_TWO (*(REG32_PTR_T)(CHIP_ID_BASE_ADDR+0x04)) | ||
536 | |||
diff --git a/firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h b/firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h new file mode 100644 index 0000000000..c0a069ac0c --- /dev/null +++ b/firmware/target/arm/s5l8700/meizu-m6sl/adc-target.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2006 by Barry Wardell | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | #ifndef _ADC_TARGET_H_ | ||
20 | #define _ADC_TARGET_H_ | ||
21 | |||
22 | /* only two channels used by the Gigabeat */ | ||
23 | #define NUM_ADC_CHANNELS 1 | ||
24 | |||
25 | #define ADC_UNKNOWN_1 0 | ||
26 | #define ADC_UNKNOWN_2 1 | ||
27 | #define ADC_BATTERY 2 | ||
28 | #define ADC_UNKNOWN_4 3 | ||
29 | |||
30 | #define ADC_UNREG_POWER ADC_BATTERY /* For compatibility */ | ||
31 | #define ADC_READ_ERROR 0xFFFF | ||
32 | |||
33 | #endif | ||
diff --git a/firmware/target/arm/s5l8700/meizu-m6sl/button-target.h b/firmware/target/arm/s5l8700/meizu-m6sl/button-target.h new file mode 100644 index 0000000000..7d0d7a1c4d --- /dev/null +++ b/firmware/target/arm/s5l8700/meizu-m6sl/button-target.h | |||
@@ -0,0 +1,52 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2006 by Linus Nielsen Feltzing | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | #ifndef _BUTTON_TARGET_H_ | ||
20 | #define _BUTTON_TARGET_H_ | ||
21 | |||
22 | #include <stdbool.h> | ||
23 | #include "config.h" | ||
24 | |||
25 | #define HAS_BUTTON_HOLD | ||
26 | |||
27 | bool button_hold(void); | ||
28 | void button_init_device(void); | ||
29 | int button_read_device(void); | ||
30 | |||
31 | /* Toshiba Gigabeat specific button codes */ | ||
32 | |||
33 | #define BUTTON_LEFT 0x00000001 | ||
34 | #define BUTTON_RIGHT 0x00000002 | ||
35 | #define BUTTON_UP 0x00000004 | ||
36 | #define BUTTON_DOWN 0x00000008 | ||
37 | |||
38 | #define BUTTON_SELECT 0x00000010 | ||
39 | |||
40 | #define BUTTON_MENU 0x00000020 | ||
41 | #define BUTTON_PLAY 0x00000040 | ||
42 | |||
43 | |||
44 | #define BUTTON_MAIN (BUTTON_MENU|BUTTON_LEFT|BUTTON_RIGHT\ | ||
45 | |BUTTON_UP|BUTTON_DOWN|BUTTON_SELECT|BUTTON_PLAY) | ||
46 | |||
47 | #define BUTTON_REMOTE 0 | ||
48 | |||
49 | #define POWEROFF_BUTTON BUTTON_PLAY | ||
50 | #define POWEROFF_COUNT 10 | ||
51 | |||
52 | #endif /* _BUTTON_TARGET_H_ */ | ||
diff --git a/tools/configure b/tools/configure index d81f0e2fe0..51707e970b 100755 --- a/tools/configure +++ b/tools/configure | |||
@@ -626,8 +626,9 @@ cat <<EOF | |||
626 | ==Tatung== ==Olympus== ==Logik== | 626 | ==Tatung== ==Olympus== ==Logik== |
627 | 60) Elio TPJ-1022 70) M:Robe 500 80) DAX 1GB MP3/DAB | 627 | 60) Elio TPJ-1022 70) M:Robe 500 80) DAX 1GB MP3/DAB |
628 | 71) M:Robe 100 | 628 | 71) M:Robe 100 |
629 | ==Creative== | 629 | |
630 | 90) Zen Vision:M | 630 | ==Creative== ==Meizu== |
631 | 90) Zen Vision:M 100) M6SL | ||
631 | EOF | 632 | EOF |
632 | 633 | ||
633 | buildfor=`input`; | 634 | buildfor=`input`; |
@@ -1521,6 +1522,27 @@ EOF | |||
1521 | t_model="tpj1022" | 1522 | t_model="tpj1022" |
1522 | ;; | 1523 | ;; |
1523 | 1524 | ||
1525 | 100|meizum6sl) | ||
1526 | target_id=20 | ||
1527 | modelname="meizum6sl" | ||
1528 | target="-DMEIZU_M6SL" | ||
1529 | memory=16 # always | ||
1530 | arm9tdmicc | ||
1531 | tool="cp" | ||
1532 | bmp2rb_mono="$rootdir/tools/bmp2rb -f 0" | ||
1533 | bmp2rb_native="$rootdir/tools/bmp2rb -f 4" | ||
1534 | output="rockbox.meizu" | ||
1535 | appextra="recorder:gui" | ||
1536 | plugins="no" #FIXME | ||
1537 | swcodec="yes" | ||
1538 | toolset=$genericbitmaptools | ||
1539 | boottool="cp" | ||
1540 | bootoutput="rockboot.ebn" | ||
1541 | # architecture, manufacturer and model for the target-tree build | ||
1542 | t_cpu="arm" | ||
1543 | t_manufacturer="s5l8700" | ||
1544 | t_model="meizu-m6sl" | ||
1545 | ;; | ||
1524 | *) | 1546 | *) |
1525 | echo "Please select a supported target platform!" | 1547 | echo "Please select a supported target platform!" |
1526 | exit | 1548 | exit |
diff --git a/tools/makesrc.inc b/tools/makesrc.inc index 846df8cb9e..be9c34e16b 100644 --- a/tools/makesrc.inc +++ b/tools/makesrc.inc | |||
@@ -11,4 +11,5 @@ | |||
11 | 11 | ||
12 | SRC := $(shell cat SOURCES | $(CC) -DMEMORYSIZE=$(MEMORYSIZE) $(INCLUDES) \ | 12 | SRC := $(shell cat SOURCES | $(CC) -DMEMORYSIZE=$(MEMORYSIZE) $(INCLUDES) \ |
13 | $(TARGET) $(DEFINES) $(EXTRA_DEFINES) -E -P -include "config.h" - 2>/dev/null \ | 13 | $(TARGET) $(DEFINES) $(EXTRA_DEFINES) -E -P -include "config.h" - 2>/dev/null \ |
14 | | grep -v "^\#") | 14 | | grep -v "^\#" | xargs ls) |
15 | #| grep -v "^\#") | ||
diff --git a/uisimulator/sdl/button.c b/uisimulator/sdl/button.c index 03f7dc1e96..78be6700ec 100644 --- a/uisimulator/sdl/button.c +++ b/uisimulator/sdl/button.c | |||
@@ -772,6 +772,37 @@ void button_event(int key, bool pressed) | |||
772 | case SDLK_KP9: | 772 | case SDLK_KP9: |
773 | new_btn = BUTTON_MENU; | 773 | new_btn = BUTTON_MENU; |
774 | break; | 774 | break; |
775 | |||
776 | #elif CONFIG_KEYPAD == MEIZU_M6SL_PAD | ||
777 | case SDLK_KP4: | ||
778 | case SDLK_LEFT: | ||
779 | new_btn = BUTTON_LEFT; | ||
780 | break; | ||
781 | case SDLK_KP6: | ||
782 | case SDLK_RIGHT: | ||
783 | new_btn = BUTTON_RIGHT; | ||
784 | break; | ||
785 | case SDLK_KP8: | ||
786 | case SDLK_UP: | ||
787 | new_btn = BUTTON_UP; | ||
788 | break; | ||
789 | case SDLK_KP2: | ||
790 | case SDLK_DOWN: | ||
791 | new_btn = BUTTON_DOWN; | ||
792 | break; | ||
793 | case SDLK_KP_ENTER: | ||
794 | case SDLK_RETURN: | ||
795 | case SDLK_a: | ||
796 | new_btn = BUTTON_PLAY; | ||
797 | break; | ||
798 | case SDLK_KP5: | ||
799 | case SDLK_SPACE: | ||
800 | new_btn = BUTTON_SELECT; | ||
801 | break; | ||
802 | case SDLK_KP_PERIOD: | ||
803 | case SDLK_INSERT: | ||
804 | new_btn = BUTTON_MENU; | ||
805 | break; | ||
775 | #else | 806 | #else |
776 | #error No keymap defined! | 807 | #error No keymap defined! |
777 | #endif /* CONFIG_KEYPAD */ | 808 | #endif /* CONFIG_KEYPAD */ |
diff --git a/uisimulator/sdl/uisdl.h b/uisimulator/sdl/uisdl.h index 37989a682b..890c6d0638 100644 --- a/uisimulator/sdl/uisdl.h +++ b/uisimulator/sdl/uisdl.h | |||
@@ -374,6 +374,19 @@ | |||
374 | #define UI_LCD_FGCOLOR 0, 0, 0 /* foreground color of LCD (no backlight) */ | 374 | #define UI_LCD_FGCOLOR 0, 0, 0 /* foreground color of LCD (no backlight) */ |
375 | #define UI_LCD_FGCOLORLIGHT 0, 0, 0 /* foreground color of LCD (backlight) */ | 375 | #define UI_LCD_FGCOLORLIGHT 0, 0, 0 /* foreground color of LCD (backlight) */ |
376 | 376 | ||
377 | #elif defined(MEIZU_M6SL) | ||
378 | #define UI_TITLE "Meizu M6" | ||
379 | #define UI_WIDTH 512 /* width of GUI window */ | ||
380 | #define UI_HEIGHT 322 /* height of GUI window */ | ||
381 | #define UI_LCD_POSX 39 /* x position of lcd */ | ||
382 | #define UI_LCD_POSY 38 /* y position of lcd */ | ||
383 | #define UI_LCD_WIDTH 320 | ||
384 | #define UI_LCD_HEIGHT 240 | ||
385 | #define UI_LCD_BGCOLOR 32, 32, 32 /* bkgnd color of LCD (no backlight) */ | ||
386 | #define UI_LCD_BGCOLORLIGHT 192, 192, 192 /* bkgnd color of LCD (backlight) */ | ||
387 | #define UI_LCD_FGCOLOR 0, 0, 0 /* foreground color of LCD (no backlight) */ | ||
388 | #define UI_LCD_FGCOLORLIGHT 0, 0, 0 /* foreground color of LCD (backlight) */ | ||
389 | |||
377 | #endif | 390 | #endif |
378 | extern SDL_Surface *gui_surface; | 391 | extern SDL_Surface *gui_surface; |
379 | extern bool background; /* True if the background image is enabled */ | 392 | extern bool background; /* True if the background image is enabled */ |