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author | Linus Nielsen Feltzing <linus@haxx.se> | 2006-03-28 20:35:08 +0000 |
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committer | Linus Nielsen Feltzing <linus@haxx.se> | 2006-03-28 20:35:08 +0000 |
commit | b7da52bb65dd3ecfc5f3695b97c8c0058c1fd92a (patch) | |
tree | 5c3648964d64d0aa89abf1e912334a565f5f1d32 | |
parent | 22593f4ace92209e3068bc0b9250f751fa597afd (diff) | |
download | rockbox-b7da52bb65dd3ecfc5f3695b97c8c0058c1fd92a.tar.gz rockbox-b7da52bb65dd3ecfc5f3695b97c8c0058c1fd92a.zip |
Some corrections of the TLV320 register bit definitions
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@9324 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/export/tlv320.h | 43 |
1 files changed, 21 insertions, 22 deletions
diff --git a/firmware/export/tlv320.h b/firmware/export/tlv320.h index c4599f02b2..93a79780c0 100644 --- a/firmware/export/tlv320.h +++ b/firmware/export/tlv320.h | |||
@@ -39,61 +39,60 @@ extern void tlv320_disable_recording(void); | |||
39 | /* registers */ | 39 | /* registers */ |
40 | /* REG_LLIV: Left line input channel volume control */ | 40 | /* REG_LLIV: Left line input channel volume control */ |
41 | #define REG_LLIV 0x0 | 41 | #define REG_LLIV 0x0 |
42 | #define LLIV_LRS (0 << 8) /* simultaneous volume/mute update */ | 42 | #define LLIV_LRS (1 << 8) /* simultaneous volume/mute update */ |
43 | #define LLIV_LIM (1 << 7) /* Left line input mute */ | 43 | #define LLIV_LIM (1 << 7) /* Left line input mute */ |
44 | #define LLIV_LIV(x) ((x) & 0x1f)/* Left line input volume control */ | 44 | #define LLIV_LIV(x) ((x) & 0x1f)/* Left line input volume control */ |
45 | 45 | ||
46 | /* REG_RLIV: Right line input channel volume control */ | 46 | /* REG_RLIV: Right line input channel volume control */ |
47 | #define REG_RLIV 0x1 | 47 | #define REG_RLIV 0x1 |
48 | #define RLIV_RLS (0 << 8) /* simultaneous volume/mute update */ | 48 | #define RLIV_RLS (1 << 8) /* simultaneous volume/mute update */ |
49 | #define RLIV_RIM (0 << 7) /* Right line input mute */ | 49 | #define RLIV_RIM (1 << 7) /* Right line input mute */ |
50 | #define RLIV_RIV(x) ((x) & 0x1f)/* Right line input volume control */ | 50 | #define RLIV_RIV(x) ((x) & 0x1f)/* Right line input volume control */ |
51 | 51 | ||
52 | /* REG_LHV: Left Channel Headphone Volume Control */ | 52 | /* REG_LHV: Left Channel Headphone Volume Control */ |
53 | #define REG_LHV 0x2 | 53 | #define REG_LHV 0x2 |
54 | #define LHV_LRS (0 << 8) /* simultaneous volume/mute update */ | 54 | #define LHV_LRS (1 << 8) /* simultaneous volume/mute update */ |
55 | #define LHV_LZC (0 << 7) /* Left-channel zero-cross detect */ | 55 | #define LHV_LZC (1 << 7) /* Left-channel zero-cross detect */ |
56 | #define LHV_LHV(x) ((x) & 0x7f)/* Left headphone volume control */ | 56 | #define LHV_LHV(x) ((x) & 0x7f)/* Left headphone volume control */ |
57 | 57 | ||
58 | /* REG_RHV: Right Channel Headphone Volume Control */ | 58 | /* REG_RHV: Right Channel Headphone Volume Control */ |
59 | #define REG_RHV 0x3 | 59 | #define REG_RHV 0x3 |
60 | #define RHV_LRS (0 << 8) /* simultaneous volume/mute update */ | 60 | #define RHV_LRS (1 << 8) /* simultaneous volume/mute update */ |
61 | #define RHV_RZC (0 << 7) /* Right-channel zero-cross detect */ | 61 | #define RHV_RZC (1 << 7) /* Right-channel zero-cross detect */ |
62 | #define RHV_RHV(x) ((x) & 0x7f)/* Right headphone volume control */ | 62 | #define RHV_RHV(x) ((x) & 0x7f)/* Right headphone volume control */ |
63 | 63 | ||
64 | /* REG_AAP: Analog Audio Path Control */ | 64 | /* REG_AAP: Analog Audio Path Control */ |
65 | #define REG_AAP 0x4 | 65 | #define REG_AAP 0x4 |
66 | #define AAP_DAC (1 << 4) /* DAC select */ | 66 | #define AAP_DAC (1 << 4) /* DAC select */ |
67 | #define AAP_BYPASS (1 << 3) /* bypass */ | 67 | #define AAP_BYPASS (1 << 3) /* bypass */ |
68 | #define AAP_INSEL (0 << 2) /* Input select for ADC */ | 68 | #define AAP_INSEL (1 << 2) /* Input select for ADC */ |
69 | #define AAP_MICM (1 << 1) /* Microphone mute */ | 69 | #define AAP_MICM (1 << 1) /* Microphone mute */ |
70 | #define AAP_MICB (1 << 0) /* Microphone boost */ | 70 | #define AAP_MICB (1 << 0) /* Microphone boost */ |
71 | 71 | ||
72 | /* REG_DAP: Digital Audio Path Control */ | 72 | /* REG_DAP: Digital Audio Path Control */ |
73 | #define REG_DAP 0x5 | 73 | #define REG_DAP 0x5 |
74 | #define DAP_DACM (1 << 3) /* DAC soft mute */ | 74 | #define DAP_DACM (1 << 3) /* DAC soft mute */ |
75 | #define DAP_DEEMP_DIS (0 << 1) /* De-emphasis control: disabled */ | ||
76 | #define DAP_DEEMP_32 (1 << 1) /* De-emphasis control: 32 kHz */ | 75 | #define DAP_DEEMP_32 (1 << 1) /* De-emphasis control: 32 kHz */ |
77 | #define DAP_DEEMP_44 (2 << 1) /* De-emphasis control: 44.1 kHz */ | 76 | #define DAP_DEEMP_44 (2 << 1) /* De-emphasis control: 44.1 kHz */ |
78 | #define DAP_DEEMP_48 (3 << 1) /* De-emphasis control: 48 kHz */ | 77 | #define DAP_DEEMP_48 (3 << 1) /* De-emphasis control: 48 kHz */ |
79 | #define DAP_ADCHP (0 << 0) /* ADC high-pass filter */ | 78 | #define DAP_ADCHP (1 << 0) /* ADC high-pass filter */ |
80 | 79 | ||
81 | /* REG_PC: Power Down Control */ | 80 | /* REG_PC: Power Down Control */ |
82 | #define REG_PC 0x6 | 81 | #define REG_PC 0x6 |
83 | #define PC_ON (0 << 7) /* Device power */ | 82 | #define PC_ON (1 << 7) /* Device power */ |
84 | #define PC_CLK (0 << 6) /* Clock */ | 83 | #define PC_CLK (1 << 6) /* Clock */ |
85 | #define PC_OSC (0 << 5) /* Oscillator */ | 84 | #define PC_OSC (1 << 5) /* Oscillator */ |
86 | #define PC_OUT (0 << 4) /* Outputs */ | 85 | #define PC_OUT (1 << 4) /* Outputs */ |
87 | #define PC_DAC (0 << 3) /* DAC */ | 86 | #define PC_DAC (1 << 3) /* DAC */ |
88 | #define PC_ADC (0 << 2) /* ADC */ | 87 | #define PC_ADC (1 << 2) /* ADC */ |
89 | #define PC_MIC (0 << 1) /* Microphone input */ | 88 | #define PC_MIC (1 << 1) /* Microphone input */ |
90 | #define PC_LINE (0 << 0) /* Line input */ | 89 | #define PC_LINE (1 << 0) /* Line input */ |
91 | 90 | ||
92 | /* REG_DAIF: Digital Audio Interface Format */ | 91 | /* REG_DAIF: Digital Audio Interface Format */ |
93 | #define REG_DAIF 0x7 | 92 | #define REG_DAIF 0x7 |
94 | #define DAIF_MS (1 << 6) /* Master/slave mode */ | 93 | #define DAIF_MS (1 << 6) /* Master/slave mode */ |
95 | #define DAIF_LRSWAP (1 << 5) /* DAC left/right swap */ | 94 | #define DAIF_LRSWAP (1 << 5) /* DAC left/right swap */ |
96 | #define DAIF_LRP (0 << 4) /* DAC left/right phase */ | 95 | #define DAIF_LRP (1 << 4) /* DAC left/right phase */ |
97 | #define DAIF_IWL_16 (0 << 2) /* Input bit length: 16 bit */ | 96 | #define DAIF_IWL_16 (0 << 2) /* Input bit length: 16 bit */ |
98 | #define DAIF_IWL_20 (1 << 2) /* Input bit length: 20 bit */ | 97 | #define DAIF_IWL_20 (1 << 2) /* Input bit length: 20 bit */ |
99 | #define DAIF_IWL_24 (2 << 2) /* Input bit length: 24 bit */ | 98 | #define DAIF_IWL_24 (2 << 2) /* Input bit length: 24 bit */ |
@@ -105,15 +104,15 @@ extern void tlv320_disable_recording(void); | |||
105 | 104 | ||
106 | /* REG_SRC: Sample Rate Control */ | 105 | /* REG_SRC: Sample Rate Control */ |
107 | #define REG_SRC 0x8 | 106 | #define REG_SRC 0x8 |
108 | #define SRC_CLKIN (0 << 6) /* Clock input divider */ | 107 | #define SRC_CLKIN (1 << 6) /* Clock input divider */ |
109 | #define SRC_CLKOUT (0 << 7) /* Clock output divider */ | 108 | #define SRC_CLKOUT (1 << 7) /* Clock output divider */ |
110 | /*#define SRC_SR ()*/ | 109 | /*#define SRC_SR ()*/ |
111 | #define SRC_BOSR (1 << 1) /* Base oversampling rate, depends on SRC_USB */ | 110 | #define SRC_BOSR (1 << 1) /* Base oversampling rate, depends on SRC_USB */ |
112 | #define SRC_USB (1 << 0) /* Clock mode select */ | 111 | #define SRC_USB (1 << 0) /* Clock mode select */ |
113 | 112 | ||
114 | /* REG_DIA: Digital Interface Activation */ | 113 | /* REG_DIA: Digital Interface Activation */ |
115 | #define REG_DIA 0x9 | 114 | #define REG_DIA 0x9 |
116 | #define DIA_ACT (1 << 6) /* Activate interface */ | 115 | #define DIA_ACT (1 << 0) /* Activate interface */ |
117 | 116 | ||
118 | /* REG_RR: Reset Register */ | 117 | /* REG_RR: Reset Register */ |
119 | #define REG_RR 0xf | 118 | #define REG_RR 0xf |