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author | Michael Sevakis <jethead71@rockbox.org> | 2007-10-02 08:30:30 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2007-10-02 08:30:30 +0000 |
commit | b6dab33dfdf32d32b27ed363f5f29b3db14af743 (patch) | |
tree | 58a8b74cb02f1d8e79149089806ba2bcacf55038 | |
parent | c9f699432d0c2b0b743a9b1df197c30692a94bda (diff) | |
download | rockbox-b6dab33dfdf32d32b27ed363f5f29b3db14af743.tar.gz rockbox-b6dab33dfdf32d32b27ed363f5f29b3db14af743.zip |
Ok. Really fix red
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14951 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/drivers/audio/wm8721.c | 17 | ||||
-rw-r--r-- | firmware/export/wm8721.h | 36 |
2 files changed, 25 insertions, 28 deletions
diff --git a/firmware/drivers/audio/wm8721.c b/firmware/drivers/audio/wm8721.c index 9b58454ca8..c175d2d74a 100644 --- a/firmware/drivers/audio/wm8721.c +++ b/firmware/drivers/audio/wm8721.c | |||
@@ -82,10 +82,10 @@ void audiohw_mute(bool mute) | |||
82 | if (mute) | 82 | if (mute) |
83 | { | 83 | { |
84 | /* Set DACMU = 1 to soft-mute the audio DACs. */ | 84 | /* Set DACMU = 1 to soft-mute the audio DACs. */ |
85 | wmcodec_write(DACCTRL, 0x8); | 85 | wmcodec_write(DAPCTRL, 0x8); |
86 | } else { | 86 | } else { |
87 | /* Set DACMU = 0 to soft-un-mute the audio DACs. */ | 87 | /* Set DACMU = 0 to soft-un-mute the audio DACs. */ |
88 | wmcodec_write(DACCTRL, 0x0); | 88 | wmcodec_write(DAPCTRL, 0x0); |
89 | } | 89 | } |
90 | } | 90 | } |
91 | 91 | ||
@@ -117,7 +117,7 @@ void audiohw_enable_output(bool enable) | |||
117 | wmcodec_write(0x4, 0x10); | 117 | wmcodec_write(0x4, 0x10); |
118 | 118 | ||
119 | /* set power register to POWEROFF=0 on OUTPD=0, DACPD=0 */ | 119 | /* set power register to POWEROFF=0 on OUTPD=0, DACPD=0 */ |
120 | wmcodec_write(PWRMGMT, 0x67); | 120 | wmcodec_write(PDCTRL, 0x67); |
121 | 121 | ||
122 | /* BCLKINV=0(Dont invert BCLK) MS=1(Enable Master) LRSWAP=0 LRP=0 */ | 122 | /* BCLKINV=0(Dont invert BCLK) MS=1(Enable Master) LRSWAP=0 LRP=0 */ |
123 | /* IWL=00(16 bit) FORMAT=10(I2S format) */ | 123 | /* IWL=00(16 bit) FORMAT=10(I2S format) */ |
@@ -133,7 +133,7 @@ void audiohw_enable_output(bool enable) | |||
133 | codec_set_active(1); | 133 | codec_set_active(1); |
134 | 134 | ||
135 | /* 5. Set DACMU = 0 to soft-un-mute the audio DACs. */ | 135 | /* 5. Set DACMU = 0 to soft-un-mute the audio DACs. */ |
136 | wmcodec_write(DACCTRL, 0x0); | 136 | wmcodec_write(DAPCTRL, 0x0); |
137 | 137 | ||
138 | audiohw_mute(0); | 138 | audiohw_mute(0); |
139 | } else { | 139 | } else { |
@@ -158,22 +158,19 @@ int audiohw_set_master_vol(int vol_l, int vol_r) | |||
158 | void audiohw_close(void) | 158 | void audiohw_close(void) |
159 | { | 159 | { |
160 | /* set DACMU=1 DEEMPH=0 */ | 160 | /* set DACMU=1 DEEMPH=0 */ |
161 | wmcodec_write(DACCTRL, 0x8); | 161 | wmcodec_write(DAPCTRL, 0x8); |
162 | 162 | ||
163 | /* ACTIVE=0 */ | 163 | /* ACTIVE=0 */ |
164 | codec_set_active(0x0); | 164 | codec_set_active(0x0); |
165 | 165 | ||
166 | /* line in mute left & right*/ | ||
167 | wmcodec_write(LINVOL, 0x100 | 0x80); | ||
168 | |||
169 | /* set DACSEL=0, MUTEMIC=1 */ | 166 | /* set DACSEL=0, MUTEMIC=1 */ |
170 | wmcodec_write(0x4, 0x2); | 167 | wmcodec_write(0x4, 0x2); |
171 | 168 | ||
172 | /* set POWEROFF=0 OUTPD=0 DACPD=1 */ | 169 | /* set POWEROFF=0 OUTPD=0 DACPD=1 */ |
173 | wmcodec_write(PWRMGMT, 0x6f); | 170 | wmcodec_write(PDCTRL, 0x6f); |
174 | 171 | ||
175 | /* set POWEROFF=1 OUTPD=1 DACPD=1 */ | 172 | /* set POWEROFF=1 OUTPD=1 DACPD=1 */ |
176 | wmcodec_write(PWRMGMT, 0xff); | 173 | wmcodec_write(PDCTRL, 0xff); |
177 | } | 174 | } |
178 | 175 | ||
179 | /* Change the order of the noise shaper, 5th order is recommended above 32kHz */ | 176 | /* Change the order of the noise shaper, 5th order is recommended above 32kHz */ |
diff --git a/firmware/export/wm8721.h b/firmware/export/wm8721.h index fb9cc535ab..223c3e1a0e 100644 --- a/firmware/export/wm8721.h +++ b/firmware/export/wm8721.h | |||
@@ -61,23 +61,23 @@ extern void audiohw_set_sample_rate(int sampling_control); | |||
61 | #define PDCTRL_POWEROFF (1 << 7) | 61 | #define PDCTRL_POWEROFF (1 << 7) |
62 | 62 | ||
63 | #define AINTFCE 0x07 | 63 | #define AINTFCE 0x07 |
64 | #define AINTFCE_FORMAT_MSB_RJUST(0 << 0) | 64 | #define AINTFCE_FORMAT_MSB_RJUST (0 << 0) |
65 | #define AINTFCE_FORMAT_MSB_LJUST(1 << 0) | 65 | #define AINTFCE_FORMAT_MSB_LJUST (1 << 0) |
66 | #define AINTFCE_FORMAT_I2S (2 << 0) | 66 | #define AINTFCE_FORMAT_I2S (2 << 0) |
67 | #define AINTFCE_FORMAT_DSP (3 << 0) | 67 | #define AINTFCE_FORMAT_DSP (3 << 0) |
68 | #define AINTFCE_FORMAT_MASK (3 << 0) | 68 | #define AINTFCE_FORMAT_MASK (3 << 0) |
69 | #define AINTFCE_IWL_16BIT (0 << 2) | 69 | #define AINTFCE_IWL_16BIT (0 << 2) |
70 | #define AINTFCE_IWL_20BIT (1 << 2) | 70 | #define AINTFCE_IWL_20BIT (1 << 2) |
71 | #define AINTFCE_IWL_24BIT (2 << 2) | 71 | #define AINTFCE_IWL_24BIT (2 << 2) |
72 | #define AINTFCE_IWL_32BIT (3 << 2) | 72 | #define AINTFCE_IWL_32BIT (3 << 2) |
73 | #define AINTFCE_IWL_MASK (3 << 2) | 73 | #define AINTFCE_IWL_MASK (3 << 2) |
74 | #define AINTFCE_LRP_I2S_RLO (0 << 4) | 74 | #define AINTFCE_LRP_I2S_RLO (0 << 4) |
75 | #define AINTFCE_LRP_I2S_RHI (1 << 4) | 75 | #define AINTFCE_LRP_I2S_RHI (1 << 4) |
76 | #define AINTFCE_DSP_MODE_A (0 << 4) | 76 | #define AINTFCE_DSP_MODE_A (0 << 4) |
77 | #define AINTFCE_DSP_MODE_B (1 << 4) | 77 | #define AINTFCE_DSP_MODE_B (1 << 4) |
78 | #define AINTFCE_LRSWAP (1 << 5) | 78 | #define AINTFCE_LRSWAP (1 << 5) |
79 | #define AINTFCE_MS (1 << 6) | 79 | #define AINTFCE_MS (1 << 6) |
80 | #define AINTFCE_BCLKINV (1 << 7) | 80 | #define AINTFCE_BCLKINV (1 << 7) |
81 | 81 | ||
82 | #define SAMPCTRL 0x08 | 82 | #define SAMPCTRL 0x08 |
83 | #define SAMPCTRL_USB (1 << 0) | 83 | #define SAMPCTRL_USB (1 << 0) |
@@ -86,7 +86,7 @@ extern void audiohw_set_sample_rate(int sampling_control); | |||
86 | #define SAMPCTRL_BOSR_USB_250fs (0 << 1) | 86 | #define SAMPCTRL_BOSR_USB_250fs (0 << 1) |
87 | #define SAMPCTRL_BOSR_USB_272fs (1 << 1) | 87 | #define SAMPCTRL_BOSR_USB_272fs (1 << 1) |
88 | /* Bits 2-5: | 88 | /* Bits 2-5: |
89 | * Sample rate setting are device-specific. See WM8731(L) datasheet | 89 | * Sample rate setting are device-specific. See WM8721 datasheet |
90 | * for proper settings for the device's clocking */ | 90 | * for proper settings for the device's clocking */ |
91 | #define SAMPCTRL_SR_MASK (0xf << 2) | 91 | #define SAMPCTRL_SR_MASK (0xf << 2) |
92 | #define SAMPCTRL_CLKIDIV2 (1 << 6) | 92 | #define SAMPCTRL_CLKIDIV2 (1 << 6) |