summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authoramachronic <amachronic@protonmail.com>2021-04-05 13:21:42 +0100
committeramachronic <amachronic@protonmail.com>2021-04-06 17:27:09 +0100
commitb5558c1cf968f0fcff072456408b14f130f29ce3 (patch)
tree333f75446e2e10e1152c22764e9a7f9d7a86ffcf
parent1b314502c838947a4f5b211ebf9814f39c7a3c9f (diff)
downloadrockbox-b5558c1cf968f0fcff072456408b14f130f29ce3.tar.gz
rockbox-b5558c1cf968f0fcff072456408b14f130f29ce3.zip
x1000: place SPL's NAND bounce buffers in DRAM
This frees up 2 KiB in the SPL's memory map, leaving more room for code. Change-Id: I01bbe2ab2905b2773a8b76d8c53e9f3d55bd040f
-rw-r--r--firmware/target/mips/ingenic_x1000/nand-x1000.c14
-rw-r--r--firmware/target/mips/ingenic_x1000/spl.lds14
2 files changed, 22 insertions, 6 deletions
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c
index 54a1d11d95..df86bebf4d 100644
--- a/firmware/target/mips/ingenic_x1000/nand-x1000.c
+++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c
@@ -40,11 +40,15 @@
40/* Defined by target */ 40/* Defined by target */
41extern const nand_chip_desc target_nand_chip_descs[]; 41extern const nand_chip_desc target_nand_chip_descs[];
42 42
43/* Globals for the driver 43#ifdef BOOTLOADER_SPL
44 * TODO: get rid of pagebuffer in the SPL to save code size 44# define NANDBUFFER_ATTR __attribute__((section(".sdram"))) CACHEALIGN_ATTR
45 */ 45#else
46static unsigned char pagebuffer[NAND_MAX_PAGE_SIZE] CACHEALIGN_ATTR; 46# define NANDBUFFER_ATTR CACHEALIGN_ATTR
47static unsigned char auxbuffer[NAND_AUX_BUFFER_SIZE] CACHEALIGN_ATTR; 47#endif
48
49/* Globals for the driver */
50static unsigned char pagebuffer[NAND_MAX_PAGE_SIZE] NANDBUFFER_ATTR;
51static unsigned char auxbuffer[NAND_AUX_BUFFER_SIZE] NANDBUFFER_ATTR;
48static nand_drv nand_driver; 52static nand_drv nand_driver;
49 53
50static void nand_drv_reset(nand_drv* d) 54static void nand_drv_reset(nand_drv* d)
diff --git a/firmware/target/mips/ingenic_x1000/spl.lds b/firmware/target/mips/ingenic_x1000/spl.lds
index 2a0b6b3eaa..ab4a2720f3 100644
--- a/firmware/target/mips/ingenic_x1000/spl.lds
+++ b/firmware/target/mips/ingenic_x1000/spl.lds
@@ -5,13 +5,20 @@ OUTPUT_ARCH(MIPS)
5ENTRY(_start) 5ENTRY(_start)
6STARTUP(target/mips/ingenic_x1000/crt0.o) 6STARTUP(target/mips/ingenic_x1000/crt0.o)
7 7
8#define DRAMORIG 0x80000000
9#define DRAMSIZE (MEMORYSIZE * 0x100000)
10#define USED_DRAM 16K
11
8/* TCSM is 16 KiB and is mapped starting at address 0xf4000000. 12/* TCSM is 16 KiB and is mapped starting at address 0xf4000000.
9 * 13 *
10 * The SPL is loaded to TCSM + 0x1000. The area below that is stack space. 14 * The SPL is loaded to TCSM + 0x1000. The area below that is stack space.
11 * The first 2 KiB of SPL is just headers. The code begins at TCSM + 0x1800. 15 * The first 2 KiB of SPL is just headers. The code begins at TCSM + 0x1800.
12 * The maskrom will jump to that address (via jalr) after loading the SPL. 16 * The maskrom will jump to that address (via jalr) after loading the SPL.
13 */ 17 */
14MEMORY { TCSM : ORIGIN = 0xf4001800, LENGTH = 0x2800 } 18MEMORY {
19 TCSM : ORIGIN = 0xf4001800, LENGTH = 0x2800
20 DRAM : ORIGIN = DRAMORIG + DRAMSIZE - USED_DRAM, LENGTH = USED_DRAM
21}
15 22
16SECTIONS 23SECTIONS
17{ 24{
@@ -44,4 +51,9 @@ SECTIONS
44 *(.scommon*); 51 *(.scommon*);
45 _bssend = .; 52 _bssend = .;
46 } > TCSM 53 } > TCSM
54
55 .sdram (NOLOAD) :
56 {
57 *(.sdram);
58 } > DRAM
47} 59}