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author | Amaury Pouly <pamaury@rockbox.org> | 2011-09-13 23:38:49 +0000 |
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committer | Amaury Pouly <pamaury@rockbox.org> | 2011-09-13 23:38:49 +0000 |
commit | b51ecea14aba6d86fc47cc79179eb19bdd0cd70a (patch) | |
tree | 6e62b27512cd2335a782d6dd1de502a7a709c61d | |
parent | ddb96f1b6533748585591e362579bd4528febd23 (diff) | |
download | rockbox-b51ecea14aba6d86fc47cc79179eb19bdd0cd70a.tar.gz rockbox-b51ecea14aba6d86fc47cc79179eb19bdd0cd70a.zip |
imx233/fuze+: add more interrupts, rewrite block resetting, reset icoll on boot (useful for firmware)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30524 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/target/arm/imx233/system-imx233.c | 28 | ||||
-rw-r--r-- | firmware/target/arm/imx233/system-target.h | 1 |
2 files changed, 25 insertions, 4 deletions
diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c index 8e742c0822..d27bb1b7d2 100644 --- a/firmware/target/arm/imx233/system-imx233.c +++ b/firmware/target/arm/imx233/system-imx233.c | |||
@@ -58,6 +58,14 @@ default_interrupt(INT_GPIO0); | |||
58 | default_interrupt(INT_GPIO1); | 58 | default_interrupt(INT_GPIO1); |
59 | default_interrupt(INT_GPIO2); | 59 | default_interrupt(INT_GPIO2); |
60 | default_interrupt(INT_VDD5V); | 60 | default_interrupt(INT_VDD5V); |
61 | default_interrupt(INT_LRADC_CH0); | ||
62 | default_interrupt(INT_LRADC_CH1); | ||
63 | default_interrupt(INT_LRADC_CH2); | ||
64 | default_interrupt(INT_LRADC_CH3); | ||
65 | default_interrupt(INT_LRADC_CH4); | ||
66 | default_interrupt(INT_LRADC_CH5); | ||
67 | default_interrupt(INT_LRADC_CH6); | ||
68 | default_interrupt(INT_LRADC_CH7); | ||
61 | 69 | ||
62 | typedef void (*isr_t)(void); | 70 | typedef void (*isr_t)(void); |
63 | 71 | ||
@@ -80,6 +88,14 @@ static isr_t isr_table[INT_SRC_NR_SOURCES] = | |||
80 | [INT_SRC_GPIO1] = INT_GPIO1, | 88 | [INT_SRC_GPIO1] = INT_GPIO1, |
81 | [INT_SRC_GPIO2] = INT_GPIO2, | 89 | [INT_SRC_GPIO2] = INT_GPIO2, |
82 | [INT_SRC_VDD5V] = INT_VDD5V, | 90 | [INT_SRC_VDD5V] = INT_VDD5V, |
91 | [INT_SRC_LRADC_CHx(0)] = INT_LRADC_CH0, | ||
92 | [INT_SRC_LRADC_CHx(1)] = INT_LRADC_CH1, | ||
93 | [INT_SRC_LRADC_CHx(2)] = INT_LRADC_CH2, | ||
94 | [INT_SRC_LRADC_CHx(3)] = INT_LRADC_CH3, | ||
95 | [INT_SRC_LRADC_CHx(4)] = INT_LRADC_CH4, | ||
96 | [INT_SRC_LRADC_CHx(5)] = INT_LRADC_CH5, | ||
97 | [INT_SRC_LRADC_CHx(6)] = INT_LRADC_CH6, | ||
98 | [INT_SRC_LRADC_CHx(7)] = INT_LRADC_CH7, | ||
83 | }; | 99 | }; |
84 | 100 | ||
85 | static void UIRQ(void) | 101 | static void UIRQ(void) |
@@ -100,7 +116,7 @@ void fiq_handler(void) | |||
100 | { | 116 | { |
101 | } | 117 | } |
102 | 118 | ||
103 | static void imx233_chip_reset(void) | 119 | void imx233_chip_reset(void) |
104 | { | 120 | { |
105 | HW_CLKCTRL_RESET = HW_CLKCTRL_RESET_CHIP; | 121 | HW_CLKCTRL_RESET = HW_CLKCTRL_RESET_CHIP; |
106 | } | 122 | } |
@@ -168,6 +184,7 @@ void memory_init(void) | |||
168 | 184 | ||
169 | void system_init(void) | 185 | void system_init(void) |
170 | { | 186 | { |
187 | imx233_reset_block(&HW_ICOLL_CTRL); | ||
171 | /* disable all interrupts */ | 188 | /* disable all interrupts */ |
172 | for(int i = 0; i < INT_SRC_NR_SOURCES; i++) | 189 | for(int i = 0; i < INT_SRC_NR_SOURCES; i++) |
173 | { | 190 | { |
@@ -196,13 +213,14 @@ bool imx233_us_elapsed(uint32_t ref, unsigned us_delay) | |||
196 | 213 | ||
197 | void imx233_reset_block(volatile uint32_t *block_reg) | 214 | void imx233_reset_block(volatile uint32_t *block_reg) |
198 | { | 215 | { |
199 | __REG_CLR(*block_reg) = __BLOCK_SFTRST; | 216 | /* soft-reset */ |
200 | while(*block_reg & __BLOCK_SFTRST); | ||
201 | __REG_CLR(*block_reg) = __BLOCK_CLKGATE; | ||
202 | __REG_SET(*block_reg) = __BLOCK_SFTRST; | 217 | __REG_SET(*block_reg) = __BLOCK_SFTRST; |
218 | /* make sure block is gated off */ | ||
203 | while(!(*block_reg & __BLOCK_CLKGATE)); | 219 | while(!(*block_reg & __BLOCK_CLKGATE)); |
220 | /* bring block out of reset */ | ||
204 | __REG_CLR(*block_reg) = __BLOCK_SFTRST; | 221 | __REG_CLR(*block_reg) = __BLOCK_SFTRST; |
205 | while(*block_reg & __BLOCK_SFTRST); | 222 | while(*block_reg & __BLOCK_SFTRST); |
223 | /* make sure clock is running */ | ||
206 | __REG_CLR(*block_reg) = __BLOCK_CLKGATE; | 224 | __REG_CLR(*block_reg) = __BLOCK_CLKGATE; |
207 | while(*block_reg & __BLOCK_CLKGATE); | 225 | while(*block_reg & __BLOCK_CLKGATE); |
208 | } | 226 | } |
@@ -218,6 +236,7 @@ void set_cpu_frequency(long frequency) | |||
218 | { | 236 | { |
219 | switch(frequency) | 237 | switch(frequency) |
220 | { | 238 | { |
239 | #if 0 | ||
221 | case IMX233_CPUFREQ_454_MHz: | 240 | case IMX233_CPUFREQ_454_MHz: |
222 | /* clk_h@clk_p/3 */ | 241 | /* clk_h@clk_p/3 */ |
223 | imx233_set_clock_divisor(CLK_AHB, 3); | 242 | imx233_set_clock_divisor(CLK_AHB, 3); |
@@ -228,6 +247,7 @@ void set_cpu_frequency(long frequency) | |||
228 | * clk_p@454.74 MHz | 247 | * clk_p@454.74 MHz |
229 | * clk_h@151.58 MHz */ | 248 | * clk_h@151.58 MHz */ |
230 | break; | 249 | break; |
250 | #endif | ||
231 | default: | 251 | default: |
232 | break; | 252 | break; |
233 | } | 253 | } |
diff --git a/firmware/target/arm/imx233/system-target.h b/firmware/target/arm/imx233/system-target.h index a5dc63d430..fd817a9950 100644 --- a/firmware/target/arm/imx233/system-target.h +++ b/firmware/target/arm/imx233/system-target.h | |||
@@ -62,6 +62,7 @@ | |||
62 | #define INT_SRC_I2C_DMA 26 | 62 | #define INT_SRC_I2C_DMA 26 |
63 | #define INT_SRC_I2C_ERROR 27 | 63 | #define INT_SRC_I2C_ERROR 27 |
64 | #define INT_SRC_TIMER(nr) (28 + (nr)) | 64 | #define INT_SRC_TIMER(nr) (28 + (nr)) |
65 | #define INT_SRC_LRADC_CHx(x) (37 + (x)) | ||
65 | #define INT_SRC_LCDIF_DMA 45 | 66 | #define INT_SRC_LCDIF_DMA 45 |
66 | #define INT_SRC_LCDIF_ERROR 46 | 67 | #define INT_SRC_LCDIF_ERROR 46 |
67 | #define INT_SRC_NR_SOURCES 66 | 68 | #define INT_SRC_NR_SOURCES 66 |