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| author | Linus Nielsen Feltzing <linus@haxx.se> | 2006-03-28 12:47:10 +0000 |
|---|---|---|
| committer | Linus Nielsen Feltzing <linus@haxx.se> | 2006-03-28 12:47:10 +0000 |
| commit | a8c1fb55a4b2adf25b90521d027246f6c86bdfc4 (patch) | |
| tree | 379380274248d92faa94f9cc83d119ceccb68034 | |
| parent | ab5b1796147b9d4e2513fd9e514891392e4308c3 (diff) | |
| download | rockbox-a8c1fb55a4b2adf25b90521d027246f6c86bdfc4.tar.gz rockbox-a8c1fb55a4b2adf25b90521d027246f6c86bdfc4.zip | |
Correct audio clock
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@9309 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/target/coldfire/iaudio/x5/system-x5.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/target/coldfire/iaudio/x5/system-x5.c b/firmware/target/coldfire/iaudio/x5/system-x5.c index 1d9293b5c5..dee605733f 100644 --- a/firmware/target/coldfire/iaudio/x5/system-x5.c +++ b/firmware/target/coldfire/iaudio/x5/system-x5.c | |||
| @@ -37,7 +37,7 @@ void set_cpu_frequency(long frequency) | |||
| 37 | /* Refresh timer for bypass frequency */ | 37 | /* Refresh timer for bypass frequency */ |
| 38 | PLLCR &= ~1; /* Bypass mode */ | 38 | PLLCR &= ~1; /* Bypass mode */ |
| 39 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | 39 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); |
| 40 | PLLCR = 0x13442045; | 40 | PLLCR = 0x13042045; |
| 41 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ | 41 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ |
| 42 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ | 42 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ |
| 43 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 43 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
| @@ -54,7 +54,7 @@ void set_cpu_frequency(long frequency) | |||
| 54 | /* Refresh timer for bypass frequency */ | 54 | /* Refresh timer for bypass frequency */ |
| 55 | PLLCR &= ~1; /* Bypass mode */ | 55 | PLLCR &= ~1; /* Bypass mode */ |
| 56 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | 56 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); |
| 57 | PLLCR = 0x16430045; | 57 | PLLCR = 0x16030045; |
| 58 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ | 58 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ |
| 59 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 59 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
| 60 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 60 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |