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author | Solomon Peachy <pizza@shaftnet.org> | 2021-04-01 06:18:06 -0400 |
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committer | Solomon Peachy <pizza@shaftnet.org> | 2021-04-01 08:45:43 -0400 |
commit | 9f7f1a841a11b9eb3c4c356a875c82ed58658a63 (patch) | |
tree | b80c7b5bb77ceee5859578882f75c92775555fe3 | |
parent | 0b20038d871be393a853864a3e6e3d2ff489860f (diff) | |
download | rockbox-9f7f1a841a11b9eb3c4c356a875c82ed58658a63.tar.gz rockbox-9f7f1a841a11b9eb3c4c356a875c82ed58658a63.zip |
PP: Use CURRENT_CORE instead of IF_COP_CORE(CPU)
Use of IF_COP_CORE was mistakenly introduced as part of 89acde6af2,
effectively short-circuiting multiple tests resulting in the code
paths always being executed, on both cores.
Use the correct macro, so per-CPU paths are handled properly.
Change-Id: Id346cf759fc1b06b7d56694d7af1f469caf785a4
-rw-r--r-- | firmware/target/arm/pp/system-pp502x.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/firmware/target/arm/pp/system-pp502x.c b/firmware/target/arm/pp/system-pp502x.c index 686e2ac3bd..b1e791ec59 100644 --- a/firmware/target/arm/pp/system-pp502x.c +++ b/firmware/target/arm/pp/system-pp502x.c | |||
@@ -59,7 +59,7 @@ unsigned char probed_ramsize; | |||
59 | 59 | ||
60 | void __attribute__((interrupt("IRQ"))) irq_handler(void) | 60 | void __attribute__((interrupt("IRQ"))) irq_handler(void) |
61 | { | 61 | { |
62 | if(IF_COP_CORE(CPU) == CPU) | 62 | if(CURRENT_CORE == CPU) |
63 | { | 63 | { |
64 | if (CPU_INT_STAT & TIMER1_MASK) { | 64 | if (CPU_INT_STAT & TIMER1_MASK) { |
65 | TIMER1(); | 65 | TIMER1(); |
@@ -250,7 +250,7 @@ static void ICODE_ATTR cache_invalidate_special(void) | |||
250 | bit 24-31 unused? | 250 | bit 24-31 unused? |
251 | */ | 251 | */ |
252 | register volatile unsigned long *p; | 252 | register volatile unsigned long *p; |
253 | if (IF_COP_CORE(CPU) == CPU) | 253 | if (CURRENT_CORE == CPU) |
254 | { | 254 | { |
255 | for (p = &CACHE_STATUS_BASE_CPU; | 255 | for (p = &CACHE_STATUS_BASE_CPU; |
256 | p < (&CACHE_STATUS_BASE_CPU) + CACHE_SIZE; | 256 | p < (&CACHE_STATUS_BASE_CPU) + CACHE_SIZE; |
@@ -292,7 +292,7 @@ static void init_cache(void) | |||
292 | 292 | ||
293 | #ifndef BOOTLOADER | 293 | #ifndef BOOTLOADER |
294 | /* what's this do? */ | 294 | /* what's this do? */ |
295 | CACHE_PRIORITY |= IF_COP_CORE(CPU) == CPU ? 0x10 : 0x20; | 295 | CACHE_PRIORITY |= (CURRENT_CORE == CPU) ? 0x10 : 0x20; |
296 | #endif | 296 | #endif |
297 | 297 | ||
298 | /* Cache if (addr & mask) >> 16 == (mask & match) >> 16: | 298 | /* Cache if (addr & mask) >> 16 == (mask & match) >> 16: |
@@ -324,7 +324,7 @@ static void init_cache(void) | |||
324 | void scale_suspend_core(bool suspend) ICODE_ATTR; | 324 | void scale_suspend_core(bool suspend) ICODE_ATTR; |
325 | void scale_suspend_core(bool suspend) | 325 | void scale_suspend_core(bool suspend) |
326 | { | 326 | { |
327 | unsigned int core = IF_COP_CORE(CPU); | 327 | unsigned int core = CURRENT_CORE; |
328 | IF_COP( unsigned int othercore = 1 - core; ) | 328 | IF_COP( unsigned int othercore = 1 - core; ) |
329 | static int oldstatus IBSS_ATTR; | 329 | static int oldstatus IBSS_ATTR; |
330 | 330 | ||
@@ -366,9 +366,9 @@ static void pp_set_cpu_frequency(long frequency) | |||
366 | /* Note1: The PP5022 PLL must be run at >= 96MHz | 366 | /* Note1: The PP5022 PLL must be run at >= 96MHz |
367 | * Bits 20..21 select the post divider (1/2/4/8). | 367 | * Bits 20..21 select the post divider (1/2/4/8). |
368 | * PP5026 is similar to PP5022 except it doesn't | 368 | * PP5026 is similar to PP5022 except it doesn't |
369 | * have this limitation (and the post divider?) | 369 | * have this limitation (and the post divider?) |
370 | * Note2: CLOCK_SOURCE is set via 0=32kHz, 1=16MHz, | 370 | * Note2: CLOCK_SOURCE is set via 0=32kHz, 1=16MHz, |
371 | * 2=24MHz, 3=33MHz, 4=48MHz, 5=SLOW, 6=FAST, 7=PLL. | 371 | * 2=24MHz, 3=33MHz, 4=48MHz, 5=SLOW, 6=FAST, 7=PLL. |
372 | * SLOW = 24MHz / (DIV_SLOW + 1), DIV = Bits 16-19 | 372 | * SLOW = 24MHz / (DIV_SLOW + 1), DIV = Bits 16-19 |
373 | * FAST = PLL / (DIV_FAST + 1), DIV = Bits 20-23 */ | 373 | * FAST = PLL / (DIV_FAST + 1), DIV = Bits 20-23 */ |
374 | case CPUFREQ_SLEEP: | 374 | case CPUFREQ_SLEEP: |
@@ -473,7 +473,7 @@ static void pp_set_cpu_frequency(long frequency) | |||
473 | #ifndef BOOTLOADER | 473 | #ifndef BOOTLOADER |
474 | void system_init(void) | 474 | void system_init(void) |
475 | { | 475 | { |
476 | if (IF_COP_CORE(CPU) == CPU) | 476 | if (CURRENT_CORE == CPU) |
477 | { | 477 | { |
478 | #if defined (IRIVER_H10) || defined(IRIVER_H10_5GB) || defined(IPOD_COLOR) | 478 | #if defined (IRIVER_H10) || defined(IRIVER_H10_5GB) || defined(IPOD_COLOR) |
479 | /* set minimum startup configuration */ | 479 | /* set minimum startup configuration */ |
@@ -659,7 +659,7 @@ void system_exception_wait(void) | |||
659 | COP_INT_DIS = -1; | 659 | COP_INT_DIS = -1; |
660 | 660 | ||
661 | /* Halt */ | 661 | /* Halt */ |
662 | PROC_CTL(IF_COP_CORE(CPU)) = 0x40000000; | 662 | PROC_CTL(CURRENT_CORE) = 0x40000000; |
663 | while (1); | 663 | while (1); |
664 | } | 664 | } |
665 | 665 | ||