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| author | Michael Sevakis <jethead71@rockbox.org> | 2013-05-21 20:39:22 -0400 |
|---|---|---|
| committer | Michael Sevakis <jethead71@rockbox.org> | 2013-05-21 20:39:22 -0400 |
| commit | 9b43f14165cdb4fd77a5e9c8a1213486dcb8ca67 (patch) | |
| tree | 9d07fd76dadb2cfcdcb39cc8a58a916c37ac7cfb | |
| parent | ed24e620290ad5290fc4178f13e5c7cf611a76e0 (diff) | |
| download | rockbox-9b43f14165cdb4fd77a5e9c8a1213486dcb8ca67.tar.gz rockbox-9b43f14165cdb4fd77a5e9c8a1213486dcb8ca67.zip | |
SPC Codec: Simplify configuration and assume nothing need be disabled.
Most SoCs are these days are fast enough for realtime BRR, gaussian
interpolation and echo processing.
Change-Id: I180ce8ad45242c67b5e573a406b9522098a3f12b
| -rw-r--r-- | lib/rbcodec/codecs/libspc/spc_codec.h | 54 |
1 files changed, 21 insertions, 33 deletions
diff --git a/lib/rbcodec/codecs/libspc/spc_codec.h b/lib/rbcodec/codecs/libspc/spc_codec.h index fad5a49916..96ca734f4c 100644 --- a/lib/rbcodec/codecs/libspc/spc_codec.h +++ b/lib/rbcodec/codecs/libspc/spc_codec.h | |||
| @@ -41,53 +41,41 @@ | |||
| 41 | #define ARM_ARCH 0 | 41 | #define ARM_ARCH 0 |
| 42 | #endif | 42 | #endif |
| 43 | 43 | ||
| 44 | #define SPC_DUAL_CORE 1 | 44 | #if NUM_CORES == 1 |
| 45 | |||
| 46 | #if !defined(SPC_DUAL_CORE) || NUM_CORES == 1 | ||
| 47 | #undef SPC_DUAL_CORE | ||
| 48 | #define SPC_DUAL_CORE 0 | 45 | #define SPC_DUAL_CORE 0 |
| 46 | #else | ||
| 47 | #define SPC_DUAL_CORE 1 | ||
| 49 | #endif | 48 | #endif |
| 50 | 49 | ||
| 51 | /* Only some targets are fast enough for gaussian and realtime BRR decode */ | 50 | /* Only some targets are too slow for gaussian and realtime BRR decode */ |
| 52 | #if CONFIG_CPU == S3C2440 || CONFIG_CPU == IMX31L || \ | 51 | #if defined(CPU_COLDFIRE) |
| 53 | CONFIG_CPU == AS3525 || CONFIG_CPU == AS3525v2 || \ | ||
| 54 | defined(CPU_S5L870X) || \ | ||
| 55 | (CONFIG_PLATFORM & PLATFORM_HOSTED) || MEMORYSIZE <= 2 | ||
| 56 | /* Don't cache BRR waves */ | ||
| 57 | #define SPC_BRRCACHE 0 | ||
| 58 | |||
| 59 | /* Allow gaussian interpolation */ | ||
| 60 | #define SPC_NOINTERP 0 | ||
| 61 | |||
| 62 | /* Allow echo processing */ | ||
| 63 | #define SPC_NOECHO 0 | ||
| 64 | #elif defined(CPU_COLDFIRE) | ||
| 65 | /* Cache BRR waves */ | 52 | /* Cache BRR waves */ |
| 66 | #define SPC_BRRCACHE 1 | 53 | #define SPC_BRRCACHE 1 |
| 67 | |||
| 68 | /* Disable gaussian interpolation */ | 54 | /* Disable gaussian interpolation */ |
| 69 | #define SPC_NOINTERP 1 | 55 | #define SPC_NOINTERP 1 |
| 70 | 56 | #elif defined (CPU_PP) | |
| 71 | /* Allow echo processing */ | ||
| 72 | #define SPC_NOECHO 0 | ||
| 73 | #elif defined (CPU_PP) && SPC_DUAL_CORE | ||
| 74 | /* Cache BRR waves */ | 57 | /* Cache BRR waves */ |
| 75 | #define SPC_BRRCACHE 1 | 58 | #define SPC_BRRCACHE 1 |
| 76 | |||
| 77 | /* Disable gaussian interpolation */ | 59 | /* Disable gaussian interpolation */ |
| 78 | #define SPC_NOINTERP 1 | 60 | #define SPC_NOINTERP 1 |
| 61 | #if !SPC_DUAL_CORE | ||
| 62 | /* Disable echo processing */ | ||
| 63 | #define SPC_NOECHO 1 | ||
| 64 | #endif | ||
| 65 | #endif /* CPU_* */ | ||
| 79 | 66 | ||
| 67 | /** Turn on, by default, all the good stuff **/ | ||
| 68 | #ifndef SPC_BRRCACHE | ||
| 69 | /* Don't cache BRR waves */ | ||
| 70 | #define SPC_BRRCACHE 0 | ||
| 71 | #endif | ||
| 72 | #ifndef SPC_NOINTERP | ||
| 73 | /* Allow gaussian interpolation */ | ||
| 74 | #define SPC_NOINTERP 0 | ||
| 75 | #endif | ||
| 76 | #ifndef SPC_NOECHO | ||
| 80 | /* Allow echo processing */ | 77 | /* Allow echo processing */ |
| 81 | #define SPC_NOECHO 0 | 78 | #define SPC_NOECHO 0 |
| 82 | #else | ||
| 83 | /* Cache BRR waves */ | ||
| 84 | #define SPC_BRRCACHE 1 | ||
| 85 | |||
| 86 | /* Disable gaussian interpolation */ | ||
| 87 | #define SPC_NOINTERP 1 | ||
| 88 | |||
| 89 | /* Disable echo processing */ | ||
| 90 | #define SPC_NOECHO 1 | ||
| 91 | #endif | 79 | #endif |
| 92 | 80 | ||
| 93 | #if (CONFIG_CPU == MCF5250) | 81 | #if (CONFIG_CPU == MCF5250) |