diff options
author | Karl Kurbjun <kkurbjun@gmail.com> | 2007-09-23 23:08:39 +0000 |
---|---|---|
committer | Karl Kurbjun <kkurbjun@gmail.com> | 2007-09-23 23:08:39 +0000 |
commit | 9ac9cc6024271f806af23a84903d809eb145dc60 (patch) | |
tree | 66ff450d331c4dfae8758281a7faa47ffd2f752f | |
parent | d969a420b6c7f9aee321d218b7a9feb1c7158703 (diff) | |
download | rockbox-9ac9cc6024271f806af23a84903d809eb145dc60.tar.gz rockbox-9ac9cc6024271f806af23a84903d809eb145dc60.zip |
Working DM320 interrupts, changed the way registers are accessed in spi and uart drivers. Uart might be broken with interrupts - buttons on remote don't seem to respond when interrupts are enabled.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14836 a1c6a512-1295-4272-9138-f99709370657
-rwxr-xr-x | bootloader/mrobe500.c | 37 | ||||
-rw-r--r-- | firmware/export/dm320.h | 128 | ||||
-rw-r--r-- | firmware/target/arm/olympus/mrobe-500/ata-mr500.c | 4 | ||||
-rw-r--r-- | firmware/target/arm/olympus/mrobe-500/button-mr500.c | 4 | ||||
-rwxr-xr-x | firmware/target/arm/olympus/mrobe-500/crt0.S | 2 | ||||
-rw-r--r-- | firmware/target/arm/olympus/mrobe-500/kernel-mr500.c | 14 | ||||
-rw-r--r-- | firmware/target/arm/olympus/mrobe-500/spi-mr500.c | 6 | ||||
-rw-r--r-- | firmware/target/arm/olympus/mrobe-500/system-mr500.c | 32 | ||||
-rw-r--r-- | firmware/target/arm/olympus/mrobe-500/timer-target.h | 2 | ||||
-rw-r--r-- | firmware/target/arm/olympus/mrobe-500/uart-mr500.c | 36 |
10 files changed, 134 insertions, 131 deletions
diff --git a/bootloader/mrobe500.c b/bootloader/mrobe500.c index 236fd99ff0..57df653f10 100755 --- a/bootloader/mrobe500.c +++ b/bootloader/mrobe500.c | |||
@@ -46,19 +46,20 @@ extern int line; | |||
46 | 46 | ||
47 | void main(void) | 47 | void main(void) |
48 | { | 48 | { |
49 | /* unsigned char* loadbuffer; | 49 | unsigned char* loadbuffer; |
50 | int buffer_size; | 50 | int buffer_size; |
51 | int rc; | 51 | int rc; |
52 | int(*kernel_entry)(void); | 52 | int(*kernel_entry)(void); |
53 | */ | 53 | |
54 | power_init(); | 54 | power_init(); |
55 | lcd_init(); | ||
55 | system_init(); | 56 | system_init(); |
56 | kernel_init(); | 57 | kernel_init(); |
57 | adc_init(); | 58 | adc_init(); |
58 | button_init(); | 59 | button_init(); |
59 | backlight_init(); | 60 | backlight_init(); |
60 | uartSetup(); | 61 | uartSetup(); |
61 | lcd_init(); | 62 | |
62 | font_init(); | 63 | font_init(); |
63 | spi_init(); | 64 | spi_init(); |
64 | 65 | ||
@@ -73,7 +74,6 @@ void main(void) | |||
73 | 74 | ||
74 | usb_init(); | 75 | usb_init(); |
75 | 76 | ||
76 | #if 0 | ||
77 | /* Enter USB mode without USB thread */ | 77 | /* Enter USB mode without USB thread */ |
78 | if(usb_detect()) | 78 | if(usb_detect()) |
79 | { | 79 | { |
@@ -99,18 +99,25 @@ void main(void) | |||
99 | reset_screen(); | 99 | reset_screen(); |
100 | lcd_update(); | 100 | lcd_update(); |
101 | } | 101 | } |
102 | #endif | ||
103 | 102 | ||
104 | printf("ATA"); | 103 | int button=0, *address=0x0, count=0; |
105 | |||
106 | outw(inw(IO_GIO_DIR1)&~(1<<10), IO_GIO_DIR1); // set GIO26 (reset pin) to output | ||
107 | while(true) | 104 | while(true) |
108 | { | 105 | { |
109 | if (button_read_device() == BUTTON_POWER) | 106 | button = button_read_device(); |
107 | if (button == BUTTON_POWER) | ||
110 | { | 108 | { |
111 | printf("reset"); | 109 | printf("reset"); |
112 | outw(1<<10, IO_GIO_BITSET1); | 110 | IO_GIO_BITSET1|=1<<10; |
113 | } | 111 | } |
112 | if(button==BUTTON_RC_PLAY) | ||
113 | address+=0x02; | ||
114 | else if (button==BUTTON_RC_DOWN) | ||
115 | address-=0x02; | ||
116 | else if (button==BUTTON_RC_FF) | ||
117 | address+=0x1000; | ||
118 | else if (button==BUTTON_RC_REW) | ||
119 | address-=0x1000; | ||
120 | |||
114 | // if ((inw(IO_GIO_BITSET0)&(1<<14)) == 0) | 121 | // if ((inw(IO_GIO_BITSET0)&(1<<14)) == 0) |
115 | { | 122 | { |
116 | short x,y,z1,z2, reg; | 123 | short x,y,z1,z2, reg; |
@@ -118,12 +125,15 @@ void main(void) | |||
118 | printf("x: %04x y: %04x z1: %04x z2: %04x", x, y, z1, z2); | 125 | printf("x: %04x y: %04x z1: %04x z2: %04x", x, y, z1, z2); |
119 | printf("tsadc: %4x", tsc2100_readreg(TSADC_PAGE, TSADC_ADDRESS)&0xffff); | 126 | printf("tsadc: %4x", tsc2100_readreg(TSADC_PAGE, TSADC_ADDRESS)&0xffff); |
120 | printf("current tick: %04x", current_tick); | 127 | printf("current tick: %04x", current_tick); |
128 | printf("Address: 0x%08x Data: 0x%08x", address, *address); | ||
129 | printf("Address: 0x%08x Data: 0x%08x", address+1, *(address+1)); | ||
130 | printf("Address: 0x%08x Data: 0x%08x", address+2, *(address+2)); | ||
121 | tsc2100_keyclick(); /* doesnt work :( */ | 131 | tsc2100_keyclick(); /* doesnt work :( */ |
122 | line -= 3; | 132 | line -= 6; |
123 | } | 133 | } |
124 | |||
125 | } | 134 | } |
126 | #if 0 | 135 | |
136 | printf("ATA"); | ||
127 | rc = ata_init(); | 137 | rc = ata_init(); |
128 | if(rc) | 138 | if(rc) |
129 | { | 139 | { |
@@ -155,5 +165,4 @@ void main(void) | |||
155 | kernel_entry = (void*) loadbuffer; | 165 | kernel_entry = (void*) loadbuffer; |
156 | rc = kernel_entry(); | 166 | rc = kernel_entry(); |
157 | } | 167 | } |
158 | #endif | ||
159 | } | 168 | } |
diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h index 70992b715d..93f2f3affc 100644 --- a/firmware/export/dm320.h +++ b/firmware/export/dm320.h | |||
@@ -75,21 +75,21 @@ | |||
75 | #define IO_SERIAL1_MODE DM320_REG(0x0286) | 75 | #define IO_SERIAL1_MODE DM320_REG(0x0286) |
76 | 76 | ||
77 | /* UART 0/1 */ | 77 | /* UART 0/1 */ |
78 | #define IO_UART0_DTRR 0x0300 | 78 | #define IO_UART0_DTRR DM320_REG(0x0300) |
79 | #define IO_UART0_BRSR 0x0302 | 79 | #define IO_UART0_BRSR DM320_REG(0x0302) |
80 | #define IO_UART0_MSR 0x0304 | 80 | #define IO_UART0_MSR DM320_REG(0x0304) |
81 | #define IO_UART0_RFCR 0x0306 | 81 | #define IO_UART0_RFCR DM320_REG(0x0306) |
82 | #define IO_UART0_TFCR 0x0308 | 82 | #define IO_UART0_TFCR DM320_REG(0x0308) |
83 | #define IO_UART0_LCR 0x030A | 83 | #define IO_UART0_LCR DM320_REG(0x030A) |
84 | #define IO_UART0_SR 0x030C | 84 | #define IO_UART0_SR DM320_REG(0x030C) |
85 | 85 | ||
86 | #define IO_UART1_DTRR 0x0380 | 86 | #define IO_UART1_DTRR DM320_REG(0x0380) |
87 | #define IO_UART1_BRSR 0x0382 | 87 | #define IO_UART1_BRSR DM320_REG(0x0382) |
88 | #define IO_UART1_MSR 0x0384 | 88 | #define IO_UART1_MSR DM320_REG(0x0384) |
89 | #define IO_UART1_RFCR 0x0386 | 89 | #define IO_UART1_RFCR DM320_REG(0x0386) |
90 | #define IO_UART1_TFCR 0x0388 | 90 | #define IO_UART1_TFCR DM320_REG(0x0388) |
91 | #define IO_UART1_LCR 0x038A | 91 | #define IO_UART1_LCR DM320_REG(0x038A) |
92 | #define IO_UART1_SR 0x038C | 92 | #define IO_UART1_SR DM320_REG(0x038C) |
93 | 93 | ||
94 | /* Watchdog Timer */ | 94 | /* Watchdog Timer */ |
95 | #define IO_WATCHDOG_MODE 0x0400 | 95 | #define IO_WATCHDOG_MODE 0x0400 |
@@ -168,55 +168,55 @@ | |||
168 | #define IO_INTC_ENTRY_TBA0 DM320_REG(0x0538) | 168 | #define IO_INTC_ENTRY_TBA0 DM320_REG(0x0538) |
169 | #define IO_INTC_ENTRY_TBA1 DM320_REG(0x053A) | 169 | #define IO_INTC_ENTRY_TBA1 DM320_REG(0x053A) |
170 | #define IO_INTC_PRIORITY0 DM320_REG(0x0540) | 170 | #define IO_INTC_PRIORITY0 DM320_REG(0x0540) |
171 | #define IO_INTC_PRIORITY1 0x0542 | 171 | #define IO_INTC_PRIORITY1 DM320_REG(0x0542) |
172 | #define IO_INTC_PRIORITY2 0x0544 | 172 | #define IO_INTC_PRIORITY2 DM320_REG(0x0544) |
173 | #define IO_INTC_PRIORITY3 0x0546 | 173 | #define IO_INTC_PRIORITY3 DM320_REG(0x0546) |
174 | #define IO_INTC_PRIORITY4 0x0548 | 174 | #define IO_INTC_PRIORITY4 DM320_REG(0x0548) |
175 | #define IO_INTC_PRIORITY5 0x054A | 175 | #define IO_INTC_PRIORITY5 DM320_REG(0x054A) |
176 | #define IO_INTC_PRIORITY6 0x054C | 176 | #define IO_INTC_PRIORITY6 DM320_REG(0x054C) |
177 | #define IO_INTC_PRIORITY7 0x054E | 177 | #define IO_INTC_PRIORITY7 DM320_REG(0x054E) |
178 | #define IO_INTC_PRIORITY8 0x0550 | 178 | #define IO_INTC_PRIORITY8 DM320_REG(0x0550) |
179 | #define IO_INTC_PRIORITY9 0x0552 | 179 | #define IO_INTC_PRIORITY9 DM320_REG(0x0552) |
180 | #define IO_INTC_PRIORITY10 0x0554 | 180 | #define IO_INTC_PRIORITY10 DM320_REG(0x0554) |
181 | #define IO_INTC_PRIORITY11 0x0556 | 181 | #define IO_INTC_PRIORITY11 DM320_REG(0x0556) |
182 | #define IO_INTC_PRIORITY12 0x0558 | 182 | #define IO_INTC_PRIORITY12 DM320_REG(0x0558) |
183 | #define IO_INTC_PRIORITY13 0x055A | 183 | #define IO_INTC_PRIORITY13 DM320_REG(0x055A) |
184 | #define IO_INTC_PRIORITY14 0x055C | 184 | #define IO_INTC_PRIORITY14 DM320_REG(0x055C) |
185 | #define IO_INTC_PRIORITY15 0x055E | 185 | #define IO_INTC_PRIORITY15 DM320_REG(0x055E) |
186 | #define IO_INTC_PRIORITY16 0x0560 | 186 | #define IO_INTC_PRIORITY16 DM320_REG(0x0560) |
187 | #define IO_INTC_PRIORITY17 0x0562 | 187 | #define IO_INTC_PRIORITY17 DM320_REG(0x0562) |
188 | #define IO_INTC_PRIORITY18 0x0564 | 188 | #define IO_INTC_PRIORITY18 DM320_REG(0x0564) |
189 | #define IO_INTC_PRIORITY19 0x0566 | 189 | #define IO_INTC_PRIORITY19 DM320_REG(0x0566) |
190 | #define IO_INTC_PRIORITY20 0x0568 | 190 | #define IO_INTC_PRIORITY20 DM320_REG(0x0568) |
191 | #define IO_INTC_PRIORITY21 0x056A | 191 | #define IO_INTC_PRIORITY21 DM320_REG(0x056A) |
192 | #define IO_INTC_PRIORITY22 0x056C | 192 | #define IO_INTC_PRIORITY22 DM320_REG(0x056C) |
193 | 193 | ||
194 | /* GIO Controller */ | 194 | /* GIO Controller */ |
195 | #define IO_GIO_DIR0 0x0580 | 195 | #define IO_GIO_DIR0 DM320_REG(0x0580) |
196 | #define IO_GIO_DIR1 0x0582 | 196 | #define IO_GIO_DIR1 DM320_REG(0x0582) |
197 | #define IO_GIO_DIR2 0x0584 | 197 | #define IO_GIO_DIR2 DM320_REG(0x0584) |
198 | #define IO_GIO_INV0 0x0586 | 198 | #define IO_GIO_INV0 DM320_REG(0x0586) |
199 | #define IO_GIO_INV1 0x0588 | 199 | #define IO_GIO_INV1 DM320_REG(0x0588) |
200 | #define IO_GIO_INV2 0x058A | 200 | #define IO_GIO_INV2 DM320_REG(0x058A) |
201 | #define IO_GIO_BITSET0 0x058C | 201 | #define IO_GIO_BITSET0 DM320_REG(0x058C) |
202 | #define IO_GIO_BITSET1 0x058E | 202 | #define IO_GIO_BITSET1 DM320_REG(0x058E) |
203 | #define IO_GIO_BITSET2 0x0590 | 203 | #define IO_GIO_BITSET2 DM320_REG(0x0590) |
204 | #define IO_GIO_BITCLR0 0x0592 | 204 | #define IO_GIO_BITCLR0 DM320_REG(0x0592) |
205 | #define IO_GIO_BITCLR1 0x0594 | 205 | #define IO_GIO_BITCLR1 DM320_REG(0x0594) |
206 | #define IO_GIO_BITCLR2 0x0596 | 206 | #define IO_GIO_BITCLR2 DM320_REG(0x0596) |
207 | #define IO_GIO_IRQPORT 0x0598 | 207 | #define IO_GIO_IRQPORT DM320_REG(0x0598) |
208 | #define IO_GIO_IRQEDGE 0x059A | 208 | #define IO_GIO_IRQEDGE DM320_REG(0x059A) |
209 | #define IO_GIO_CHAT0 0x059C | 209 | #define IO_GIO_CHAT0 DM320_REG(0x059C) |
210 | #define IO_GIO_CHAT1 0x059E | 210 | #define IO_GIO_CHAT1 DM320_REG(0x059E) |
211 | #define IO_GIO_CHAT2 0x05A0 | 211 | #define IO_GIO_CHAT2 DM320_REG(0x05A0) |
212 | #define IO_GIO_NCHAT 0x05A2 | 212 | #define IO_GIO_NCHAT DM320_REG(0x05A2) |
213 | #define IO_GIO_FSEL0 0x05A4 | 213 | #define IO_GIO_FSEL0 DM320_REG(0x05A4) |
214 | #define IO_GIO_FSEL1 0x05A6 | 214 | #define IO_GIO_FSEL1 DM320_REG(0x05A6) |
215 | #define IO_GIO_FSEL2 0x05A8 | 215 | #define IO_GIO_FSEL2 DM320_REG(0x05A8) |
216 | #define IO_GIO_FSEL3 0x05AA | 216 | #define IO_GIO_FSEL3 DM320_REG(0x05AA) |
217 | #define IO_GIO_FSEL4 0x05AC | 217 | #define IO_GIO_FSEL4 DM320_REG(0x05AC) |
218 | #define IO_GIO_CARD_SET 0x05AE | 218 | #define IO_GIO_CARD_SET DM320_REG(0x05AE) |
219 | #define IO_GIO_CARD_ST 0x05B0 | 219 | #define IO_GIO_CARD_ST DM320_REG(0x05B0) |
220 | 220 | ||
221 | /* DSP Controller */ | 221 | /* DSP Controller */ |
222 | #define IO_DSPC_HPIB_CONTROL 0x0600 | 222 | #define IO_DSPC_HPIB_CONTROL 0x0600 |
@@ -707,10 +707,6 @@ | |||
707 | * Copyright (C) 1999 ARM Limited | 707 | * Copyright (C) 1999 ARM Limited |
708 | */ | 708 | */ |
709 | 709 | ||
710 | #define CONFIG_TIMER1_TMPRSCL 0x000A | ||
711 | #define CLOCK_TICK_RATE (CPUFREQ_MAX / CONFIG_TIMER1_TMPRSCL) | ||
712 | #define CONFIG_TIMER1_TMDIV (unsigned short)(CLOCK_TICK_RATE / HZ) | ||
713 | |||
714 | #define CONFIG_TIMER0_TMMD_STOP 0x0000 | 710 | #define CONFIG_TIMER0_TMMD_STOP 0x0000 |
715 | #define CONFIG_TIMER0_TMMD_ONE_SHOT 0x0001 | 711 | #define CONFIG_TIMER0_TMMD_ONE_SHOT 0x0001 |
716 | #define CONFIG_TIMER0_TMMD_FREE_RUN 0x0002 | 712 | #define CONFIG_TIMER0_TMMD_FREE_RUN 0x0002 |
diff --git a/firmware/target/arm/olympus/mrobe-500/ata-mr500.c b/firmware/target/arm/olympus/mrobe-500/ata-mr500.c index 171097f823..2b018194d2 100644 --- a/firmware/target/arm/olympus/mrobe-500/ata-mr500.c +++ b/firmware/target/arm/olympus/mrobe-500/ata-mr500.c | |||
@@ -62,6 +62,10 @@ void ata_device_init(void) | |||
62 | { | 62 | { |
63 | /* ATA reset */ | 63 | /* ATA reset */ |
64 | ATA_RESET_DISABLE; /* Set the pin to disable an active low reset */ | 64 | ATA_RESET_DISABLE; /* Set the pin to disable an active low reset */ |
65 | |||
66 | /* set GIO17 (ATA power) on and output */ | ||
67 | IO_GIO_BITSET1&=~(1<<1); | ||
68 | IO_GIO_DIR1&=~(1<<1); | ||
65 | } | 69 | } |
66 | 70 | ||
67 | #if !defined(BOOTLOADER) | 71 | #if !defined(BOOTLOADER) |
diff --git a/firmware/target/arm/olympus/mrobe-500/button-mr500.c b/firmware/target/arm/olympus/mrobe-500/button-mr500.c index 87ab80a5e5..7410875fd1 100644 --- a/firmware/target/arm/olympus/mrobe-500/button-mr500.c +++ b/firmware/target/arm/olympus/mrobe-500/button-mr500.c | |||
@@ -37,7 +37,7 @@ | |||
37 | void button_init_device(void) | 37 | void button_init_device(void) |
38 | { | 38 | { |
39 | /* GIO is the power button, set as input */ | 39 | /* GIO is the power button, set as input */ |
40 | outw(inw(IO_GIO_DIR0)|0x01, IO_GIO_DIR0); | 40 | IO_GIO_DIR0|=0x01; |
41 | } | 41 | } |
42 | 42 | ||
43 | inline bool button_hold(void) | 43 | inline bool button_hold(void) |
@@ -52,7 +52,7 @@ int button_read_device(void) | |||
52 | int i = 0; | 52 | int i = 0; |
53 | int btn = BUTTON_NONE, timeout = BUTTON_TIMEOUT; | 53 | int btn = BUTTON_NONE, timeout = BUTTON_TIMEOUT; |
54 | 54 | ||
55 | if ((inw(IO_GIO_BITSET0)&0x01) == 0) | 55 | if ((IO_GIO_BITSET0&0x01) == 0) |
56 | btn |= BUTTON_POWER; | 56 | btn |= BUTTON_POWER; |
57 | 57 | ||
58 | uartHeartbeat(); | 58 | uartHeartbeat(); |
diff --git a/firmware/target/arm/olympus/mrobe-500/crt0.S b/firmware/target/arm/olympus/mrobe-500/crt0.S index 672e917cc8..a7c1131367 100755 --- a/firmware/target/arm/olympus/mrobe-500/crt0.S +++ b/firmware/target/arm/olympus/mrobe-500/crt0.S | |||
@@ -102,7 +102,7 @@ start: | |||
102 | ldr sp, =irq_stack | 102 | ldr sp, =irq_stack |
103 | msr cpsr_c, #0xdb | 103 | msr cpsr_c, #0xdb |
104 | ldr sp, =irq_stack | 104 | ldr sp, =irq_stack |
105 | /* Switch to supervisor mode */ | 105 | /* Switch to supervisor mode (no IRQ) */ |
106 | msr cpsr_c, #0xd3 | 106 | msr cpsr_c, #0xd3 |
107 | ldr sp, =stackend | 107 | ldr sp, =stackend |
108 | 108 | ||
diff --git a/firmware/target/arm/olympus/mrobe-500/kernel-mr500.c b/firmware/target/arm/olympus/mrobe-500/kernel-mr500.c index 3ac0730691..487bc2d7d2 100644 --- a/firmware/target/arm/olympus/mrobe-500/kernel-mr500.c +++ b/firmware/target/arm/olympus/mrobe-500/kernel-mr500.c | |||
@@ -29,20 +29,22 @@ void tick_start(unsigned int interval_in_ms) | |||
29 | { | 29 | { |
30 | IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_STOP; | 30 | IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_STOP; |
31 | 31 | ||
32 | /* Setup the Prescalar */ | 32 | /* Setup the Prescalar (Divide by 10) |
33 | IO_TIMER1_TMPRSCL = CONFIG_TIMER1_TMPRSCL; | 33 | * Based on linux/include/asm-arm/arch-integrator/timex.h |
34 | */ | ||
35 | IO_TIMER1_TMPRSCL = 0x000A; | ||
34 | 36 | ||
35 | /* Setup the Divisor */ | 37 | /* Setup the Divisor */ |
36 | IO_TIMER1_TMDIV = CONFIG_TIMER1_TMDIV; | 38 | IO_TIMER1_TMDIV = (TIMER_FREQ / (10*1000))*interval_in_ms; |
37 | 39 | ||
38 | /* Turn Timer1 to Free Run mode */ | 40 | /* Turn Timer1 to Free Run mode */ |
39 | IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_FREE_RUN; | 41 | IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_FREE_RUN; |
40 | 42 | ||
41 | /* Enable the interrupt */ | 43 | /* Enable the interrupt */ |
42 | IO_INTC_EINT0 |= 1<<IRQ_TIMER1; | 44 | IO_INTC_EINT0 |= 1<<IRQ_TIMER1; |
43 | } | 45 | } |
44 | 46 | ||
45 | void TIMER4(void) | 47 | void TIMER1(void) |
46 | { | 48 | { |
47 | int i; | 49 | int i; |
48 | 50 | ||
diff --git a/firmware/target/arm/olympus/mrobe-500/spi-mr500.c b/firmware/target/arm/olympus/mrobe-500/spi-mr500.c index 8aeecd97f2..c47ab8f6ed 100644 --- a/firmware/target/arm/olympus/mrobe-500/spi-mr500.c +++ b/firmware/target/arm/olympus/mrobe-500/spi-mr500.c | |||
@@ -28,8 +28,8 @@ | |||
28 | #include "system.h" | 28 | #include "system.h" |
29 | 29 | ||
30 | #define GIO_TS_ENABLE (1<<2) | 30 | #define GIO_TS_ENABLE (1<<2) |
31 | #define clr_gio_enable() outw(GIO_TS_ENABLE, IO_GIO_BITSET1) | 31 | #define clr_gio_enable() IO_GIO_BITSET1=GIO_TS_ENABLE |
32 | #define set_gio_enable() outw(GIO_TS_ENABLE, IO_GIO_BITCLR1) | 32 | #define set_gio_enable() IO_GIO_BITCLR1=GIO_TS_ENABLE |
33 | 33 | ||
34 | int spi_block_transfer(const uint8_t *tx_bytes, unsigned int tx_size, | 34 | int spi_block_transfer(const uint8_t *tx_bytes, unsigned int tx_size, |
35 | uint8_t *rx_bytes, unsigned int rx_size) | 35 | uint8_t *rx_bytes, unsigned int rx_size) |
@@ -72,6 +72,6 @@ void spi_init(void) | |||
72 | IO_SERIAL0_TX_ENABLE = 0x0001; | 72 | IO_SERIAL0_TX_ENABLE = 0x0001; |
73 | 73 | ||
74 | /* Set GIO 18 to output for touch screen slave enable */ | 74 | /* Set GIO 18 to output for touch screen slave enable */ |
75 | outw(inw(IO_GIO_DIR1)&~GIO_TS_ENABLE, IO_GIO_DIR1); | 75 | IO_GIO_DIR1&=~GIO_TS_ENABLE; |
76 | clr_gio_enable(); | 76 | clr_gio_enable(); |
77 | } | 77 | } |
diff --git a/firmware/target/arm/olympus/mrobe-500/system-mr500.c b/firmware/target/arm/olympus/mrobe-500/system-mr500.c index 5b52dc3208..4fdfbd03c6 100644 --- a/firmware/target/arm/olympus/mrobe-500/system-mr500.c +++ b/firmware/target/arm/olympus/mrobe-500/system-mr500.c | |||
@@ -95,7 +95,7 @@ static const char * const irqname[] = | |||
95 | 95 | ||
96 | static void UIRQ(void) | 96 | static void UIRQ(void) |
97 | { | 97 | { |
98 | unsigned int offset = IO_INTC_IRQENTRY0; | 98 | unsigned int offset = (IO_INTC_IRQENTRY0>>2)-1; |
99 | panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]); | 99 | panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]); |
100 | } | 100 | } |
101 | 101 | ||
@@ -105,18 +105,13 @@ void irq_handler(void) | |||
105 | /* | 105 | /* |
106 | * Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c | 106 | * Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c |
107 | */ | 107 | */ |
108 | printf("INTERUPT!"); | 108 | |
109 | asm volatile ( | 109 | asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */ |
110 | "sub lr, lr, #4 \r\n" | 110 | "sub sp, sp, #8 \n"); /* Reserve stack */ |
111 | "stmfd sp!, {r0-r3, ip, lr} \r\n" | 111 | irqvector[(IO_INTC_IRQENTRY0>>2)-1](); |
112 | "mov r0, #0x00030000 \r\n" | 112 | asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */ |
113 | "ldr r0, [r0, #0x518] \r\n" | 113 | "ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */ |
114 | "ldr r1, =irqvector \r\n" | 114 | "subs pc, lr, #4 \n"); /* Return from FIQ */ |
115 | "ldr r1, [r1, r0, lsl #2] \r\n" | ||
116 | "mov lr, pc \r\n" | ||
117 | "bx r1 \r\n" | ||
118 | "ldmfd sp!, {r0-r3, ip, pc}^ \r\n" | ||
119 | ); | ||
120 | } | 115 | } |
121 | 116 | ||
122 | void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked)); | 117 | void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked)); |
@@ -144,6 +139,11 @@ void system_reboot(void) | |||
144 | 139 | ||
145 | } | 140 | } |
146 | 141 | ||
142 | void enable_interrupts (void) | ||
143 | { | ||
144 | asm volatile ("msr cpsr_c, #0x13" ); | ||
145 | } | ||
146 | |||
147 | void system_init(void) | 147 | void system_init(void) |
148 | { | 148 | { |
149 | /* taken from linux/arch/arm/mach-itdm320-20/irq.c */ | 149 | /* taken from linux/arch/arm/mach-itdm320-20/irq.c */ |
@@ -166,6 +166,12 @@ void system_init(void) | |||
166 | IO_INTC_FISEL0 = 0; | 166 | IO_INTC_FISEL0 = 0; |
167 | IO_INTC_FISEL1 = 0; | 167 | IO_INTC_FISEL1 = 0; |
168 | IO_INTC_FISEL2 = 0; | 168 | IO_INTC_FISEL2 = 0; |
169 | |||
170 | /* set GIO26 (reset pin) to output and low */ | ||
171 | IO_GIO_BITSET1&=~(1<<10); | ||
172 | IO_GIO_DIR1&=~(1<<10); | ||
173 | |||
174 | enable_interrupts(); | ||
169 | } | 175 | } |
170 | 176 | ||
171 | int system_memory_guard(int newmode) | 177 | int system_memory_guard(int newmode) |
diff --git a/firmware/target/arm/olympus/mrobe-500/timer-target.h b/firmware/target/arm/olympus/mrobe-500/timer-target.h index 71cfa72e9d..4abe75ad82 100644 --- a/firmware/target/arm/olympus/mrobe-500/timer-target.h +++ b/firmware/target/arm/olympus/mrobe-500/timer-target.h | |||
@@ -20,7 +20,7 @@ | |||
20 | #define TIMER_TARGET_H | 20 | #define TIMER_TARGET_H |
21 | 21 | ||
22 | /* timer is based on PCLK and minimum division is 2 */ | 22 | /* timer is based on PCLK and minimum division is 2 */ |
23 | #define TIMER_FREQ (49156800/2) | 23 | #define TIMER_FREQ (27000000) |
24 | 24 | ||
25 | bool __timer_set(long cycles, bool set); | 25 | bool __timer_set(long cycles, bool set); |
26 | bool __timer_register(void); | 26 | bool __timer_register(void); |
diff --git a/firmware/target/arm/olympus/mrobe-500/uart-mr500.c b/firmware/target/arm/olympus/mrobe-500/uart-mr500.c index f8208f8717..99cf0f2d36 100644 --- a/firmware/target/arm/olympus/mrobe-500/uart-mr500.c +++ b/firmware/target/arm/olympus/mrobe-500/uart-mr500.c | |||
@@ -22,21 +22,7 @@ | |||
22 | #include "system.h" | 22 | #include "system.h" |
23 | 23 | ||
24 | /* UART 0/1 */ | 24 | /* UART 0/1 */ |
25 | #define IO_UART0_DTRR 0x0300 | ||
26 | #define IO_UART0_BRSR 0x0302 | ||
27 | #define IO_UART0_MSR 0x0304 | ||
28 | #define IO_UART0_RFCR 0x0306 | ||
29 | #define IO_UART0_TFCR 0x0308 | ||
30 | #define IO_UART0_LCR 0x030A | ||
31 | #define IO_UART0_SR 0x030C | ||
32 | 25 | ||
33 | #define IO_UART1_DTRR 0x0380 | ||
34 | #define IO_UART1_BRSR 0x0382 | ||
35 | #define IO_UART1_MSR 0x0384 | ||
36 | #define IO_UART1_RFCR 0x0386 | ||
37 | #define IO_UART1_TFCR 0x0388 | ||
38 | #define IO_UART1_LCR 0x038A | ||
39 | #define IO_UART1_SR 0x038C | ||
40 | #define CONFIG_UART_BRSR 87 | 26 | #define CONFIG_UART_BRSR 87 |
41 | 27 | ||
42 | void do_checksums(char *data, int len, char *xor, char *add) | 28 | void do_checksums(char *data, int len, char *xor, char *add) |
@@ -53,16 +39,16 @@ void do_checksums(char *data, int len, char *xor, char *add) | |||
53 | 39 | ||
54 | void uartSetup(void) { | 40 | void uartSetup(void) { |
55 | // 8-N-1 | 41 | // 8-N-1 |
56 | outw(0x8000, IO_UART1_MSR); | 42 | IO_UART1_MSR=0x8000; |
57 | outw(CONFIG_UART_BRSR, IO_UART1_BRSR); | 43 | IO_UART1_BRSR=CONFIG_UART_BRSR; |
58 | } | 44 | } |
59 | 45 | ||
60 | void uartPutc(char ch) { | 46 | void uartPutc(char ch) { |
61 | // Wait for room in FIFO | 47 | // Wait for room in FIFO |
62 | while ((inw(IO_UART1_TFCR) & 0x3f) >= 0x20); | 48 | while ((IO_UART1_TFCR & 0x3f) >= 0x20); |
63 | 49 | ||
64 | // Write character | 50 | // Write character |
65 | outw(ch, IO_UART1_DTRR); | 51 | IO_UART1_DTRR=ch; |
66 | } | 52 | } |
67 | 53 | ||
68 | // Unsigned integer to ASCII hexadecimal conversion | 54 | // Unsigned integer to ASCII hexadecimal conversion |
@@ -88,17 +74,17 @@ void uartGets(char *str, unsigned int size) { | |||
88 | char ch; | 74 | char ch; |
89 | 75 | ||
90 | // Wait for FIFO to contain something | 76 | // Wait for FIFO to contain something |
91 | while ((inw(IO_UART1_RFCR) & 0x3f) == 0); | 77 | while ((IO_UART1_RFCR & 0x3f) == 0); |
92 | 78 | ||
93 | // Read character | 79 | // Read character |
94 | ch = (char)inw(IO_UART1_DTRR); | 80 | ch = (char)IO_UART1_DTRR; |
95 | 81 | ||
96 | // Echo character back | 82 | // Echo character back |
97 | outw(ch, IO_UART1_DTRR); | 83 | IO_UART1_DTRR=ch; |
98 | 84 | ||
99 | // If CR, also echo LF, null-terminate, and return | 85 | // If CR, also echo LF, null-terminate, and return |
100 | if (ch == '\r') { | 86 | if (ch == '\r') { |
101 | outw('\n', IO_UART1_DTRR); | 87 | IO_UART1_DTRR='\n'; |
102 | if (size) { | 88 | if (size) { |
103 | *str++ = '\0'; | 89 | *str++ = '\0'; |
104 | } | 90 | } |
@@ -115,8 +101,8 @@ void uartGets(char *str, unsigned int size) { | |||
115 | 101 | ||
116 | int uartPollch(unsigned int ticks) { | 102 | int uartPollch(unsigned int ticks) { |
117 | while (ticks--) { | 103 | while (ticks--) { |
118 | if (inw(IO_UART1_RFCR) & 0x3f) { | 104 | if (IO_UART1_RFCR & 0x3f) { |
119 | return inw(IO_UART1_DTRR) & 0xff; | 105 | return IO_UART1_DTRR & 0xff; |
120 | } | 106 | } |
121 | } | 107 | } |
122 | 108 | ||
@@ -125,7 +111,7 @@ int uartPollch(unsigned int ticks) { | |||
125 | 111 | ||
126 | bool uartAvailable(void) | 112 | bool uartAvailable(void) |
127 | { | 113 | { |
128 | return (inw(IO_UART1_RFCR) & 0x3f)?true:false; | 114 | return (IO_UART1_RFCR & 0x3f)?true:false; |
129 | } | 115 | } |
130 | 116 | ||
131 | void uartHeartbeat(void) | 117 | void uartHeartbeat(void) |