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author | Karl Kurbjun <kkurbjun@gmail.com> | 2011-02-06 20:17:15 +0000 |
---|---|---|
committer | Karl Kurbjun <kkurbjun@gmail.com> | 2011-02-06 20:17:15 +0000 |
commit | 9a8ff746f2c08493578c18bc3b0b63de4c07bf92 (patch) | |
tree | ca7a80c77e7f047f32611be7824cb23bc6e31069 | |
parent | 924121005083bf6f07f877dfc6eb6c0e2908316d (diff) | |
download | rockbox-9a8ff746f2c08493578c18bc3b0b63de4c07bf92.tar.gz rockbox-9a8ff746f2c08493578c18bc3b0b63de4c07bf92.zip |
DM320: Update boot linker script (right now it is linked against flash). Include board initialization for M:Robe 500.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29225 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/SOURCES | 1 | ||||
-rw-r--r-- | firmware/target/arm/tms320dm320/boot.lds | 159 | ||||
-rw-r--r-- | firmware/target/arm/tms320dm320/mrobe-500/crt0-board.S | 313 |
3 files changed, 407 insertions, 66 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES index 303c080c97..ae0c8a4f20 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES | |||
@@ -1003,6 +1003,7 @@ target/arm/ata-as-arm.S | |||
1003 | target/arm/lcd-as-memframe.S | 1003 | target/arm/lcd-as-memframe.S |
1004 | #endif | 1004 | #endif |
1005 | target/arm/mmu-arm.S | 1005 | target/arm/mmu-arm.S |
1006 | target/arm/tms320dm320/mrobe-500/crt0-board.S | ||
1006 | target/arm/tms320dm320/mrobe-500/adc-mr500.c | 1007 | target/arm/tms320dm320/mrobe-500/adc-mr500.c |
1007 | target/arm/tms320dm320/mrobe-500/ata-mr500.c | 1008 | target/arm/tms320dm320/mrobe-500/ata-mr500.c |
1008 | target/arm/tms320dm320/mrobe-500/backlight-mr500.c | 1009 | target/arm/tms320dm320/mrobe-500/backlight-mr500.c |
diff --git a/firmware/target/arm/tms320dm320/boot.lds b/firmware/target/arm/tms320dm320/boot.lds index 11fc79c24a..2b9f345a23 100644 --- a/firmware/target/arm/tms320dm320/boot.lds +++ b/firmware/target/arm/tms320dm320/boot.lds | |||
@@ -1,6 +1,6 @@ | |||
1 | #include "config.h" | 1 | #include "config.h" |
2 | 2 | ||
3 | ENTRY(start) | 3 | ENTRY(_vectors) |
4 | 4 | ||
5 | OUTPUT_FORMAT(elf32-littlearm) | 5 | OUTPUT_FORMAT(elf32-littlearm) |
6 | OUTPUT_ARCH(arm) | 6 | OUTPUT_ARCH(arm) |
@@ -27,15 +27,19 @@ STARTUP(target/arm/tms320dm320/crt0.o) | |||
27 | */ | 27 | */ |
28 | #define LCD_TTB_AREA 0x100000*((LCD_BUFFER_SIZE>>19)+1) | 28 | #define LCD_TTB_AREA 0x100000*((LCD_BUFFER_SIZE>>19)+1) |
29 | 29 | ||
30 | #define BOOT_OFFSET 0x1000000 | 30 | /* Bootloader only uses/knows about the upper 32 M */ |
31 | #define DRAMORIG 0x02900000 | ||
32 | #define DRAMSIZE (MEMORYSIZE * 0x80000) | ||
31 | 33 | ||
32 | #define DRAMSIZE (MEMORYSIZE * 0x100000) - BOOT_OFFSET | ||
33 | |||
34 | #define DRAMORIG (0x00900000+BOOT_OFFSET) /* actually it's 0x00900000 */ | ||
35 | #define IRAMORIG 0x00000000 | 34 | #define IRAMORIG 0x00000000 |
36 | #define IRAMSIZE 0x4000 | 35 | #define IRAMSIZE 0x4000 |
36 | |||
37 | #define FLASHORIG 0x00100000 | 37 | #define FLASHORIG 0x00100000 |
38 | #define FLASHSIZE 8M | 38 | #define FLASHSIZE 0x00800000 |
39 | |||
40 | PRO_STACK_SIZE = 0x2000; | ||
41 | IRQ_STACK_SIZE = 0x400; | ||
42 | FIQ_STACK_SIZE = 0x400; | ||
39 | 43 | ||
40 | /* End of the audio buffer, where the codec buffer starts */ | 44 | /* End of the audio buffer, where the codec buffer starts */ |
41 | #define TTB_BEGIN (DRAMORIG + DRAMSIZE - LCD_TTB_AREA) | 45 | #define TTB_BEGIN (DRAMORIG + DRAMSIZE - LCD_TTB_AREA) |
@@ -49,98 +53,121 @@ MEMORY | |||
49 | 53 | ||
50 | SECTIONS | 54 | SECTIONS |
51 | { | 55 | { |
52 | . = DRAMORIG; | 56 | /* Set up variables needed for memory initialization */ |
57 | _sdram_start = DRAMORIG; | ||
58 | _sdram_sizem = (DRAMSIZE / 0x100000); | ||
59 | |||
60 | _flash_start = FLASHORIG; | ||
61 | _flash_sizem = (FLASHSIZE / 0x100000); | ||
62 | |||
63 | .vectors : | ||
64 | { | ||
65 | _vectorsstart = .; | ||
66 | KEEP(*(.vectors)) | ||
67 | _vectorsend = .; | ||
68 | } > IRAM AT> FLASH | ||
69 | _vectorscopy = LOADADDR(.vectors); | ||
53 | 70 | ||
54 | .text : { | 71 | /* crt0.S initialization */ |
55 | loadaddress = .; | 72 | .init : |
73 | { | ||
74 | . = ALIGN(0x4); | ||
56 | _loadaddress = .; | 75 | _loadaddress = .; |
57 | *(.init.text) | 76 | *(.init) |
58 | *(.text*) | 77 | } > FLASH |
59 | *(.glue_7) | 78 | |
60 | *(.glue_7t) | 79 | /* Program code */ |
80 | .text : | ||
81 | { | ||
61 | . = ALIGN(0x4); | 82 | . = ALIGN(0x4); |
62 | } > DRAM | 83 | *(.text*) |
84 | } > FLASH | ||
63 | 85 | ||
86 | /* Thumb interworking sections - for some reason LD dies even if these | ||
87 | * sections are empty. | ||
88 | */ | ||
89 | .glue : | ||
90 | { | ||
91 | . = ALIGN(0x4); | ||
92 | *(.glue_7) /* ARM calling Thumb */ | ||
93 | *(.glue_7t) /* Thumb calling ARM */ | ||
94 | } > FLASH | ||
95 | |||
96 | /* Read-only data */ | ||
64 | .rodata : | 97 | .rodata : |
65 | { | 98 | { |
66 | *(.rodata) /* problems without this, dunno why */ | ||
67 | *(.rodata*) | ||
68 | *(.rodata.str1.1) | ||
69 | *(.rodata.str1.4) | ||
70 | . = ALIGN(0x4); | 99 | . = ALIGN(0x4); |
100 | *(.rodata*) | ||
101 | } > FLASH | ||
71 | 102 | ||
72 | /* Pseudo-allocate the copies of the data sections */ | 103 | /* Dynamic data - this needs to be copied out of flash before it is used. */ |
73 | _datacopy = .; | 104 | .data : |
74 | } > DRAM | 105 | { |
75 | 106 | . = ALIGN(0x4); | |
76 | .data : { | 107 | _dramstart = .; |
77 | *(.data*) | 108 | *(.data*) |
109 | _dramend = .; | ||
110 | } > DRAM AT> FLASH | ||
111 | _dramcopy = LOADADDR(.data); | ||
112 | |||
113 | .bss (NOLOAD) : | ||
114 | { | ||
78 | . = ALIGN(0x4); | 115 | . = ALIGN(0x4); |
79 | _dataend = . ; | 116 | _bss_start = .; |
117 | *(.bss*) | ||
118 | *(COMMON) | ||
119 | _bss_end = .; | ||
80 | } > DRAM | 120 | } > DRAM |
81 | 121 | ||
82 | .vectors IRAMORIG : | ||
83 | { | ||
84 | _vectorsstart = .; | ||
85 | KEEP(*(.resetvectors)); | ||
86 | *(.resetvectors); | ||
87 | KEEP(*(.vectors)); | ||
88 | *(.vectors); | ||
89 | _vectorsend = .; | ||
90 | } > IRAM AT > DRAM | ||
91 | _vectorscopy = LOADADDR(.vectors); | ||
92 | |||
93 | .iram : | 122 | .iram : |
94 | { | 123 | { |
124 | . = ALIGN(0x4); | ||
95 | _iramstart = .; | 125 | _iramstart = .; |
96 | *(.icode) | 126 | *(.icode) |
97 | *(.irodata*) | 127 | *(.irodata) |
98 | *(.idata) | 128 | *(.idata) |
99 | . = ALIGN(0x4); | ||
100 | _iramend = .; | 129 | _iramend = .; |
101 | } > IRAM AT> DRAM | 130 | } > IRAM AT> FLASH |
102 | 131 | ||
103 | _iramcopy = LOADADDR(.iram); | 132 | _iramcopy = LOADADDR(.iram); |
104 | 133 | ||
105 | .ibss (NOLOAD) : | 134 | .ibss (NOLOAD) : |
106 | { | 135 | { |
107 | _iedata = .; | ||
108 | *(.ibss) | ||
109 | . = ALIGN(0x4); | 136 | . = ALIGN(0x4); |
110 | _iend = .; | 137 | _ibss_start = .; |
138 | *(.ibss) | ||
139 | _ibss_end = .; | ||
111 | } > IRAM | 140 | } > IRAM |
112 | 141 | ||
113 | .stack (NOLOAD) : | 142 | /* Program stack space */ |
114 | { | 143 | .pro_stack (NOLOAD): |
115 | *(.stack) | ||
116 | stackbegin = .; | ||
117 | . += 0x2000; | ||
118 | stackend = .; | ||
119 | } > IRAM | ||
120 | |||
121 | .irqstack (NOLOAD) : | ||
122 | { | 144 | { |
123 | *(.stack) | 145 | . = ALIGN(0x4); |
124 | . += 0x400; | 146 | *(.stack) |
125 | irq_stack = .; | 147 | stackbegin = .; /* Variable for thread.c */ |
148 | _pro_stack_end = .; | ||
149 | . += PRO_STACK_SIZE; | ||
150 | _pro_stack_start = .; | ||
151 | stackend = .; /* Variable for tread.c */ | ||
126 | } > IRAM | 152 | } > IRAM |
127 | 153 | ||
128 | .fiqstack (NOLOAD) : | 154 | /* IRQ stack space */ |
155 | .irq_stack (NOLOAD): | ||
129 | { | 156 | { |
130 | *(.stack) | 157 | . = ALIGN(0x4); |
131 | . += 0x100; | 158 | _irq_stack_end = .; |
132 | fiq_stack = .; | 159 | . += IRQ_STACK_SIZE; |
160 | _irq_stack_start = .; | ||
133 | } > IRAM | 161 | } > IRAM |
134 | 162 | ||
135 | .bss (NOLOAD) : | 163 | /* FIQ stack space */ |
164 | .fiq_stack (NOLOAD): | ||
136 | { | 165 | { |
137 | . = ADDR(.data) + SIZEOF(.data) + SIZEOF(.vectors) + SIZEOF(.iram); | ||
138 | _edata = .; | ||
139 | *(.bss*) | ||
140 | *(COMMON) | ||
141 | . = ALIGN(0x4); | 166 | . = ALIGN(0x4); |
142 | _end = .; | 167 | _fiq_stack_end = .; |
143 | } > DRAM | 168 | . += FIQ_STACK_SIZE; |
169 | _fiq_stack_start = .; | ||
170 | } > IRAM | ||
144 | 171 | ||
145 | .ttbtable TTB_BEGIN (NOLOAD) : | 172 | .ttbtable TTB_BEGIN (NOLOAD) : |
146 | { | 173 | { |
diff --git a/firmware/target/arm/tms320dm320/mrobe-500/crt0-board.S b/firmware/target/arm/tms320dm320/mrobe-500/crt0-board.S new file mode 100644 index 0000000000..ace04df847 --- /dev/null +++ b/firmware/target/arm/tms320dm320/mrobe-500/crt0-board.S | |||
@@ -0,0 +1,313 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id: $ | ||
9 | * | ||
10 | * Copyright (C) 2010 by Karl Kurbjun | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include "config.h" | ||
22 | #include "cpu.h" | ||
23 | |||
24 | #define SDRAM_MODE 0x9B00 | ||
25 | |||
26 | /* Macro for reading a register */ | ||
27 | .macro mrh register | ||
28 | ldr r1, =\register | ||
29 | ldrh r0, [r1] | ||
30 | .endm | ||
31 | |||
32 | /* Macro for writing a register */ | ||
33 | .macro mwh register, value | ||
34 | ldr r0, =\value | ||
35 | ldr r1, =\register | ||
36 | strh r0, [r1] | ||
37 | .endm | ||
38 | |||
39 | /* This version uses a mov to save on the literal pool size. Otherwise it is | ||
40 | * functionally equivalent. | ||
41 | */ | ||
42 | .macro mwhm register, value | ||
43 | mov r0, #\value | ||
44 | ldr r1, =\register | ||
45 | strh r0, [r1] | ||
46 | .endm | ||
47 | |||
48 | /****************************************************************************** | ||
49 | * _init_board: * | ||
50 | * This function initializes the specific baord this SoC is on. * | ||
51 | ******************************************************************************/ | ||
52 | .section .init, "ax" | ||
53 | .code 32 | ||
54 | .align 0x04 | ||
55 | .global _init_board | ||
56 | .type _init_board, %function | ||
57 | |||
58 | _init_board: | ||
59 | |||
60 | /* Setup the EMIF interface timings */ | ||
61 | |||
62 | /* FLASH interface: | ||
63 | * These are based on the OF setup | ||
64 | */ | ||
65 | /* IO_EMIF_CS0CTRL1 and | ||
66 | * IO_EMIF_CS0CTRL2 | ||
67 | */ | ||
68 | mwh 0x30A00, 0x4488 | ||
69 | mwh 0x30A02, 0x1220 | ||
70 | |||
71 | /* ATA interface: | ||
72 | * These are based on the OF setup | ||
73 | */ | ||
74 | /* IO_EMIF_CS3CTRL1 and | ||
75 | * IO_EMIF_CS3CTRL2 | ||
76 | */ | ||
77 | mwh 0x30A10, 0x77EF | ||
78 | mwh 0x30A12, 0x5220 | ||
79 | |||
80 | /* USB interface: | ||
81 | * The following EMIF timing values are from the OF: | ||
82 | * IO_EMIF_CS4CTRL1 = 0x66AB; | ||
83 | * IO_EMIF_CS4CTRL2 = 0x4220; | ||
84 | * | ||
85 | * More agressive numbers may be possible, but it depends on the clocking | ||
86 | * setup. | ||
87 | */ | ||
88 | /* IO_EMIF_CS4CTRL1 and | ||
89 | * IO_EMIF_CS4CTRL2 | ||
90 | */ | ||
91 | mwh 0x30A14, 0x66AB | ||
92 | mwh 0x30A16, 0x4220 | ||
93 | |||
94 | /* IO_EMIF_BUSCTRL */ | ||
95 | mwh 0x30A18, 0x0001 | ||
96 | |||
97 | _clock_setup: | ||
98 | /* Clock initialization */ | ||
99 | /* Used for ES10 and unknown, slower clocks, but also uses more power | ||
100 | * due to PLL setup and slow ARM clock speed. | ||
101 | */ | ||
102 | |||
103 | /* IO_CLK_BYP: Bypass the PLLs for the following changes */ | ||
104 | mwh 0x30894, 0x1111 | ||
105 | |||
106 | /* 27 MHz input clock: | ||
107 | * IO_CLK_PLLA = 27 * 11 / 1 = 297 MHz | ||
108 | * IO_CLK_PLLB = 27 * 13 / 1 = 351 MHz | ||
109 | */ | ||
110 | mwh 0x30880, 0x10A0 | ||
111 | mwh 0x30882, 0x10C0 | ||
112 | |||
113 | /* IO_CLK_SEL0: VLNQ is fed by PLLB, I2C from M48XI, MS from PLLA */ | ||
114 | mwh 0x30884, 0x17E | ||
115 | |||
116 | /* IO_CLK_SEL1: VENC = MXI CLK, PLLA, PCLK, nodiv2 */ | ||
117 | mwhm 0x30886, 0x1000 | ||
118 | |||
119 | # IO_CLK_SEL2: ARM and AXL are from PLLB, SDRAM and DSP are PLLA */ | ||
120 | mwh 0x30888, 0x1001 | ||
121 | |||
122 | /* IO_CLK_DIV0: Set the slow clock speed for the ARM/AHB | ||
123 | * Slow Setup: | ||
124 | * ARM div = 4 ( 87.5 MHz ) | ||
125 | * AHB div = 1 ( 87.5 MHz ) | ||
126 | */ | ||
127 | mwh 0x3088A, 0x0003 /* OF sets this to 0x0103 */ | ||
128 | |||
129 | /* IO_CLK_DIV1: | ||
130 | * SDRAM div= 3 ( 99 MHz ) | ||
131 | * AXL div = 2 ( 175 MHz ) | ||
132 | */ | ||
133 | mwh 0x3088C, 0x0102 /* OF sets this to 0x0103 */ | ||
134 | |||
135 | /* IO_CLK_DIV2: | ||
136 | * MS div = 32 ( ~9 MHz ) | ||
137 | * DSP div = 3 ( 99 MHz ) | ||
138 | */ | ||
139 | mwh 0x3088E, 0x020E | ||
140 | |||
141 | /* IO_CLK_DIV3: (this comment is incorrect, (31 << 8) | 255;) | ||
142 | * MMC div = 256 ( slow ) | ||
143 | * VENC div = 32 ( 843.75 KHz ) | ||
144 | */ | ||
145 | mwhm 0x30890, 0x0003 | ||
146 | |||
147 | /* IO_CLK_DIV4: (this comment is incorrect, (31 << 8) | 0;) | ||
148 | * I2C div = 1 (48 MHz if M48XI is running) | ||
149 | * VLNQ div = 32 | ||
150 | */ | ||
151 | mwhm 0x30892, 0x0200 | ||
152 | |||
153 | # PLLA &= ~0x1000 (BIC #0x1000) | ||
154 | mrh 0x30880 | ||
155 | bic r0, r0, #0x1000 | ||
156 | strh r0, [r1] | ||
157 | |||
158 | # PLLB &= ~0x1000 | ||
159 | mrh 0x30882 | ||
160 | bic r0, r0, #0x1000 | ||
161 | strh r0, [r1] | ||
162 | |||
163 | /* Wait for PLLs to lock before feeding them to the downstream devices */ | ||
164 | _plla_wait: | ||
165 | mrh 0x30880 | ||
166 | bic r0, r0, #0x7F | ||
167 | tst r0, r0 | ||
168 | beq _plla_wait | ||
169 | |||
170 | _pllb_wait: | ||
171 | mrh 0x30882 | ||
172 | bic r0, r0, #0x7F | ||
173 | tst r0, r0 | ||
174 | beq _plla_wait | ||
175 | |||
176 | /* IO_CLK_BYP: Enable PLL feeds */ | ||
177 | mwhm 0x30894, 0x0 | ||
178 | |||
179 | /* IO_CLK_MOD0: Most off */ | ||
180 | mwh 0x30898, 0x0167 | ||
181 | |||
182 | /* IO_CLK_MOD1: All off */ | ||
183 | mwhm 0x3089A, 0x0 | ||
184 | |||
185 | /* IO_CLK_MOD2: Turn on the GPIO clock */ | ||
186 | mwhm 0x3089C, 0x20 | ||
187 | |||
188 | /* Setup the SDRAM range on the AHB bus */ | ||
189 | /* SDRAMSA */ | ||
190 | mov r0, #0x60000 | ||
191 | mov r1, #0x900000 | ||
192 | str r1, [r0, #0xF00] | ||
193 | |||
194 | /* SDRAMEA: 64MB */ | ||
195 | mov r1, #0x4900000 | ||
196 | str r1, [r0, #0xF04] | ||
197 | |||
198 | /* BUSCTRL */ | ||
199 | mov r1, #0x00000 | ||
200 | str r1, [r0, #0xF08] | ||
201 | |||
202 | /* USBCTRL */ | ||
203 | str r1, [r0, #0xF20] | ||
204 | |||
205 | /* Setup IO_SDRAM_SDMODE based on OF */ | ||
206 | mov r1, #0x00030000 | ||
207 | orr r1, r1, #0x900 | ||
208 | |||
209 | /* Pre-charge all banks */ | ||
210 | ldr r0, =(SDRAM_MODE | 0x82) | ||
211 | strh r0, [r1, #0xA6] | ||
212 | |||
213 | /* Setup auto refresh, OF uses 0x5F */ | ||
214 | ldr r0, =0x140 | ||
215 | strh r0, [r1, #0xA8] | ||
216 | |||
217 | /* Issue 8 auto refresh cycles */ | ||
218 | ldr r0, =(SDRAM_MODE | 0x84) | ||
219 | strh r0, [r1, #0xA6] | ||
220 | strh r0, [r1, #0xA6] | ||
221 | strh r0, [r1, #0xA6] | ||
222 | strh r0, [r1, #0xA6] | ||
223 | strh r0, [r1, #0xA6] | ||
224 | strh r0, [r1, #0xA6] | ||
225 | strh r0, [r1, #0xA6] | ||
226 | strh r0, [r1, #0xA6] | ||
227 | |||
228 | /* Set the mode register */ | ||
229 | ldr r0, =(SDRAM_MODE | 0x81) | ||
230 | strh r0, [r1, #0xA6] | ||
231 | |||
232 | /* Go back to the NOP state */ | ||
233 | ldr r0, =(SDRAM_MODE | 0x80) | ||
234 | strh r0, [r1, #0xA6] | ||
235 | |||
236 | /* Turn on auto power down */ | ||
237 | ldr r0, =(SDRAM_MODE | 0x40) | ||
238 | strh r0, [r1, #0xA6] | ||
239 | |||
240 | /* Go through the GPIO initialization */ | ||
241 | /* IO_GIO_FSEL0: Set up the GPIO pin functions 0-16 */ | ||
242 | mwh 0x305A4, 0x0000 | ||
243 | |||
244 | /* IO_GIO_FSEL1: 17-24 */ | ||
245 | mwh 0x305A6, 0x0000 | ||
246 | |||
247 | /* IO_GIO_FSEL2: 18-32 */ | ||
248 | mwh 0x305A8, 0x1450 | ||
249 | |||
250 | /* IO_GIO_FSEL3: 33-40 */ | ||
251 | mwh 0x305AA, 0x0404 | ||
252 | |||
253 | /* IO_GIO_DIR0 */ | ||
254 | mwh 0x30580, 0x6A0B | ||
255 | |||
256 | /* IO_GIO_DIR1: Important note - pin 26 has control over the system power. | ||
257 | * If this pin is not initialized the device will shut off immediately. | ||
258 | */ | ||
259 | mwh 0x30582, 0x8B00 | ||
260 | |||
261 | /* IO_GIO_DIR2 */ | ||
262 | mwh 0x30584, 0x0000 | ||
263 | |||
264 | /* IO_GIO_INV0 */ | ||
265 | mwh 0x30586, 0x0000 | ||
266 | |||
267 | /* IO_GIO_INV1 */ | ||
268 | mwh 0x30588, 0x0000 | ||
269 | |||
270 | /* IO_GIO_INV2 */ | ||
271 | mwh 0x3058A, 0x0000 | ||
272 | |||
273 | /* IO_GIO_BITCLR0 */ | ||
274 | mwh 0x30592, 0xFFFF | ||
275 | |||
276 | /* IO_GIO_BITCLR1 */ | ||
277 | mwh 0x30594, 0xFFFF | ||
278 | |||
279 | /* IO_GIO_BITCLR2 */ | ||
280 | mwh 0x30596, 0xFFFF | ||
281 | |||
282 | /* IO_GIO_BITSET0 */ | ||
283 | mwh 0x3058C, 0x0280 | ||
284 | |||
285 | /* IO_GIO_BITSET1 */ | ||
286 | mwh 0x3058E, 0x2066 | ||
287 | |||
288 | /* IO_GIO_BITSET2 */ | ||
289 | mwh 0x30590, 0x0025 | ||
290 | |||
291 | /* IO_GIO_IRQPORT */ | ||
292 | mwh 0x30598, 0xD60B | ||
293 | |||
294 | /* IO_GIO_IRQEDGE */ | ||
295 | mwh 0x3059A, 0x0801 | ||
296 | |||
297 | /* IO_GIO_CHAT0 */ | ||
298 | mwh 0x3059C, 0x0000 | ||
299 | |||
300 | /* IO_GIO_CHAT1 */ | ||
301 | mwh 0x3059E, 0x0000 | ||
302 | |||
303 | /* IO_GIO_CHAT2 */ | ||
304 | mwh 0x305A0, 0x0000 | ||
305 | |||
306 | /* IO_GIO_NCHAT */ | ||
307 | mwh 0x305A2, 0x0000 | ||
308 | |||
309 | bx lr | ||
310 | |||
311 | .ltorg | ||
312 | .size _init_board, .-_init_board | ||
313 | |||