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author | Rafaël Carré <rafael.carre@gmail.com> | 2010-04-13 15:17:08 +0000 |
---|---|---|
committer | Rafaël Carré <rafael.carre@gmail.com> | 2010-04-13 15:17:08 +0000 |
commit | 96e97987d9ac962380573de29ab70554da8cd64b (patch) | |
tree | b8adc295133573505a3f8b07e9f3e7f6fea13864 | |
parent | 4205a508d70be4d3776697327eba2d925bb3eb3b (diff) | |
download | rockbox-96e97987d9ac962380573de29ab70554da8cd64b.tar.gz rockbox-96e97987d9ac962380573de29ab70554da8cd64b.zip |
mmu-arm.S: disable MMU functions on CPUs which don't use them
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25629 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/target/arm/mmu-arm.S | 40 |
1 files changed, 28 insertions, 12 deletions
diff --git a/firmware/target/arm/mmu-arm.S b/firmware/target/arm/mmu-arm.S index 9a41b956a5..9e2100af28 100644 --- a/firmware/target/arm/mmu-arm.S +++ b/firmware/target/arm/mmu-arm.S | |||
@@ -24,16 +24,26 @@ | |||
24 | /* Used by ARMv4 & ARMv5 CPUs with cp15 register and MMU */ | 24 | /* Used by ARMv4 & ARMv5 CPUs with cp15 register and MMU */ |
25 | /* WARNING : assume size of a data cache line == 32 bytes */ | 25 | /* WARNING : assume size of a data cache line == 32 bytes */ |
26 | 26 | ||
27 | #if CONFIG_CPU == TCC7801 || CONFIG_CPU == AT91SAM9260 \ | 27 | #if CONFIG_CPU == TCC7801 || CONFIG_CPU == AT91SAM9260 |
28 | || CONFIG_CPU == DM320 || CONFIG_CPU == AS3525v2 | 28 | /* MMU present but unused */ |
29 | #define HAVE_TEST_AND_CLEAN_CACHE | 29 | #define HAVE_TEST_AND_CLEAN_CACHE |
30 | |||
31 | #elif CONFIG_CPU == DM320 || CONFIG_CPU == AS3525v2 | ||
32 | #define USE_MMU | ||
33 | #define HAVE_TEST_AND_CLEAN_CACHE | ||
34 | |||
30 | #elif CONFIG_CPU == AS3525 | 35 | #elif CONFIG_CPU == AS3525 |
36 | #define USE_MMU | ||
31 | #define CACHE_SIZE 8 | 37 | #define CACHE_SIZE 8 |
38 | |||
32 | #elif CONFIG_CPU == S3C2440 | 39 | #elif CONFIG_CPU == S3C2440 |
40 | #define USE_MMU | ||
33 | #define CACHE_SIZE 16 | 41 | #define CACHE_SIZE 16 |
42 | |||
34 | #else | 43 | #else |
35 | #error Cache settings unknown for this CPU ! | 44 | #error Cache settings unknown for this CPU ! |
36 | #endif | 45 | |
46 | #endif /* CPU specific configuration */ | ||
37 | 47 | ||
38 | @ Index format: 31:26 = index, N:5 = segment, remainder = SBZ | 48 | @ Index format: 31:26 = index, N:5 = segment, remainder = SBZ |
39 | @ assume 64-way set associative separate I/D caches, 32B (2^5) cache line size | 49 | @ assume 64-way set associative separate I/D caches, 32B (2^5) cache line size |
@@ -45,6 +55,8 @@ | |||
45 | #define INDEX_STEPS (CACHE_SIZE/2) | 55 | #define INDEX_STEPS (CACHE_SIZE/2) |
46 | 56 | ||
47 | 57 | ||
58 | #ifdef USE_MMU | ||
59 | |||
48 | /** MMU setup **/ | 60 | /** MMU setup **/ |
49 | 61 | ||
50 | /* | 62 | /* |
@@ -80,18 +92,18 @@ map_section: | |||
80 | @ 10: superuser - r/w, user - no access | 92 | @ 10: superuser - r/w, user - no access |
81 | @ 4: should be "1" | 93 | @ 4: should be "1" |
82 | @ 3,2: Cache flags (flags (r3)) | 94 | @ 3,2: Cache flags (flags (r3)) |
83 | @ 1: Section signature | 95 | @ 1: Section signature |
84 | orr r0, r0, r3 | 96 | orr r0, r0, r3 |
85 | orr r0, r0, #0x410 | 97 | orr r0, r0, #0x410 |
86 | orr r0, r0, #0x2 | 98 | orr r0, r0, #0x2 |
87 | 99 | ||
88 | @ unsigned int* ttbPtr = TTB_BASE + (va >> 20); | 100 | @ unsigned int* ttbPtr = TTB_BASE + (va >> 20); |
89 | @ sections are 1MB size | 101 | @ sections are 1MB size |
90 | mov r1, r1, lsr #20 | 102 | mov r1, r1, lsr #20 |
91 | ldr r3, =TTB_BASE_ADDR | 103 | ldr r3, =TTB_BASE_ADDR |
92 | add r1, r3, r1, lsl #0x2 | 104 | add r1, r3, r1, lsl #0x2 |
93 | 105 | ||
94 | @ Add MB to pa, flags are already present in pa, but addition | 106 | @ Add MB to pa, flags are already present in pa, but addition |
95 | @ should not effect them | 107 | @ should not effect them |
96 | @ | 108 | @ |
97 | @ for( ; mb>0; mb--, pa += (1 << 20)) | 109 | @ for( ; mb>0; mb--, pa += (1 << 20)) |
@@ -133,7 +145,11 @@ enable_mmu: | |||
133 | bx lr @ | 145 | bx lr @ |
134 | .size enable_mmu, .-enable_mmu | 146 | .size enable_mmu, .-enable_mmu |
135 | .ltorg | 147 | .ltorg |
136 | 148 | ||
149 | #endif /* USE_MMU */ | ||
150 | |||
151 | |||
152 | |||
137 | /** Cache coherency **/ | 153 | /** Cache coherency **/ |
138 | 154 | ||
139 | /* | 155 | /* |
@@ -315,7 +331,7 @@ cpucache_flush: | |||
315 | bne 1b @ clean_start @ | 331 | bne 1b @ clean_start @ |
316 | #endif /* HAVE_TEST_AND_CLEAN_CACHE */ | 332 | #endif /* HAVE_TEST_AND_CLEAN_CACHE */ |
317 | mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer | 333 | mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer |
318 | bx lr @ | 334 | bx lr @ |
319 | .size clean_dcache, .-clean_dcache | 335 | .size clean_dcache, .-clean_dcache |
320 | 336 | ||
321 | /* | 337 | /* |
@@ -362,7 +378,7 @@ invalidate_dcache: | |||
362 | .type invalidate_idcache, %function | 378 | .type invalidate_idcache, %function |
363 | .global cpucache_invalidate @ Alias | 379 | .global cpucache_invalidate @ Alias |
364 | invalidate_idcache: | 380 | invalidate_idcache: |
365 | cpucache_invalidate: | 381 | cpucache_invalidate: |
366 | mov r2, lr @ save lr to r1, call uses r0 only | 382 | mov r2, lr @ save lr to r1, call uses r0 only |
367 | bl invalidate_dcache @ Clean and invalidate entire DCache | 383 | bl invalidate_dcache @ Clean and invalidate entire DCache |
368 | mcr p15, 0, r1, c7, c5, 0 @ Invalidate ICache (r1=0 from call) | 384 | mcr p15, 0, r1, c7, c5, 0 @ Invalidate ICache (r1=0 from call) |