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author | Karl Kurbjun <kkurbjun@gmail.com> | 2007-11-20 04:55:57 +0000 |
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committer | Karl Kurbjun <kkurbjun@gmail.com> | 2007-11-20 04:55:57 +0000 |
commit | 95ef859fac1c5a1827a7c4a693eb8d7b836b7188 (patch) | |
tree | 5b46a51cb22c2948aaf1909898b85512804dd0a3 | |
parent | 6675e427d4261371e9b3308fdffe1a83bab4f393 (diff) | |
download | rockbox-95ef859fac1c5a1827a7c4a693eb8d7b836b7188.tar.gz rockbox-95ef859fac1c5a1827a7c4a693eb8d7b836b7188.zip |
Remove last few inw/outw uses in the M:Robe port
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15712 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/export/dm320.h | 130 | ||||
-rw-r--r-- | firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c | 37 | ||||
-rwxr-xr-x | firmware/target/arm/tms320dm320/system-target.h | 3 |
3 files changed, 84 insertions, 86 deletions
diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h index 7a64056a4c..57561dc7d3 100644 --- a/firmware/export/dm320.h +++ b/firmware/export/dm320.h | |||
@@ -227,71 +227,71 @@ | |||
227 | #define IO_DSPC_HPIB_STATUS 0x0602 | 227 | #define IO_DSPC_HPIB_STATUS 0x0602 |
228 | 228 | ||
229 | /* OSD Controller */ | 229 | /* OSD Controller */ |
230 | #define IO_OSD_MODE 0x0680 | 230 | #define IO_OSD_MODE DM320_REG(0x0680) |
231 | #define IO_OSD_VIDWINMD 0x0682 | 231 | #define IO_OSD_VIDWINMD DM320_REG(0x0682) |
232 | #define IO_OSD_OSDWINMD0 0x0684 | 232 | #define IO_OSD_OSDWINMD0 DM320_REG(0x0684) |
233 | #define IO_OSD_OSDWINMD1 0x0686 | 233 | #define IO_OSD_OSDWINMD1 DM320_REG(0x0686) |
234 | #define IO_OSD_ATRMD 0x0688 | 234 | #define IO_OSD_ATRMD DM320_REG(0x0688) |
235 | #define IO_OSD_RECTCUR 0x0688 | 235 | #define IO_OSD_RECTCUR DM320_REG(0x0688) |
236 | #define IO_OSD_RESERVED 0x068A | 236 | #define IO_OSD_RESERVED DM320_REG(0x068A) |
237 | #define IO_OSD_VIDWIN0OFST 0x068C | 237 | #define IO_OSD_VIDWIN0OFST DM320_REG(0x068C) |
238 | #define IO_OSD_VIDWIN1OFST 0x068E | 238 | #define IO_OSD_VIDWIN1OFST DM320_REG(0x068E) |
239 | #define IO_OSD_OSDWIN0OFST 0x0690 | 239 | #define IO_OSD_OSDWIN0OFST DM320_REG(0x0690) |
240 | #define IO_OSD_OSDWIN1OFST 0x0692 | 240 | #define IO_OSD_OSDWIN1OFST DM320_REG(0x0692) |
241 | #define IO_OSD_VIDWINADH 0x0694 | 241 | #define IO_OSD_VIDWINADH DM320_REG(0x0694) |
242 | #define IO_OSD_VIDWIN0ADL 0x0696 | 242 | #define IO_OSD_VIDWIN0ADL DM320_REG(0x0696) |
243 | #define IO_OSD_VIDWIN1ADL 0x0698 | 243 | #define IO_OSD_VIDWIN1ADL DM320_REG(0x0698) |
244 | #define IO_OSD_OSDWINADH 0x069A | 244 | #define IO_OSD_OSDWINADH DM320_REG(0x069A) |
245 | #define IO_OSD_OSDWIN0ADL 0x069C | 245 | #define IO_OSD_OSDWIN0ADL DM320_REG(0x069C) |
246 | #define IO_OSD_OSDWIN1ADL 0x069E | 246 | #define IO_OSD_OSDWIN1ADL DM320_REG(0x069E) |
247 | #define IO_OSD_BASEPX 0x06A0 | 247 | #define IO_OSD_BASEPX DM320_REG(0x06A0) |
248 | #define IO_OSD_BASEPY 0x06A2 | 248 | #define IO_OSD_BASEPY DM320_REG(0x06A2) |
249 | #define IO_OSD_VIDWIN0XP 0x06A4 | 249 | #define IO_OSD_VIDWIN0XP DM320_REG(0x06A4) |
250 | #define IO_OSD_VIDWIN0YP 0x06A6 | 250 | #define IO_OSD_VIDWIN0YP DM320_REG(0x06A6) |
251 | #define IO_OSD_VIDWIN0XL 0x06A8 | 251 | #define IO_OSD_VIDWIN0XL DM320_REG(0x06A8) |
252 | #define IO_OSD_VIDWIN0YL 0x06AA | 252 | #define IO_OSD_VIDWIN0YL DM320_REG(0x06AA) |
253 | #define IO_OSD_VIDWIN1XP 0x06AC | 253 | #define IO_OSD_VIDWIN1XP DM320_REG(0x06AC) |
254 | #define IO_OSD_VIDWIN1YP 0x06AE | 254 | #define IO_OSD_VIDWIN1YP DM320_REG(0x06AE) |
255 | #define IO_OSD_VIDWIN1XL 0x06B0 | 255 | #define IO_OSD_VIDWIN1XL DM320_REG(0x06B0) |
256 | #define IO_OSD_VIDWIN1YL 0x06B2 | 256 | #define IO_OSD_VIDWIN1YL DM320_REG(0x06B2) |
257 | 257 | ||
258 | #define IO_OSD_OSDWIN0XP 0x06B4 | 258 | #define IO_OSD_OSDWIN0XP DM320_REG(0x06B4) |
259 | #define IO_OSD_OSDWIN0YP 0x06B6 | 259 | #define IO_OSD_OSDWIN0YP DM320_REG(0x06B6) |
260 | #define IO_OSD_OSDWIN0XL 0x06B8 | 260 | #define IO_OSD_OSDWIN0XL DM320_REG(0x06B8) |
261 | #define IO_OSD_OSDWIN0YL 0x06BA | 261 | #define IO_OSD_OSDWIN0YL DM320_REG(0x06BA) |
262 | #define IO_OSD_OSDWIN1XP 0x06BC | 262 | #define IO_OSD_OSDWIN1XP DM320_REG(0x06BC) |
263 | #define IO_OSD_OSDWIN1YP 0x06BE | 263 | #define IO_OSD_OSDWIN1YP DM320_REG(0x06BE) |
264 | #define IO_OSD_OSDWIN1XL 0x06C0 | 264 | #define IO_OSD_OSDWIN1XL DM320_REG(0x06C0) |
265 | #define IO_OSD_OSDWIN1YL 0x06C2 | 265 | #define IO_OSD_OSDWIN1YL DM320_REG(0x06C2) |
266 | #define IO_OSD_CURXP 0x06C4 | 266 | #define IO_OSD_CURXP DM320_REG(0x06C4) |
267 | #define IO_OSD_CURYP 0x06C6 | 267 | #define IO_OSD_CURYP DM320_REG(0x06C6) |
268 | #define IO_OSD_CURXL 0x06C8 | 268 | #define IO_OSD_CURXL DM320_REG(0x06C8) |
269 | #define IO_OSD_CURYL 0x06CA | 269 | #define IO_OSD_CURYL DM320_REG(0x06CA) |
270 | 270 | ||
271 | #define IO_OSD_W0BMP01 0x06D0 | 271 | #define IO_OSD_W0BMP01 DM320_REG(0x06D0) |
272 | #define IO_OSD_W0BMP23 0x06D2 | 272 | #define IO_OSD_W0BMP23 DM320_REG(0x06D2) |
273 | #define IO_OSD_W0BMP45 0x06D4 | 273 | #define IO_OSD_W0BMP45 DM320_REG(0x06D4) |
274 | #define IO_OSD_W0BMP67 0x06D6 | 274 | #define IO_OSD_W0BMP67 DM320_REG(0x06D6) |
275 | #define IO_OSD_W0BMP89 0x06D8 | 275 | #define IO_OSD_W0BMP89 DM320_REG(0x06D8) |
276 | #define IO_OSD_W0BMPAB 0x06DA | 276 | #define IO_OSD_W0BMPAB DM320_REG(0x06DA) |
277 | #define IO_OSD_W0BMPCD 0x06DC | 277 | #define IO_OSD_W0BMPCD DM320_REG(0x06DC) |
278 | #define IO_OSD_W0BMPEF 0x06DE | 278 | #define IO_OSD_W0BMPEF DM320_REG(0x06DE) |
279 | 279 | ||
280 | #define IO_OSD_W1BMP01 0x06E0 | 280 | #define IO_OSD_W1BMP01 DM320_REG(0x06E0) |
281 | #define IO_OSD_W1BMP23 0x06E2 | 281 | #define IO_OSD_W1BMP23 DM320_REG(0x06E2) |
282 | #define IO_OSD_W1BMP45 0x06E4 | 282 | #define IO_OSD_W1BMP45 DM320_REG(0x06E4) |
283 | #define IO_OSD_W1BMP67 0x06E6 | 283 | #define IO_OSD_W1BMP67 DM320_REG(0x06E6) |
284 | #define IO_OSD_W1BMP89 0x06E8 | 284 | #define IO_OSD_W1BMP89 DM320_REG(0x06E8) |
285 | #define IO_OSD_W1BMPAB 0x06EA | 285 | #define IO_OSD_W1BMPAB DM320_REG(0x06EA) |
286 | #define IO_OSD_W1BMPCD 0x06EC | 286 | #define IO_OSD_W1BMPCD DM320_REG(0x06EC) |
287 | #define IO_OSD_W1BMPEF 0x06EE | 287 | #define IO_OSD_W1BMPEF DM320_REG(0x06EE) |
288 | 288 | ||
289 | #define IO_OSD_MISCCTL 0x06F4 | 289 | #define IO_OSD_MISCCTL DM320_REG(0x06F4) |
290 | #define IO_OSD_CLUTRAMYCB 0x06F6 | 290 | #define IO_OSD_CLUTRAMYCB DM320_REG(0x06F6) |
291 | #define IO_OSD_CLUTRAMCR 0x06F8 | 291 | #define IO_OSD_CLUTRAMCR DM320_REG(0x06F8) |
292 | 292 | ||
293 | #define IO_OSD_PPWIN0ADH 0x06FC | 293 | #define IO_OSD_PPWIN0ADH DM320_REG(0x06FC) |
294 | #define IO_OSD_PPWIN0ADL 0x06FE | 294 | #define IO_OSD_PPWIN0ADL DM320_REG(0x06FE) |
295 | 295 | ||
296 | 296 | ||
297 | /* CCD Controller */ | 297 | /* CCD Controller */ |
diff --git a/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c b/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c index 54417b0f97..e4b36eb9be 100644 --- a/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c +++ b/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include "kernel.h" | 27 | #include "kernel.h" |
28 | #include "memory.h" | 28 | #include "memory.h" |
29 | #include "system-target.h" | 29 | #include "system-target.h" |
30 | #include "lcd-target.h" | ||
30 | 31 | ||
31 | /* Copies a rectangle from one framebuffer to another. Can be used in | 32 | /* Copies a rectangle from one framebuffer to another. Can be used in |
32 | single transfer mode with width = num pixels, and height = 1 which | 33 | single transfer mode with width = num pixels, and height = 1 which |
@@ -57,25 +58,25 @@ void lcd_init_device(void) | |||
57 | /* Clear the Frame */ | 58 | /* Clear the Frame */ |
58 | memset16(FRAME, 0x0000, LCD_WIDTH*LCD_HEIGHT); | 59 | memset16(FRAME, 0x0000, LCD_WIDTH*LCD_HEIGHT); |
59 | 60 | ||
60 | outw(0x00ff, IO_OSD_MODE); | 61 | IO_OSD_MODE=0x00ff; |
61 | outw(0x0002, IO_OSD_VIDWINMD); | 62 | IO_OSD_VIDWINMD=0x0002; |
62 | outw(0x2001, IO_OSD_OSDWINMD0); | 63 | IO_OSD_OSDWINMD0=0x2001; |
63 | outw(0x0002, IO_OSD_OSDWINMD1); | 64 | IO_OSD_OSDWINMD1=0x0002; |
64 | outw(0x0000, IO_OSD_ATRMD); | 65 | IO_OSD_ATRMD=0x0000; |
65 | outw(0x0000, IO_OSD_RECTCUR); | 66 | IO_OSD_RECTCUR=0x0000; |
66 | 67 | ||
67 | outw((480*2) / 32, IO_OSD_OSDWIN0OFST); | 68 | IO_OSD_OSDWIN0OFST=(480*2) / 32; |
68 | addr = ((int)FRAME-CONFIG_SDRAM_START) / 32; | 69 | addr = ((int)FRAME-CONFIG_SDRAM_START) / 32; |
69 | outw(addr >> 16, IO_OSD_OSDWINADH); | 70 | IO_OSD_OSDWINADH=addr >> 16; |
70 | outw(addr & 0xFFFF, IO_OSD_OSDWIN0ADL); | 71 | IO_OSD_OSDWIN0ADL=addr & 0xFFFF; |
71 | 72 | ||
72 | outw(80, IO_OSD_BASEPX); | 73 | IO_OSD_BASEPX=80; |
73 | outw(2, IO_OSD_BASEPY); | 74 | IO_OSD_BASEPY=2; |
74 | 75 | ||
75 | outw(0, IO_OSD_OSDWIN0XP); | 76 | IO_OSD_OSDWIN0XP=0; |
76 | outw(0, IO_OSD_OSDWIN0YP); | 77 | IO_OSD_OSDWIN0YP=0; |
77 | outw(480, IO_OSD_OSDWIN0XL); | 78 | IO_OSD_OSDWIN0XL=480; |
78 | outw(640, IO_OSD_OSDWIN0YL); | 79 | IO_OSD_OSDWIN0YL=640; |
79 | } | 80 | } |
80 | 81 | ||
81 | /* Update a fraction of the display. */ | 82 | /* Update a fraction of the display. */ |
@@ -168,7 +169,7 @@ void lcd_yuv_blit(unsigned char * const src[3], | |||
168 | { | 169 | { |
169 | /* Caches for chroma data so it only need be recaculated every other | 170 | /* Caches for chroma data so it only need be recaculated every other |
170 | line */ | 171 | line */ |
171 | /* unsigned char chroma_buf[LCD_HEIGHT/2*3];*/ /* 480 bytes */ | 172 | unsigned char chroma_buf[LCD_HEIGHT/2*3]; /* 480 bytes */ |
172 | unsigned char const * yuv_src[3]; | 173 | unsigned char const * yuv_src[3]; |
173 | off_t z; | 174 | off_t z; |
174 | 175 | ||
@@ -188,9 +189,9 @@ void lcd_yuv_blit(unsigned char * const src[3], | |||
188 | 189 | ||
189 | do | 190 | do |
190 | { | 191 | { |
191 | /* lcd_write_yuv420_lines(dst, chroma_buf, yuv_src, width, | 192 | lcd_write_yuv420_lines(dst, chroma_buf, yuv_src, width, |
192 | stride); | 193 | stride); |
193 | */ | 194 | |
194 | yuv_src[0] += stride << 1; /* Skip down two luma lines */ | 195 | yuv_src[0] += stride << 1; /* Skip down two luma lines */ |
195 | yuv_src[1] += stride >> 1; /* Skip down one chroma line */ | 196 | yuv_src[1] += stride >> 1; /* Skip down one chroma line */ |
196 | yuv_src[2] += stride >> 1; | 197 | yuv_src[2] += stride >> 1; |
diff --git a/firmware/target/arm/tms320dm320/system-target.h b/firmware/target/arm/tms320dm320/system-target.h index 7adfda6f7d..065acd722f 100755 --- a/firmware/target/arm/tms320dm320/system-target.h +++ b/firmware/target/arm/tms320dm320/system-target.h | |||
@@ -26,7 +26,4 @@ | |||
26 | #define CPUFREQ_NORMAL 30000000 | 26 | #define CPUFREQ_NORMAL 30000000 |
27 | #define CPUFREQ_MAX 80000000 | 27 | #define CPUFREQ_MAX 80000000 |
28 | 28 | ||
29 | #define inw(p) (*((volatile unsigned short*)((p) + PHY_IO_BASE))) | ||
30 | #define outw(v,p) (*((volatile unsigned short*)((p) + PHY_IO_BASE)) = (v)) | ||
31 | |||
32 | #endif /* SYSTEM_TARGET_H */ | 29 | #endif /* SYSTEM_TARGET_H */ |