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authorSolomon Peachy <pizza@shaftnet.org>2024-07-16 17:34:26 -0400
committerSolomon Peachy <pizza@shaftnet.org>2024-07-16 17:35:53 -0400
commit942e013eac7859ee1cf823e7b98af163c79b54d5 (patch)
tree977a9d5f37f22f720f644f07ef52db483e15e61a
parent27a0cda6ac36f9be7309e4b963d5383299651c23 (diff)
downloadrockbox-942e013eac7859ee1cf823e7b98af163c79b54d5.tar.gz
rockbox-942e013eac7859ee1cf823e7b98af163c79b54d5.zip
pp5020: Cache the result of the is_ssd check.
...So we don't look it up on every write. Change-Id: I85b0abe5032a60588535b401cc719661601807ee
-rw-r--r--firmware/target/arm/pp/ata-pp5020.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/firmware/target/arm/pp/ata-pp5020.c b/firmware/target/arm/pp/ata-pp5020.c
index 396e684019..7351215693 100644
--- a/firmware/target/arm/pp/ata-pp5020.c
+++ b/firmware/target/arm/pp/ata-pp5020.c
@@ -106,6 +106,8 @@ static bool dma_boosted = false;
106static bool dma_needs_boost; 106static bool dma_needs_boost;
107#endif 107#endif
108 108
109static int ata_is_ssd = 0;
110
109/* This function sets up registers for 80 Mhz. 111/* This function sets up registers for 80 Mhz.
110 Ultra DMA mode 2 works at 30 Mhz. 112 Ultra DMA mode 2 works at 30 Mhz.
111 */ 113 */
@@ -133,6 +135,8 @@ void ata_dma_set_mode(unsigned char mode) {
133#if !defined(IPOD_NANO) 135#if !defined(IPOD_NANO)
134 IDE0_CFG |= 0x20000000; /* >= 50 Mhz */ 136 IDE0_CFG |= 0x20000000; /* >= 50 Mhz */
135#endif 137#endif
138
139 ata_is_ssd = ata_disk_isssd();
136} 140}
137 141
138#define IDE_CFG_INTRQ 8 142#define IDE_CFG_INTRQ 8
@@ -175,7 +179,7 @@ bool ata_dma_setup(void *addr, unsigned long bytes, bool write) {
175 if (write) { 179 if (write) {
176 if ((unsigned long)addr & 3) 180 if ((unsigned long)addr & 3)
177 return false; 181 return false;
178 if (!ata_disk_isssd()) 182 if (!ata_is_ssd)
179 return false; 183 return false;
180 } 184 }
181 185