Define CACHEALIGN_BITS for missing ARM CPUs for later use.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28619 a1c6a512-1295-4272-9138-f99709370657

4 files changed, 6 insertions, 1 deletions

diff --git a/firmware/export/as3525v2.h b/firmware/export/as3525v2.h
index c5c9c0504f..5cff4d6f75 100644
--- a/firmware/export/as3525v2.h
+++ b/firmware/export/as3525v2.h
@@ -26,6 +26,8 @@
 
 /* insert differences here */
 
+#define CACHEALIGN_BITS (5)
+
 #ifndef IRAM_SIZE   /* protect in case the define name changes */
 #   error IRAM_SIZE not defined !
 #endif
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h
index 7cb452d3cb..bf1a05b6ec 100644
--- a/firmware/export/imx31l.h
+++ b/firmware/export/imx31l.h
@@ -38,7 +38,6 @@
 #define FRAME         ((void *)(FRAME_PHYS_ADDR+0x100000-CSD0_BASE_ADDR))
 
 #define CACHEALIGN_BITS     5
-#define CACHEALIGN_SIZE     32
 #define NOCACHE_BASE        CSD0_BASE_ADDR
 
 /* USBOTG */
diff --git a/firmware/export/tcc77x.h b/firmware/export/tcc77x.h
index db128b68f6..3c457c5b38 100644
--- a/firmware/export/tcc77x.h
+++ b/firmware/export/tcc77x.h
@@ -21,6 +21,8 @@
 #ifndef __TCC77X_H__
 #define __TCC77X_H__
 
+#define CACHEALIGN_BITS (5)
+
 /* General-purpose IO */
 
 #define GPIOA      (*(volatile unsigned long *)0x80000300)
diff --git a/firmware/export/tcc780x.h b/firmware/export/tcc780x.h
index aca3bec2bd..8706fbbf6d 100644
--- a/firmware/export/tcc780x.h
+++ b/firmware/export/tcc780x.h
@@ -21,6 +21,8 @@
 #ifndef __TCC780X_H__
 #define __TCC780X_H__
 
+#define CACHEALIGN_BITS (5)
+
 #define TTB_SIZE      (0x4000)
 /* must be 16Kb (0x4000) aligned */
 #define TTB_BASE_ADDR (0x20000000 + (MEMORYSIZE*1024*1024) - TTB_SIZE)