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author | Aidan MacDonald <amachronic@protonmail.com> | 2021-03-03 23:48:49 +0000 |
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committer | Aidan MacDonald <amachronic@protonmail.com> | 2021-03-03 23:57:08 +0000 |
commit | 8cb4c18310f3975adfa318154b1b9c317fcdbfab (patch) | |
tree | 4fe7f92b52691d32c2cec33387dcf76c2aa53b59 | |
parent | cde5ae755fde5b645ab287a91c613f803a88d79d (diff) | |
download | rockbox-8cb4c18310f3975adfa318154b1b9c317fcdbfab.tar.gz rockbox-8cb4c18310f3975adfa318154b1b9c317fcdbfab.zip |
Really fix the MIPS cache bug this time
In fixing the original bug I tried to optimize discard_dcache_range()
to minimize writeback and inadvertently introduced a second bug, which
typically ends in a TLB refill panic.
It occurs only if the range fits within one cache line, and when both
the start and end of the range are not aligned to a cache line. This
causes ptr to be incremented and end to be decremented, so ptr > end,
and the loop can't terminate.
Change-Id: Ibaac072f1369268d3327d534ad08ef9dcee3db65
-rw-r--r-- | firmware/target/mips/mmu-mips.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c index f4ffbfa6ee..46094bf6b6 100644 --- a/firmware/target/mips/mmu-mips.c +++ b/firmware/target/mips/mmu-mips.c | |||
@@ -235,7 +235,7 @@ void discard_dcache_range(const void *base, unsigned int size) | |||
235 | } | 235 | } |
236 | 236 | ||
237 | /* Interior of region is safe to discard */ | 237 | /* Interior of region is safe to discard */ |
238 | for(; ptr != end; ptr += CACHEALIGN_SIZE) | 238 | for(; ptr <= end; ptr += CACHEALIGN_SIZE) |
239 | __CACHE_OP(DCHitInv, ptr); | 239 | __CACHE_OP(DCHitInv, ptr); |
240 | 240 | ||
241 | SYNC_WB(); | 241 | SYNC_WB(); |