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author | Aidan MacDonald <amachronic@protonmail.com> | 2021-06-10 23:54:07 +0100 |
---|---|---|
committer | Aidan MacDonald <amachronic@protonmail.com> | 2021-06-14 20:45:14 +0100 |
commit | 89f40647431713b663e416329341a733c457df32 (patch) | |
tree | dba54c935784a53b0e9abc4ad45771c92ed89d84 | |
parent | 2d6ddd0c5be78678ec2a349b9a912cc1999c1c68 (diff) | |
download | rockbox-89f40647431713b663e416329341a733c457df32.tar.gz rockbox-89f40647431713b663e416329341a733c457df32.zip |
x1000: Extend CPM registers for dual boot
Change-Id: I283834a653506fd95ff8b56897e5f3afaf375cf5
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/cpm.h | 140 | ||||
-rw-r--r-- | utils/reggen-ng/x1000.reggen | 37 |
2 files changed, 177 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/cpm.h b/firmware/target/mips/ingenic_x1000/x1000/cpm.h index 8c5d74b2e9..30750195ce 100644 --- a/firmware/target/mips/ingenic_x1000/x1000/cpm.h +++ b/firmware/target/mips/ingenic_x1000/x1000/cpm.h | |||
@@ -233,6 +233,44 @@ | |||
233 | #define BF_CPM_DDRCDR_FLAG_V(e) BF_CPM_DDRCDR_FLAG(BV_CPM_DDRCDR_FLAG__##e) | 233 | #define BF_CPM_DDRCDR_FLAG_V(e) BF_CPM_DDRCDR_FLAG(BV_CPM_DDRCDR_FLAG__##e) |
234 | #define BFM_CPM_DDRCDR_FLAG_V(v) BM_CPM_DDRCDR_FLAG | 234 | #define BFM_CPM_DDRCDR_FLAG_V(v) BM_CPM_DDRCDR_FLAG |
235 | 235 | ||
236 | #define REG_CPM_MACCDR jz_reg(CPM_MACCDR) | ||
237 | #define JA_CPM_MACCDR (0xb0000000 + 0x54) | ||
238 | #define JT_CPM_MACCDR JIO_32_RW | ||
239 | #define JN_CPM_MACCDR CPM_MACCDR | ||
240 | #define JI_CPM_MACCDR | ||
241 | #define BP_CPM_MACCDR_CLKDIV 0 | ||
242 | #define BM_CPM_MACCDR_CLKDIV 0xff | ||
243 | #define BF_CPM_MACCDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
244 | #define BFM_CPM_MACCDR_CLKDIV(v) BM_CPM_MACCDR_CLKDIV | ||
245 | #define BF_CPM_MACCDR_CLKDIV_V(e) BF_CPM_MACCDR_CLKDIV(BV_CPM_MACCDR_CLKDIV__##e) | ||
246 | #define BFM_CPM_MACCDR_CLKDIV_V(v) BM_CPM_MACCDR_CLKDIV | ||
247 | #define BP_CPM_MACCDR_CLKSRC 31 | ||
248 | #define BM_CPM_MACCDR_CLKSRC 0x80000000 | ||
249 | #define BV_CPM_MACCDR_CLKSRC__SCLK_A 0x0 | ||
250 | #define BV_CPM_MACCDR_CLKSRC__MPLL 0x1 | ||
251 | #define BF_CPM_MACCDR_CLKSRC(v) (((v) & 0x1) << 31) | ||
252 | #define BFM_CPM_MACCDR_CLKSRC(v) BM_CPM_MACCDR_CLKSRC | ||
253 | #define BF_CPM_MACCDR_CLKSRC_V(e) BF_CPM_MACCDR_CLKSRC(BV_CPM_MACCDR_CLKSRC__##e) | ||
254 | #define BFM_CPM_MACCDR_CLKSRC_V(v) BM_CPM_MACCDR_CLKSRC | ||
255 | #define BP_CPM_MACCDR_CE 29 | ||
256 | #define BM_CPM_MACCDR_CE 0x20000000 | ||
257 | #define BF_CPM_MACCDR_CE(v) (((v) & 0x1) << 29) | ||
258 | #define BFM_CPM_MACCDR_CE(v) BM_CPM_MACCDR_CE | ||
259 | #define BF_CPM_MACCDR_CE_V(e) BF_CPM_MACCDR_CE(BV_CPM_MACCDR_CE__##e) | ||
260 | #define BFM_CPM_MACCDR_CE_V(v) BM_CPM_MACCDR_CE | ||
261 | #define BP_CPM_MACCDR_BUSY 28 | ||
262 | #define BM_CPM_MACCDR_BUSY 0x10000000 | ||
263 | #define BF_CPM_MACCDR_BUSY(v) (((v) & 0x1) << 28) | ||
264 | #define BFM_CPM_MACCDR_BUSY(v) BM_CPM_MACCDR_BUSY | ||
265 | #define BF_CPM_MACCDR_BUSY_V(e) BF_CPM_MACCDR_BUSY(BV_CPM_MACCDR_BUSY__##e) | ||
266 | #define BFM_CPM_MACCDR_BUSY_V(v) BM_CPM_MACCDR_BUSY | ||
267 | #define BP_CPM_MACCDR_STOP 27 | ||
268 | #define BM_CPM_MACCDR_STOP 0x8000000 | ||
269 | #define BF_CPM_MACCDR_STOP(v) (((v) & 0x1) << 27) | ||
270 | #define BFM_CPM_MACCDR_STOP(v) BM_CPM_MACCDR_STOP | ||
271 | #define BF_CPM_MACCDR_STOP_V(e) BF_CPM_MACCDR_STOP(BV_CPM_MACCDR_STOP__##e) | ||
272 | #define BFM_CPM_MACCDR_STOP_V(v) BM_CPM_MACCDR_STOP | ||
273 | |||
236 | #define REG_CPM_I2SCDR jz_reg(CPM_I2SCDR) | 274 | #define REG_CPM_I2SCDR jz_reg(CPM_I2SCDR) |
237 | #define JA_CPM_I2SCDR (0xb0000000 + 0x60) | 275 | #define JA_CPM_I2SCDR (0xb0000000 + 0x60) |
238 | #define JT_CPM_I2SCDR JIO_32_RW | 276 | #define JT_CPM_I2SCDR JIO_32_RW |
@@ -492,6 +530,108 @@ | |||
492 | #define BF_CPM_SSICDR_STOP_V(e) BF_CPM_SSICDR_STOP(BV_CPM_SSICDR_STOP__##e) | 530 | #define BF_CPM_SSICDR_STOP_V(e) BF_CPM_SSICDR_STOP(BV_CPM_SSICDR_STOP__##e) |
493 | #define BFM_CPM_SSICDR_STOP_V(v) BM_CPM_SSICDR_STOP | 531 | #define BFM_CPM_SSICDR_STOP_V(v) BM_CPM_SSICDR_STOP |
494 | 532 | ||
533 | #define REG_CPM_CIMCDR jz_reg(CPM_CIMCDR) | ||
534 | #define JA_CPM_CIMCDR (0xb0000000 + 0x7c) | ||
535 | #define JT_CPM_CIMCDR JIO_32_RW | ||
536 | #define JN_CPM_CIMCDR CPM_CIMCDR | ||
537 | #define JI_CPM_CIMCDR | ||
538 | #define BP_CPM_CIMCDR_CLKDIV 0 | ||
539 | #define BM_CPM_CIMCDR_CLKDIV 0xff | ||
540 | #define BF_CPM_CIMCDR_CLKDIV(v) (((v) & 0xff) << 0) | ||
541 | #define BFM_CPM_CIMCDR_CLKDIV(v) BM_CPM_CIMCDR_CLKDIV | ||
542 | #define BF_CPM_CIMCDR_CLKDIV_V(e) BF_CPM_CIMCDR_CLKDIV(BV_CPM_CIMCDR_CLKDIV__##e) | ||
543 | #define BFM_CPM_CIMCDR_CLKDIV_V(v) BM_CPM_CIMCDR_CLKDIV | ||
544 | #define BP_CPM_CIMCDR_CLKSRC 31 | ||
545 | #define BM_CPM_CIMCDR_CLKSRC 0x80000000 | ||
546 | #define BV_CPM_CIMCDR_CLKSRC__SCLK_A 0x1 | ||
547 | #define BV_CPM_CIMCDR_CLKSRC__MPLL 0x1 | ||
548 | #define BF_CPM_CIMCDR_CLKSRC(v) (((v) & 0x1) << 31) | ||
549 | #define BFM_CPM_CIMCDR_CLKSRC(v) BM_CPM_CIMCDR_CLKSRC | ||
550 | #define BF_CPM_CIMCDR_CLKSRC_V(e) BF_CPM_CIMCDR_CLKSRC(BV_CPM_CIMCDR_CLKSRC__##e) | ||
551 | #define BFM_CPM_CIMCDR_CLKSRC_V(v) BM_CPM_CIMCDR_CLKSRC | ||
552 | #define BP_CPM_CIMCDR_CE 29 | ||
553 | #define BM_CPM_CIMCDR_CE 0x20000000 | ||
554 | #define BF_CPM_CIMCDR_CE(v) (((v) & 0x1) << 29) | ||
555 | #define BFM_CPM_CIMCDR_CE(v) BM_CPM_CIMCDR_CE | ||
556 | #define BF_CPM_CIMCDR_CE_V(e) BF_CPM_CIMCDR_CE(BV_CPM_CIMCDR_CE__##e) | ||
557 | #define BFM_CPM_CIMCDR_CE_V(v) BM_CPM_CIMCDR_CE | ||
558 | #define BP_CPM_CIMCDR_BUSY 28 | ||
559 | #define BM_CPM_CIMCDR_BUSY 0x10000000 | ||
560 | #define BF_CPM_CIMCDR_BUSY(v) (((v) & 0x1) << 28) | ||
561 | #define BFM_CPM_CIMCDR_BUSY(v) BM_CPM_CIMCDR_BUSY | ||
562 | #define BF_CPM_CIMCDR_BUSY_V(e) BF_CPM_CIMCDR_BUSY(BV_CPM_CIMCDR_BUSY__##e) | ||
563 | #define BFM_CPM_CIMCDR_BUSY_V(v) BM_CPM_CIMCDR_BUSY | ||
564 | #define BP_CPM_CIMCDR_STOP 27 | ||
565 | #define BM_CPM_CIMCDR_STOP 0x8000000 | ||
566 | #define BF_CPM_CIMCDR_STOP(v) (((v) & 0x1) << 27) | ||
567 | #define BFM_CPM_CIMCDR_STOP(v) BM_CPM_CIMCDR_STOP | ||
568 | #define BF_CPM_CIMCDR_STOP_V(e) BF_CPM_CIMCDR_STOP(BV_CPM_CIMCDR_STOP__##e) | ||
569 | #define BFM_CPM_CIMCDR_STOP_V(v) BM_CPM_CIMCDR_STOP | ||
570 | |||
571 | #define REG_CPM_PCMCDR jz_reg(CPM_PCMCDR) | ||
572 | #define JA_CPM_PCMCDR (0xb0000000 + 0x84) | ||
573 | #define JT_CPM_PCMCDR JIO_32_RW | ||
574 | #define JN_CPM_PCMCDR CPM_PCMCDR | ||
575 | #define JI_CPM_PCMCDR | ||
576 | #define BP_CPM_PCMCDR_DIV_M 13 | ||
577 | #define BM_CPM_PCMCDR_DIV_M 0x3fe000 | ||
578 | #define BF_CPM_PCMCDR_DIV_M(v) (((v) & 0x1ff) << 13) | ||
579 | #define BFM_CPM_PCMCDR_DIV_M(v) BM_CPM_PCMCDR_DIV_M | ||
580 | #define BF_CPM_PCMCDR_DIV_M_V(e) BF_CPM_PCMCDR_DIV_M(BV_CPM_PCMCDR_DIV_M__##e) | ||
581 | #define BFM_CPM_PCMCDR_DIV_M_V(v) BM_CPM_PCMCDR_DIV_M | ||
582 | #define BP_CPM_PCMCDR_DIV_N 0 | ||
583 | #define BM_CPM_PCMCDR_DIV_N 0x1fff | ||
584 | #define BF_CPM_PCMCDR_DIV_N(v) (((v) & 0x1fff) << 0) | ||
585 | #define BFM_CPM_PCMCDR_DIV_N(v) BM_CPM_PCMCDR_DIV_N | ||
586 | #define BF_CPM_PCMCDR_DIV_N_V(e) BF_CPM_PCMCDR_DIV_N(BV_CPM_PCMCDR_DIV_N__##e) | ||
587 | #define BFM_CPM_PCMCDR_DIV_N_V(v) BM_CPM_PCMCDR_DIV_N | ||
588 | #define BP_CPM_PCMCDR_PCS 31 | ||
589 | #define BM_CPM_PCMCDR_PCS 0x80000000 | ||
590 | #define BV_CPM_PCMCDR_PCS__SCLK_A 0x0 | ||
591 | #define BV_CPM_PCMCDR_PCS__MPLL 0x1 | ||
592 | #define BF_CPM_PCMCDR_PCS(v) (((v) & 0x1) << 31) | ||
593 | #define BFM_CPM_PCMCDR_PCS(v) BM_CPM_PCMCDR_PCS | ||
594 | #define BF_CPM_PCMCDR_PCS_V(e) BF_CPM_PCMCDR_PCS(BV_CPM_PCMCDR_PCS__##e) | ||
595 | #define BFM_CPM_PCMCDR_PCS_V(v) BM_CPM_PCMCDR_PCS | ||
596 | #define BP_CPM_PCMCDR_CS 30 | ||
597 | #define BM_CPM_PCMCDR_CS 0x40000000 | ||
598 | #define BV_CPM_PCMCDR_CS__EXCLK 0x0 | ||
599 | #define BV_CPM_PCMCDR_CS__PLL 0x1 | ||
600 | #define BF_CPM_PCMCDR_CS(v) (((v) & 0x1) << 30) | ||
601 | #define BFM_CPM_PCMCDR_CS(v) BM_CPM_PCMCDR_CS | ||
602 | #define BF_CPM_PCMCDR_CS_V(e) BF_CPM_PCMCDR_CS(BV_CPM_PCMCDR_CS__##e) | ||
603 | #define BFM_CPM_PCMCDR_CS_V(v) BM_CPM_PCMCDR_CS | ||
604 | #define BP_CPM_PCMCDR_CE 29 | ||
605 | #define BM_CPM_PCMCDR_CE 0x20000000 | ||
606 | #define BF_CPM_PCMCDR_CE(v) (((v) & 0x1) << 29) | ||
607 | #define BFM_CPM_PCMCDR_CE(v) BM_CPM_PCMCDR_CE | ||
608 | #define BF_CPM_PCMCDR_CE_V(e) BF_CPM_PCMCDR_CE(BV_CPM_PCMCDR_CE__##e) | ||
609 | #define BFM_CPM_PCMCDR_CE_V(v) BM_CPM_PCMCDR_CE | ||
610 | |||
611 | #define REG_CPM_PCMCDR1 jz_reg(CPM_PCMCDR1) | ||
612 | #define JA_CPM_PCMCDR1 (0xb0000000 + 0xe0) | ||
613 | #define JT_CPM_PCMCDR1 JIO_32_RW | ||
614 | #define JN_CPM_PCMCDR1 CPM_PCMCDR1 | ||
615 | #define JI_CPM_PCMCDR1 | ||
616 | #define BP_CPM_PCMCDR1_DIV_D 0 | ||
617 | #define BM_CPM_PCMCDR1_DIV_D 0x1fff | ||
618 | #define BF_CPM_PCMCDR1_DIV_D(v) (((v) & 0x1fff) << 0) | ||
619 | #define BFM_CPM_PCMCDR1_DIV_D(v) BM_CPM_PCMCDR1_DIV_D | ||
620 | #define BF_CPM_PCMCDR1_DIV_D_V(e) BF_CPM_PCMCDR1_DIV_D(BV_CPM_PCMCDR1_DIV_D__##e) | ||
621 | #define BFM_CPM_PCMCDR1_DIV_D_V(v) BM_CPM_PCMCDR1_DIV_D | ||
622 | #define BP_CPM_PCMCDR1_N_EN 31 | ||
623 | #define BM_CPM_PCMCDR1_N_EN 0x80000000 | ||
624 | #define BF_CPM_PCMCDR1_N_EN(v) (((v) & 0x1) << 31) | ||
625 | #define BFM_CPM_PCMCDR1_N_EN(v) BM_CPM_PCMCDR1_N_EN | ||
626 | #define BF_CPM_PCMCDR1_N_EN_V(e) BF_CPM_PCMCDR1_N_EN(BV_CPM_PCMCDR1_N_EN__##e) | ||
627 | #define BFM_CPM_PCMCDR1_N_EN_V(v) BM_CPM_PCMCDR1_N_EN | ||
628 | #define BP_CPM_PCMCDR1_D_EN 30 | ||
629 | #define BM_CPM_PCMCDR1_D_EN 0x40000000 | ||
630 | #define BF_CPM_PCMCDR1_D_EN(v) (((v) & 0x1) << 30) | ||
631 | #define BFM_CPM_PCMCDR1_D_EN(v) BM_CPM_PCMCDR1_D_EN | ||
632 | #define BF_CPM_PCMCDR1_D_EN_V(e) BF_CPM_PCMCDR1_D_EN(BV_CPM_PCMCDR1_D_EN__##e) | ||
633 | #define BFM_CPM_PCMCDR1_D_EN_V(v) BM_CPM_PCMCDR1_D_EN | ||
634 | |||
495 | #define REG_CPM_INTR jz_reg(CPM_INTR) | 635 | #define REG_CPM_INTR jz_reg(CPM_INTR) |
496 | #define JA_CPM_INTR (0xb0000000 + 0xb0) | 636 | #define JA_CPM_INTR (0xb0000000 + 0xb0) |
497 | #define JT_CPM_INTR JIO_32_RW | 637 | #define JT_CPM_INTR JIO_32_RW |
diff --git a/utils/reggen-ng/x1000.reggen b/utils/reggen-ng/x1000.reggen index f77f55b8b9..339deef483 100644 --- a/utils/reggen-ng/x1000.reggen +++ b/utils/reggen-ng/x1000.reggen | |||
@@ -509,6 +509,14 @@ node CPM { | |||
509 | fld 3 0 CLKDIV | 509 | fld 3 0 CLKDIV |
510 | } | 510 | } |
511 | 511 | ||
512 | reg MACCDR 0x54 { | ||
513 | bit 31 CLKSRC { enum SCLK_A 0; enum MPLL 1; } | ||
514 | bit 29 CE | ||
515 | bit 28 BUSY | ||
516 | bit 27 STOP | ||
517 | fld 7 0 CLKDIV | ||
518 | } | ||
519 | |||
512 | reg I2SCDR 0x60 { | 520 | reg I2SCDR 0x60 { |
513 | bit 31 PCS { enum SCLK_A 0; enum MPLL 1; } | 521 | bit 31 PCS { enum SCLK_A 0; enum MPLL 1; } |
514 | bit 30 CS { enum EXCLK 0; enum PLL 1; } | 522 | bit 30 CS { enum EXCLK 0; enum PLL 1; } |
@@ -564,6 +572,35 @@ node CPM { | |||
564 | fld 7 0 CLKDIV | 572 | fld 7 0 CLKDIV |
565 | } | 573 | } |
566 | 574 | ||
575 | reg CIMCDR 0x7c { | ||
576 | bit 31 CLKSRC { enum SCLK_A 1; enum MPLL 1 } | ||
577 | bit 29 CE | ||
578 | bit 28 BUSY | ||
579 | bit 27 STOP | ||
580 | fld 7 0 CLKDIV | ||
581 | } | ||
582 | |||
583 | reg PCMCDR 0x84 { | ||
584 | # Hardware manual says this is the correct definition, but based | ||
585 | # on Ingenic's sources, the format is actually like I2SCDR. | ||
586 | #fld 31 30 CLKSRC { enum SCLK_A 0; enum EXCLK 1; enum MPLL 2 } | ||
587 | |||
588 | # Note this format hasn't been verified to work because none of | ||
589 | # the X1000 targets are using a PCM interface. | ||
590 | bit 31 PCS { enum SCLK_A 0; enum MPLL 1; } | ||
591 | bit 30 CS { enum EXCLK 0; enum PLL 1; } | ||
592 | |||
593 | bit 29 CE | ||
594 | fld 21 13 DIV_M | ||
595 | fld 12 0 DIV_N | ||
596 | } | ||
597 | |||
598 | reg PCMCDR1 0xe0 { | ||
599 | bit 31 N_EN | ||
600 | bit 30 D_EN | ||
601 | fld 12 0 DIV_D | ||
602 | } | ||
603 | |||
567 | reg INTR 0xb0 { | 604 | reg INTR 0xb0 { |
568 | bit 1 VBUS | 605 | bit 1 VBUS |
569 | bit 0 ADEV | 606 | bit 0 ADEV |