Initial commit for the "Lyre prototype 1" port by Jorge Pinto from FS#10045.

Bootloader builds, normal does not.


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20574 a1c6a512-1295-4272-9138-f99709370657

24 files changed, 2029 insertions, 6 deletions

diff --git a/bootloader/SOURCES b/bootloader/SOURCES
index 693644df5e..d86a815840 100644
--- a/bootloader/SOURCES
+++ b/bootloader/SOURCES
@@ -47,4 +47,7 @@ creativezvm.c
 #elif CONFIG_CPU==AS3525
 sansa_as3525.c
 show_logo.c
+#elif defined(LYRE_PROTO1)
+lyre_proto1.c
+show_logo.c
 #endif
diff --git a/bootloader/lyre_proto1.c b/bootloader/lyre_proto1.c
new file mode 100644
index 0000000000..b40143b988
--- /dev/null
+++ b/bootloader/lyre_proto1.c
@@ -0,0 +1,36 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/* Include Standard files */
+#include "kernel.h"
+#include "system.h"
+
+/* Show the Rockbox logo - in show_logo.c */
+extern int show_logo(void);
+
+int main(void)
+{
+    /* Initialize Rockbox kernel */
+    kernel_init();
+
+    /* Never returns */
+    while(1) ;
+}
diff --git a/firmware/SOURCES b/firmware/SOURCES
index 82b7b34942..91482bf683 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -1259,4 +1259,16 @@ target/mips/ingenic_jz47xx/onda_vx767/lcd-onda_vx767.c
 target/mips/ingenic_jz47xx/onda_vx767/power-onda_vx767.c
 target/mips/ingenic_jz47xx/onda_vx767/sadc-onda_vx767.c
 #endif /* ONDA_VX767 */
+
+#if defined(LYRE_PROTO1)
+target/arm/at91sam/lyre_proto1/adc-lyre_proto1.c
+target/arm/at91sam/lyre_proto1/backlight-lyre_proto1.c
+target/arm/at91sam/lyre_proto1/button-lyre_proto1.c
+target/arm/at91sam/lyre_proto1/crt0.S
+target/arm/at91sam/lyre_proto1/debug-lyre_proto1.c
+target/arm/at91sam/lyre_proto1/kernel-lyre_proto1.c
+target/arm/at91sam/lyre_proto1/lcd-lyre_proto1.c
+target/arm/at91sam/lyre_proto1/system-lyre_proto1.c
+target/arm/at91sam/lyre_proto1/timer-lyre_proto1.c
+#endif
 #endif /* SIMULATOR */
diff --git a/firmware/export/at91sam9260.h b/firmware/export/at91sam9260.h
new file mode 100644
index 0000000000..fa0b9d2d4f
--- /dev/null
+++ b/firmware/export/at91sam9260.h
@@ -0,0 +1,678 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/* MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register */
+#define AT91C_MATRIX_RCA926I  (0x1 <<  0) /* (MATRIX) Remap Command for
+ARM926EJ-S Instruction Master */
+#define AT91C_MATRIX_RCA926D  (0x1 <<  1) /* (MATRIX) Remap Command for
+ARM926EJ-S Data Master */
+
+/* Register definition for MATRIX peripheral */
+#define AT91C_MATRIX_MCFG0 (*(volatile unsigned long*)   0xFFFFEE00) /*(MATRIX)
+Master Configuration Register 0 (ram96k) */
+#define AT91C_MATRIX_MCFG7 (*(volatile unsigned long*)   0xFFFFEE1C) /*(MATRIX)
+Master Configuration Register 7 (teak_prog) */
+#define AT91C_MATRIX_SCFG1 (*(volatile unsigned long*)   0xFFFFEE44) /*(MATRIX)
+Slave Configuration Register 1 (rom) */
+#define AT91C_MATRIX_MCFG4 (*(volatile unsigned long*)   0xFFFFEE10) /*(MATRIX)
+Master Configuration Register 4 (bridge) */
+#define AT91C_MATRIX_VERSION (*(volatile unsigned long*) 0xFFFFEFFC) /*(MATRIX)
+Version Register */
+#define AT91C_MATRIX_MCFG2 (*(volatile unsigned long*)   0xFFFFEE08) /*(MATRIX)
+Master Configuration Register 2 (hperiphs) */
+#define AT91C_MATRIX_PRBS0 (*(volatile unsigned long*)   0xFFFFEE84) /*(MATRIX)
+PRBS0 (ram0) */
+#define AT91C_MATRIX_SCFG3 (*(volatile unsigned long*)   0xFFFFEE4C) /*(MATRIX)
+Slave Configuration Register 3 (ebi) */
+#define AT91C_MATRIX_MCFG6 (*(volatile unsigned long*)   0xFFFFEE18) /*(MATRIX)
+Master Configuration Register 6 (ram16k) */
+#define AT91C_MATRIX_EBI (*(volatile unsigned long*)     0xFFFFEF1C) /*(MATRIX)
+Slave 3 (ebi) Special Function Register */
+#define AT91C_MATRIX_SCFG0 (*(volatile unsigned long*)   0xFFFFEE40) /*(MATRIX)
+Slave Configuration Register 0 (ram96k) */
+#define AT91C_MATRIX_PRAS0 (*(volatile unsigned long*)   0xFFFFEE80) /*(MATRIX)
+PRAS0 (ram0) */
+#define AT91C_MATRIX_MCFG3 (*(volatile unsigned long*)   0xFFFFEE0C) /*(MATRIX)
+Master Configuration Register 3 (ebi) */
+#define AT91C_MATRIX_PRAS1 (*(volatile unsigned long*)   0xFFFFEE88) /*(MATRIX)
+PRAS1 (ram1) */
+#define AT91C_MATRIX_PRAS2 (*(volatile unsigned long*)   0xFFFFEE90) /*(MATRIX)
+PRAS2 (ram2) */
+#define AT91C_MATRIX_SCFG2 (*(volatile unsigned long*)   0xFFFFEE48) /*(MATRIX)
+Slave Configuration Register 2 (hperiphs) */
+#define AT91C_MATRIX_MCFG5 (*(volatile unsigned long*)   0xFFFFEE14) /*(MATRIX)
+Master Configuration Register 5 (mailbox) */
+#define AT91C_MATRIX_MCFG1 (*(volatile unsigned long*)   0xFFFFEE04) /*(MATRIX)
+Master Configuration Register 1 (rom) */
+#define AT91C_MATRIX_MRCR (*(volatile unsigned long*)    0xFFFFEF00) /*(MATRIX)
+Master Remp Control Register */
+#define AT91C_MATRIX_PRBS2 (*(volatile unsigned long*)   0xFFFFEE94) /*(MATRIX)
+PRBS2 (ram2) */
+#define AT91C_MATRIX_SCFG4 (*(volatile unsigned long*)   0xFFFFEE50) /*(MATRIX)
+Slave Configuration Register 4 (bridge) */
+#define AT91C_MATRIX_TEAKCFG (*(volatile unsigned long*) 0xFFFFEF2C) /*(MATRIX)
+Slave 7 (teak_prog) Special Function Register */
+#define AT91C_MATRIX_PRBS1 (*(volatile unsigned long*)   0xFFFFEE8C) /*(MATRIX)
+PRBS1 (ram1) */
+
+/* SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface */
+/* - WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register ---- */
+#define AT91C_WDTC_WDRSTT     (0x1 <<  0) /* (WDTC) Watchdog Restart */
+#define AT91C_WDTC_KEY        (0xFF << 24) /* (WDTC) Watchdog KEY Password */
+/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
+#define AT91C_WDTC_WDV     (0xFFF <<  0) /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDFIEN     (0x1 << 12) /* (WDTC) Watchdog Fault Interrupt
+Enable */
+#define AT91C_WDTC_WDRSTEN    (0x1 << 13) /* (WDTC) Watchdog Reset Enable */
+#define AT91C_WDTC_WDRPROC    (0x1 << 14) /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDDIS      (0x1 << 15) /* (WDTC) Watchdog Disable */
+#define AT91C_WDTC_WDD        (0xFFF << 16) /* (WDTC) Watchdog Delta Value */
+#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) /* (WDTC) Watchdog Debug Halt */
+#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) /* (WDTC) Watchdog Idle Halt */
+/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register ----- */
+#define AT91C_WDTC_WDUNF      (0x1 <<  0) /* (WDTC) Watchdog Underflow */
+#define AT91C_WDTC_WDERR      (0x1 <<  1) /* (WDTC) Watchdog Error */
+
+/* SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface */
+/* - WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register ---- */
+#define AT91C_WDTC_WDRSTT     (0x1 <<  0) /* (WDTC) Watchdog Restart */
+#define AT91C_WDTC_KEY        (0xFF << 24) /* (WDTC) Watchdog KEY Password */
+/* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
+#define AT91C_WDTC_WDV     (0xFFF <<  0) /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDFIEN     (0x1 << 12) /* (WDTC) Watchdog Fault Interrupt
+Enable */
+#define AT91C_WDTC_WDRSTEN    (0x1 << 13) /* (WDTC) Watchdog Reset Enable */
+#define AT91C_WDTC_WDRPROC    (0x1 << 14) /* (WDTC) Watchdog Timer Restart */
+#define AT91C_WDTC_WDDIS      (0x1 << 15) /* (WDTC) Watchdog Disable */
+#define AT91C_WDTC_WDD        (0xFFF << 16) /* (WDTC) Watchdog Delta Value */
+#define AT91C_WDTC_WDDBGHLT   (0x1 << 28) /* (WDTC) Watchdog Debug Halt */
+#define AT91C_WDTC_WDIDLEHLT  (0x1 << 29) /* (WDTC) Watchdog Idle Halt */
+/* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register ----- */
+#define AT91C_WDTC_WDUNF      (0x1 <<  0) /* (WDTC) Watchdog Underflow */
+#define AT91C_WDTC_WDERR      (0x1 <<  1) /* (WDTC) Watchdog Error */
+
+/* Register definition for WDTC peripheral */
+#define AT91C_WDTC_WDCR (*(volatile unsigned long*)  0xFFFFFD40) /* (WDTC)
+Watchdog Control Register */
+#define AT91C_WDTC_WDSR (*(volatile unsigned long*)  0xFFFFFD48) /* (WDTC)
+Watchdog Status Register */
+#define AT91C_WDTC_WDMR (*(volatile unsigned long*)  0xFFFFFD44) /* (WDTC)
+Watchdog Mode Register */
+
+/* CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register */
+#define AT91C_CKGR_MOSCEN     (0x1 <<  0) /* (CKGR) Main Oscillator Enable */
+#define AT91C_CKGR_OSCBYPASS  (0x1 <<  1) /* (CKGR) Main Oscillator Bypass */
+#define AT91C_CKGR_OSCOUNT    (0xFF <<  8) /* (CKGR) Main Oscillator Start
+-up Time */
+/* CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register */
+#define AT91C_CKGR_MAINF      (0xFFFF <<  0) /* (CKGR) Main Clock Frequency */
+#define AT91C_CKGR_MAINRDY    (0x1 << 16) /* (CKGR) Main Clock Ready */
+/* CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register */
+#define AT91C_CKGR_DIVA       (0xFF <<  0) /* (CKGR) Divider A Selected */
+#define     AT91C_CKGR_DIVA_0        (0x0) /* (CKGR) Divider A output is 0 */
+#define     AT91C_CKGR_DIVA_BYPASS    (0x1) /* (CKGR) Divider A is bypassed */
+#define AT91C_CKGR_PLLACOUNT  (0x3F <<  8) /* (CKGR) PLL A Counter */
+#define AT91C_CKGR_OUTA  (0x3 << 14) /* (CKGR) PLL A Output Frequency Range */
+#define     AT91C_CKGR_OUTA_0                    (0x0 << 14) /* (CKGR) Please
+refer to the PLLA datasheet */
+#define     AT91C_CKGR_OUTA_1                    (0x1 << 14) /* (CKGR) Please
+refer to the PLLA datasheet */
+#define     AT91C_CKGR_OUTA_2                    (0x2 << 14) /* (CKGR) Please
+refer to the PLLA datasheet */
+#define     AT91C_CKGR_OUTA_3                    (0x3 << 14) /* (CKGR) Please
+refer to the PLLA datasheet */
+#define AT91C_CKGR_MULA       (0x7FF << 16) /* (CKGR) PLL A Multiplier */
+#define AT91C_CKGR_SRCA       (0x1 << 29) /* (CKGR) */
+/* CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register */
+#define AT91C_CKGR_DIVB       (0xFF <<  0) /* (CKGR) Divider B Selected */
+#define     AT91C_CKGR_DIVB_0        (0x0) /* (CKGR) Divider B output is 0 */
+#define     AT91C_CKGR_DIVB_BYPASS   (0x1) /* (CKGR) Divider B is bypassed */
+#define AT91C_CKGR_PLLBCOUNT  (0x3F <<  8) /* (CKGR) PLL B Counter */
+#define AT91C_CKGR_OUTB  (0x3 << 14) /* (CKGR) PLL B Output Frequency Range */
+#define     AT91C_CKGR_OUTB_0                    (0x0 << 14) /* (CKGR) Please
+refer to the PLLB datasheet */
+#define     AT91C_CKGR_OUTB_1                    (0x1 << 14) /* (CKGR) Please
+refer to the PLLB datasheet */
+#define     AT91C_CKGR_OUTB_2                    (0x2 << 14) /* (CKGR) Please
+refer to the PLLB datasheet */
+#define     AT91C_CKGR_OUTB_3                    (0x3 << 14) /* (CKGR) Please
+refer to the PLLB datasheet */
+#define AT91C_CKGR_MULB       (0x7FF << 16) /* (CKGR) PLL B Multiplier */
+#define AT91C_CKGR_USBDIV     (0x3 << 28) /* (CKGR) Divider for USB Clocks */
+#define     AT91C_CKGR_USBDIV_0                    (0x0 << 28) /* (CKGR)
+Divider output is PLL clock output */
+#define     AT91C_CKGR_USBDIV_1                    (0x1 << 28) /* (CKGR)
+Divider output is PLL clock output divided by 2 */
+#define     AT91C_CKGR_USBDIV_2                    (0x2 << 28) /* (CKGR)
+Divider output is PLL clock output divided by 4 */
+
+/* SOFTWARE API DEFINITION  FOR Power Management Controler */
+/* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register ----- */
+#define AT91C_PMC_PCK         (0x1 <<  0) /* (PMC) Processor Clock */
+#define AT91C_PMC_UHP         (0x1 <<  6) /* (PMC) USB Host Port Clock */
+#define AT91C_PMC_UDP         (0x1 <<  7) /* (PMC) USB Device Port Clock */
+#define AT91C_PMC_PCK0        (0x1 <<  8) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK1        (0x1 <<  9) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_HCK0        (0x1 << 16) /* (PMC) AHB UHP Clock Output */
+#define AT91C_PMC_HCK1        (0x1 << 17) /* (PMC) AHB LCDC Clock Output */
+/* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ----- */
+ /* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register ----- */
+ /* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
+ /* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register--- */
+ /* -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- */
+ /* -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- */
+ /* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
+ #define AT91C_PMC_CSS    (0x3 <<  0) /* (PMC) Programmable Clock Selection */
+ #define AT91C_PMC_CSS_SLOW_CLK      (0x0) /* (PMC) Slow Clock is selected */
+ #define  AT91C_PMC_CSS_MAIN_CLK      (0x1) /* (PMC) Main Clock is selected */
+ #define AT91C_PMC_CSS_PLLA_CLK (0x2) /* (PMC) Clock from PLL A is selected */
+ #define AT91C_PMC_CSS_PLLB_CLK (0x3) /* (PMC) Clock from PLL B is selected */
+ #define AT91C_PMC_PRES   (0x7 <<  2) /* (PMC) Programmable Clock Prescaler */
+ #define AT91C_PMC_PRES_CLK     (0x0 <<  2) /* (PMC) Selected clock */
+ #define AT91C_PMC_PRES_CLK_2   (0x1 <<  2) /* (PMC) Selected clock
+                                                            divided by 2 */
+ #define AT91C_PMC_PRES_CLK_4   (0x2 <<  2) /* (PMC) Selected clock
+                                                            divided by 4 */
+ #define AT91C_PMC_PRES_CLK_8   (0x3 <<  2) /* (PMC) Selected clock
+                                                            divided by 8 */
+ #define AT91C_PMC_PRES_CLK_16  (0x4 <<  2) /* (PMC) Selected clock
+                                                            divided by 16 */
+ #define AT91C_PMC_PRES_CLK_32  (0x5 <<  2) /* (PMC) Selected clock
+                                                            divided by 32 */
+ #define AT91C_PMC_PRES_CLK_64  (0x6 <<  2) /* (PMC) Selected clock
+                                                            divided by 64 */
+ #define AT91C_PMC_MDIV      (0x3 <<  8) /* (PMC) Master Clock Divisionv */
+ #define AT91C_PMC_MDIV_1  (0x0 <<  8) /* (PMC) The master clock and the
+                                              processor clock are the same */
+ #define AT91C_PMC_MDIV_2  (0x1 <<  8) /* (PMC) The processor clock is twice
+                                                as fast as the master clock */
+ #define AT91C_PMC_MDIV_3  (0x2 <<  8) /* (PMC) The processor clock is four
+                                         times faster than the master clock */
+ /* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register ----- */
+ /* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register ---- */
+ #define AT91C_PMC_MOSCS (0x1 <<  0) /* (PMC) MOSC Status/Enable/Disable/Mask*/
+ #define AT91C_PMC_LOCKA (0x1 <<  1) /* (PMC) PLL A Status/Enable/Disable/
+                                                                      Mask */
+ #define AT91C_PMC_LOCKB (0x1 <<  2) /* (PMC) PLL B Status/Enable/Disable/
+                                                                      Mask */
+ #define AT91C_PMC_MCKRDY (0x1 <<  3) /* (PMC) Master Clock Status/Enable/
+ Disable/Mask */
+ #define AT91C_PMC_PCK0RDY (0x1 <<  8) /* (PMC) PCK0_RDY Status/Enable/
+ Disable/Mask */
+ #define AT91C_PMC_PCK1RDY (0x1 <<  9) /* (PMC) PCK1_RDY Status/Enable/
+ Disable/Mask */
+ /* ---PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
+ /* ------ PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
+ #define AT91C_PMC_OSCSEL      (0x1 <<  7) /* (PMC) 32kHz Oscillator
+ selection status */
+ /* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register ---- */
+
+/* SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller */
+/* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
+#define AT91C_AIC_PRIOR       (0x7 <<  0) /* (AIC) Priority Level */
+#define     AT91C_AIC_PRIOR_LOWEST               (0x0) /* (AIC) Lowest priority
+                                                            level */
+#define     AT91C_AIC_PRIOR_HIGHEST              (0x7) /* (AIC) Highest
+                                                             priority level */
+#define AT91C_AIC_SRCTYPE     (0x3 <<  5) /* (AIC) Interrupt Source Type */
+#define     AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) /* (AIC)
+                                Internal Sources Code Label Level Sensitive */
+#define     AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) /* (AIC)
+                                 Internal Sources Code Label Edge triggered */
+#define     AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) /* (AIC)
+                            External Sources Code Label High-level Sensitive */
+#define     AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) /* (AIC)
+                         External Sources Code Label Positive Edge triggered */
+/* - AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register ----- */
+#define AT91C_AIC_NFIQ        (0x1 <<  0) /* (AIC) NFIQ Status */
+#define AT91C_AIC_NIRQ        (0x1 <<  1) /* (AIC) NIRQ Status */
+/* - AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) ---- */
+#define AT91C_AIC_DCR_PROT    (0x1 <<  0) /* (AIC) Protection Mode */
+#define AT91C_AIC_DCR_GMSK    (0x1 <<  1) /* (AIC) General Mask */
+
+/* Register definition for AIC peripheral */
+#define AT91C_AIC_IVR   (*(volatile unsigned long*)  0xFFFFF100) /* (AIC) IRQ
+Vector Register */
+#define AIC_IVR 0x00000100
+/* (AIC) Source Mode Register */
+#define AT91C_AIC_SMR(a) (*(volatile unsigned long*)  (0xFFFFF000 + 4*(a)))
+#define AT91C_AIC_FVR   (*(volatile unsigned long*)  0xFFFFF104) /* (AIC) FIQ
+Vector Register */
+#define AT91C_AIC_DCR   (*(volatile unsigned long*)  0xFFFFF138) /* (AIC) Debug
+Control Register (Protect) */
+#define AT91C_AIC_EOICR (*(volatile unsigned long*)  0xFFFFF130) /* (AIC) End
+of Interrupt Command Register */
+#define AIC_EOICR 0x00000130
+/* (AIC) Source Vector Register */
+#define AT91C_AIC_SVR(a) (*(volatile unsigned long*)  (0xFFFFF080 + 4*(a)))
+#define AT91C_AIC_FFSR  (*(volatile unsigned long*)  0xFFFFF148) /* (AIC) Fast
+Forcing Status Register */
+#define AT91C_AIC_ICCR  (*(volatile unsigned long*)  0xFFFFF128) /* (AIC)
+Interrupt Clear Command Register */
+#define AT91C_AIC_ISR   (*(volatile unsigned long*)  0xFFFFF108) /* (AIC)
+Interrupt Status Register */
+#define AT91C_AIC_IMR   (*(volatile unsigned long*)  0xFFFFF110) /* (AIC)
+Interrupt Mask Register */
+#define AT91C_AIC_IPR   (*(volatile unsigned long*)  0xFFFFF10C) /* (AIC)
+Interrupt Pending Register */
+#define AT91C_AIC_FFER  (*(volatile unsigned long*)  0xFFFFF140) /* (AIC)
+Fast Forcing Enable Register */
+#define AT91C_AIC_IECR  (*(volatile unsigned long*)  0xFFFFF120) /* (AIC)
+Interrupt Enable Command Register */
+#define AT91C_AIC_ISCR  (*(volatile unsigned long*)  0xFFFFF12C) /* (AIC)
+Interrupt Set Command Register */
+#define AT91C_AIC_FFDR  (*(volatile unsigned long*)  0xFFFFF144) /* (AIC)
+Fast Forcing Disable Register */
+#define AT91C_AIC_CISR  (*(volatile unsigned long*)  0xFFFFF114) /* (AIC)
+Core Interrupt Status Register */
+#define AT91C_AIC_IDCR  (*(volatile unsigned long*)  0xFFFFF124) /* (AIC)
+Interrupt Disable Command Register */
+#define AT91C_AIC_SPU   (*(volatile unsigned long*)  0xFFFFF134) /* (AIC)
+Spurious Vector Register */
+
+/* SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface */
+/* PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
+#define AT91C_PITC_PIV        (0xFFFFF <<  0) /* (PITC) Periodic Interval
+Value */
+#define AT91C_PITC_PITEN      (0x1 << 24) /* (PITC) Periodic Interval Timer
+Enabled */
+#define AT91C_PITC_PITIEN     (0x1 << 25) /* (PITC) Periodic Interval Timer
+Interrupt Enable */
+/* --- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register - */
+#define AT91C_PITC_PITS       (0x1 <<  0) /* (PITC) Periodic Interval Timer
+Status */
+/* - PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register ---- */
+#define AT91C_PITC_CPIV       (0xFFFFF <<  0) /* (PITC) Current Periodic
+Interval Value */
+#define AT91C_PITC_PICNT (0xFFF << 20) /* (PITC) Periodic Interval Counter */
+/* PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register ---- */
+
+/* Register definition for AIC peripheral */
+#define AT91C_AIC_IVR   (*(volatile unsigned long*)  0xFFFFF100) /* (AIC) IRQ
+Vector Register */
+#define AIC_IVR 0x00000100
+#define AT91C_AIC_EOICR (*(volatile unsigned long*)  0xFFFFF130) /* (AIC) End
+of Interrupt Command Register */
+#define AIC_EOICR 0x00000130
+
+/* Register definition for PIOA peripheral */
+#define AT91C_PIOA_ODR  (*(volatile unsigned long*)  0xFFFFF414) /* (PIOA)
+Output Disable Registerr */
+#define AT91C_PIOA_SODR (*(volatile unsigned long*)  0xFFFFF430) /* (PIOA)
+Set Output Data Register */
+#define AT91C_PIOA_ISR  (*(volatile unsigned long*)  0xFFFFF44C) /* (PIOA)
+Interrupt Status Register */
+#define AT91C_PIOA_ABSR (*(volatile unsigned long*)  0xFFFFF478) /* (PIOA)
+AB Select Status Register */
+#define AT91C_PIOA_IER  (*(volatile unsigned long*)  0xFFFFF440) /* (PIOA)
+Interrupt Enable Register */
+#define AT91C_PIOA_PPUDR (*(volatile unsigned long*)     0xFFFFF460) /* (PIOA)
+Pull-up Disable Register */
+#define AT91C_PIOA_IMR  (*(volatile unsigned long*)  0xFFFFF448) /* (PIOA)
+Interrupt Mask Register */
+#define AT91C_PIOA_PER  (*(volatile unsigned long*)  0xFFFFF400) /* (PIOA)
+PIO Enable Register */
+#define AT91C_PIOA_IFDR (*(volatile unsigned long*)  0xFFFFF424) /* (PIOA)
+Input Filter Disable Register */
+#define AT91C_PIOA_OWDR (*(volatile unsigned long*)  0xFFFFF4A4) /* (PIOA)
+Output Write Disable Register */
+#define AT91C_PIOA_MDSR (*(volatile unsigned long*)  0xFFFFF458) /* (PIOA)
+Multi-driver Status Register */
+#define AT91C_PIOA_IDR  (*(volatile unsigned long*)  0xFFFFF444) /* (PIOA)
+Interrupt Disable Register */
+#define AT91C_PIOA_ODSR (*(volatile unsigned long*)  0xFFFFF438) /* (PIOA)
+Output Data Status Register */
+#define AT91C_PIOA_PPUSR (*(volatile unsigned long*)  0xFFFFF468) /* (PIOA)
+Pull-up Status Register */
+#define AT91C_PIOA_OWSR (*(volatile unsigned long*)  0xFFFFF4A8) /* (PIOA)
+Output Write Status Register */
+#define AT91C_PIOA_BSR  (*(volatile unsigned long*)  0xFFFFF474) /* (PIOA)
+Select B Register */
+#define AT91C_PIOA_OWER (*(volatile unsigned long*)  0xFFFFF4A0) /* (PIOA)
+Output Write Enable Register */
+#define AT91C_PIOA_IFER (*(volatile unsigned long*)  0xFFFFF420) /* (PIOA)
+Input Filter Enable Register */
+#define AT91C_PIOA_PDSR (*(volatile unsigned long*)  0xFFFFF43C) /* (PIOA)
+Pin Data Status Register */
+#define AT91C_PIOA_PPUER (*(volatile unsigned long*)  0xFFFFF464) /* (PIOA)
+Pull-up Enable Register */
+#define AT91C_PIOA_OSR  (*(volatile unsigned long*)  0xFFFFF418) /* (PIOA)
+Output Status Register */
+#define AT91C_PIOA_ASR  (*(volatile unsigned long*)  0xFFFFF470) /* (PIOA)
+Select A Register */
+#define AT91C_PIOA_MDDR (*(volatile unsigned long*)  0xFFFFF454) /* (PIOA)
+Multi-driver Disable Register */
+#define AT91C_PIOA_CODR (*(volatile unsigned long*)  0xFFFFF434) /* (PIOA)
+Clear Output Data Register */
+#define AT91C_PIOA_MDER (*(volatile unsigned long*)  0xFFFFF450) /* (PIOA)
+Multi-driver Enable Register */
+#define AT91C_PIOA_PDR  (*(volatile unsigned long*)  0xFFFFF404) /* (PIOA)
+PIO Disable Register */
+#define AT91C_PIOA_IFSR (*(volatile unsigned long*)  0xFFFFF428) /* (PIOA)
+Input Filter Status Register */
+#define AT91C_PIOA_OER  (*(volatile unsigned long*)  0xFFFFF410) /* (PIOA)
+Output Enable Register */
+#define AT91C_PIOA_PSR  (*(volatile unsigned long*)  0xFFFFF408) /* (PIOA)
+PIO Status Register */
+
+/* Register definition for PIOB peripheral */
+#define AT91C_PIOB_OWDR (*(volatile unsigned long*)  0xFFFFF6A4) /* (PIOB)
+Output Write Disable Register */
+#define AT91C_PIOB_MDER (*(volatile unsigned long*)  0xFFFFF650) /* (PIOB)
+Multi-driver Enable Register */
+#define AT91C_PIOB_PPUSR (*(volatile unsigned long*)     0xFFFFF668) /* (PIOB)
+Pull-up Status Register */
+#define AT91C_PIOB_IMR  (*(volatile unsigned long*)  0xFFFFF648) /* (PIOB)
+Interrupt Mask Register */
+#define AT91C_PIOB_ASR  (*(volatile unsigned long*)  0xFFFFF670) /* (PIOB)
+Select A Register */
+#define AT91C_PIOB_PPUDR (*(volatile unsigned long*)     0xFFFFF660) /* (PIOB)
+Pull-up Disable Register */
+#define AT91C_PIOB_PSR  (*(volatile unsigned long*)  0xFFFFF608) /* (PIOB)
+PIO Status Register */
+#define AT91C_PIOB_IER  (*(volatile unsigned long*)  0xFFFFF640) /* (PIOB)
+Interrupt Enable Register */
+#define AT91C_PIOB_CODR (*(volatile unsigned long*)  0xFFFFF634) /* (PIOB)
+Clear Output Data Register */
+#define AT91C_PIOB_OWER (*(volatile unsigned long*)  0xFFFFF6A0) /* (PIOB)
+Output Write Enable Register */
+#define AT91C_PIOB_ABSR (*(volatile unsigned long*)  0xFFFFF678) /* (PIOB)
+AB Select Status Register */
+#define AT91C_PIOB_IFDR (*(volatile unsigned long*)  0xFFFFF624) /* (PIOB)
+Input Filter Disable Register */
+#define AT91C_PIOB_PDSR (*(volatile unsigned long*)  0xFFFFF63C) /* (PIOB)
+Pin Data Status Register */
+#define AT91C_PIOB_IDR  (*(volatile unsigned long*)  0xFFFFF644) /* (PIOB)
+Interrupt Disable Register */
+#define AT91C_PIOB_OWSR (*(volatile unsigned long*)  0xFFFFF6A8) /* (PIOB)
+Output Write Status Register */
+#define AT91C_PIOB_PDR  (*(volatile unsigned long*)  0xFFFFF604) /* (PIOB)
+PIO Disable Register */
+#define AT91C_PIOB_ODR  (*(volatile unsigned long*)  0xFFFFF614) /* (PIOB)
+Output Disable Registerr */
+#define AT91C_PIOB_IFSR (*(volatile unsigned long*)  0xFFFFF628) /* (PIOB)
+Input Filter Status Register */
+#define AT91C_PIOB_PPUER (*(volatile unsigned long*)     0xFFFFF664) /* (PIOB)
+Pull-up Enable Register */
+#define AT91C_PIOB_SODR (*(volatile unsigned long*)  0xFFFFF630) /* (PIOB)
+Set Output Data Register */
+#define AT91C_PIOB_ISR  (*(volatile unsigned long*)  0xFFFFF64C) /* (PIOB)
+Interrupt Status Register */
+#define AT91C_PIOB_ODSR (*(volatile unsigned long*)  0xFFFFF638) /* (PIOB)
+Output Data Status Register */
+#define AT91C_PIOB_OSR  (*(volatile unsigned long*)  0xFFFFF618) /* (PIOB)
+Output Status Register */
+#define AT91C_PIOB_MDSR (*(volatile unsigned long*)  0xFFFFF658) /* (PIOB)
+Multi-driver Status Register */
+#define AT91C_PIOB_IFER (*(volatile unsigned long*)  0xFFFFF620) /* (PIOB)
+Input Filter Enable Register */
+#define AT91C_PIOB_BSR  (*(volatile unsigned long*)  0xFFFFF674) /* (PIOB)
+Select B Register */
+#define AT91C_PIOB_MDDR (*(volatile unsigned long*)  0xFFFFF654) /* (PIOB)
+Multi-driver Disable Register */
+#define AT91C_PIOB_OER  (*(volatile unsigned long*)  0xFFFFF610) /* (PIOB)
+Output Enable Register */
+#define AT91C_PIOB_PER  (*(volatile unsigned long*)  0xFFFFF600) /* (PIOB)
+PIO Enable Register */
+
+/* Register definition for PIOC peripheral */
+#define AT91C_PIOC_OWDR (*(volatile unsigned long*)  0xFFFFF8A4) /* (PIOC)
+Output Write Disable Register */
+#define AT91C_PIOC_SODR (*(volatile unsigned long*)  0xFFFFF830) /* (PIOC)
+Set Output Data Register */
+#define AT91C_PIOC_PPUER (*(volatile unsigned long*)     0xFFFFF864) /* (PIOC)
+Pull-up Enable Register */
+#define AT91C_PIOC_CODR (*(volatile unsigned long*)  0xFFFFF834) /* (PIOC)
+Clear Output Data Register */
+#define AT91C_PIOC_PSR  (*(volatile unsigned long*)  0xFFFFF808) /* (PIOC)
+PIO Status Register */
+#define AT91C_PIOC_PDR  (*(volatile unsigned long*)  0xFFFFF804) /* (PIOC)
+PIO Disable Register */
+#define AT91C_PIOC_ODR  (*(volatile unsigned long*)  0xFFFFF814) /* (PIOC)
+Output Disable Register */
+#define AT91C_PIOC_PPUSR (*(volatile unsigned long*)     0xFFFFF868) /* (PIOC)
+Pull-up Status Register */
+#define AT91C_PIOC_ABSR (*(volatile unsigned long*)  0xFFFFF878) /* (PIOC)
+AB Select Status Register */
+#define AT91C_PIOC_IFSR (*(volatile unsigned long*)  0xFFFFF828) /* (PIOC)
+Input Filter Status Register */
+#define AT91C_PIOC_OER  (*(volatile unsigned long*)  0xFFFFF810) /* (PIOC)
+Output Enable Register */
+#define AT91C_PIOC_IMR  (*(volatile unsigned long*)  0xFFFFF848) /* (PIOC)
+Interrupt Mask Register */
+#define AT91C_PIOC_ASR  (*(volatile unsigned long*)  0xFFFFF870) /* (PIOC)
+Select A Register */
+#define AT91C_PIOC_MDDR (*(volatile unsigned long*)  0xFFFFF854) /* (PIOC)
+Multi-driver Disable Register */
+#define AT91C_PIOC_OWSR (*(volatile unsigned long*)  0xFFFFF8A8) /* (PIOC)
+Output Write Status Register */
+#define AT91C_PIOC_PER  (*(volatile unsigned long*)  0xFFFFF800) /* (PIOC)
+PIO Enable Register */
+#define AT91C_PIOC_IDR  (*(volatile unsigned long*)  0xFFFFF844) /* (PIOC)
+Interrupt Disable Register */
+#define AT91C_PIOC_MDER (*(volatile unsigned long*)  0xFFFFF850) /* (PIOC)
+Multi-driver Enable Register */
+#define AT91C_PIOC_PDSR (*(volatile unsigned long*)  0xFFFFF83C) /* (PIOC)
+Pin Data Status Register */
+#define AT91C_PIOC_MDSR (*(volatile unsigned long*)  0xFFFFF858) /* (PIOC)
+Multi-driver Status Register */
+#define AT91C_PIOC_OWER (*(volatile unsigned long*)  0xFFFFF8A0) /* (PIOC)
+Output Write Enable Register */
+#define AT91C_PIOC_BSR  (*(volatile unsigned long*)  0xFFFFF874) /* (PIOC)
+Select B Register */
+#define AT91C_PIOC_PPUDR (*(volatile unsigned long*)     0xFFFFF860) /* (PIOC)
+Pull-up Disable Register */
+#define AT91C_PIOC_IFDR (*(volatile unsigned long*)  0xFFFFF824) /* (PIOC)
+Input Filter Disable Register */
+#define AT91C_PIOC_IER  (*(volatile unsigned long*)  0xFFFFF840) /* (PIOC)
+Interrupt Enable Register */
+#define AT91C_PIOC_OSR  (*(volatile unsigned long*)  0xFFFFF818) /* (PIOC)
+Output Status Register */
+#define AT91C_PIOC_ODSR (*(volatile unsigned long*)  0xFFFFF838) /* (PIOC)
+Output Data Status Register */
+#define AT91C_PIOC_ISR  (*(volatile unsigned long*)  0xFFFFF84C) /* (PIOC)
+Interrupt Status Register */
+#define AT91C_PIOC_IFER (*(volatile unsigned long*)  0xFFFFF820) /* (PIOC)
+Input Filter Enable Register */
+
+/* Register definition for PMC peripheral */
+#define AT91C_PMC_PCER  (*(volatile unsigned long*)  0xFFFFFC10) /* (PMC)
+Peripheral Clock Enable Register */
+#define AT91C_PMC_PCKR  (*(volatile unsigned long*)  0xFFFFFC40) /* (PMC)
+Programmable Clock Register */
+#define AT91C_PMC_MCKR  (*(volatile unsigned long*)  0xFFFFFC30) /* (PMC)
+Master Clock Register */
+#define AT91C_PMC_PLLAR (*(volatile unsigned long*)  0xFFFFFC28) /* (PMC)
+PLL A Register */
+#define AT91C_PMC_PCDR  (*(volatile unsigned long*)  0xFFFFFC14) /* (PMC)
+Peripheral Clock Disable Register */
+#define AT91C_PMC_SCSR  (*(volatile unsigned long*)  0xFFFFFC08) /* (PMC)
+System Clock Status Register */
+#define AT91C_PMC_MCFR  (*(volatile unsigned long*)  0xFFFFFC24) /* (PMC)
+Main Clock  Frequency Register */
+#define AT91C_PMC_IMR   (*(volatile unsigned long*)  0xFFFFFC6C) /* (PMC)
+Interrupt Mask Register */
+#define AT91C_PMC_IER   (*(volatile unsigned long*)  0xFFFFFC60) /* (PMC)
+Interrupt Enable Register */
+#define AT91C_PMC_MOR   (*(volatile unsigned long *) 0xFFFFFC20) /* (PMC)
+Main Oscillator Register */
+#define AT91C_PMC_IDR   (*(volatile unsigned long *)  0xFFFFFC64) /* (PMC)
+Interrupt Disable Register */
+#define AT91C_PMC_PLLBR (*(volatile unsigned long*)  0xFFFFFC2C) /* (PMC)
+PLL B Register */
+#define AT91C_PMC_SCDR  (*(volatile unsigned long*)  0xFFFFFC04) /* (PMC)
+System Clock Disable Register */
+#define AT91C_PMC_PCSR  (*(volatile unsigned long*)  0xFFFFFC18) /* (PMC)
+Peripheral Clock Status Register */
+#define AT91C_PMC_SCER  (*(volatile unsigned long*)  0xFFFFFC00) /* (PMC)
+System Clock Enable Register */
+#define AT91C_PMC_SR    (*(volatile unsigned long*)  0xFFFFFC68) /* (PMC)
+Status Register */
+
+/* Register definition for PITC peripheral */
+#define AT91C_PITC_PIVR (*(volatile unsigned long*)  0xFFFFFD38) /* (PITC)
+Period Interval Value Register */
+#define AT91C_PITC_PISR (*(volatile unsigned long*)  0xFFFFFD34) /* (PITC)
+Period Interval Status Register */
+#define AT91C_PITC_PIIR (*(volatile unsigned long*)  0xFFFFFD3C) /* (PITC)
+Period Interval Image Register */
+#define AT91C_PITC_PIMR (*(volatile unsigned long*)  0xFFFFFD30) /* (PITC)
+Period Interval Mode Register */
+
+/* PIO DEFINITIONS FOR AT91SAM9260 */
+#define AT91C_PIO_PA0        (1 <<  0) /* Pin Controlled by PA0 */
+#define AT91C_PIO_PA1        (1 <<  1) /* Pin Controlled by PA1 */
+#define AT91C_PIO_PA10       (1 << 10) /* Pin Controlled by PA10 */
+#define AT91C_PIO_PA11       (1 << 11) /* Pin Controlled by PA11 */
+#define AT91C_PIO_PA12       (1 << 12) /* Pin Controlled by PA12 */
+#define AT91C_PIO_PA13       (1 << 13) /* Pin Controlled by PA13 */
+#define AT91C_PIO_PA14       (1 << 14) /* Pin Controlled by PA14 */
+#define AT91C_PIO_PA15       (1 << 15) /* Pin Controlled by PA15 */
+#define AT91C_PIO_PA16       (1 << 16) /* Pin Controlled by PA16 */
+#define AT91C_PIO_PA17       (1 << 17) /* Pin Controlled by PA17 */
+#define AT91C_PIO_PA18       (1 << 18) /* Pin Controlled by PA18 */
+#define AT91C_PIO_PA19       (1 << 19) /* Pin Controlled by PA19 */
+#define AT91C_PIO_PA2        (1 <<  2) /* Pin Controlled by PA2 */
+#define AT91C_PIO_PA20       (1 << 20) /* Pin Controlled by PA20 */
+#define AT91C_PIO_PA21       (1 << 21) /* Pin Controlled by PA21 */
+#define AT91C_PIO_PA22       (1 << 22) /* Pin Controlled by PA22 */
+#define AT91C_PIO_PA23       (1 << 23) /* Pin Controlled by PA23 */
+#define AT91C_PIO_PA24       (1 << 24) /* Pin Controlled by PA24 */
+#define AT91C_PIO_PA25       (1 << 25) /* Pin Controlled by PA25 */
+#define AT91C_PIO_PA26       (1 << 26) /* Pin Controlled by PA26 */
+#define AT91C_PIO_PA27       (1 << 27) /* Pin Controlled by PA27 */
+#define AT91C_PIO_PA28       (1 << 28) /* Pin Controlled by PA28 */
+#define AT91C_PIO_PA29       (1 << 29) /* Pin Controlled by PA29 */
+#define AT91C_PIO_PA3        (1 <<  3) /* Pin Controlled by PA3 */
+#define AT91C_PIO_PA30       (1 << 30) /* Pin Controlled by PA30 */
+#define AT91C_PIO_PA31       (1 << 31) /* Pin Controlled by PA31 */
+#define AT91C_PIO_PA4        (1 <<  4) /* Pin Controlled by PA4 */
+#define AT91C_PIO_PA5        (1 <<  5) /* Pin Controlled by PA5 */
+#define AT91C_PIO_PA6        (1 <<  6) /* Pin Controlled by PA6 */
+#define AT91C_PIO_PA7        (1 <<  7) /* Pin Controlled by PA7 */
+#define AT91C_PIO_PA8        (1 <<  8) /* Pin Controlled by PA8 */
+#define AT91C_PIO_PA9        (1 <<  9) /* Pin Controlled by PA9 */
+#define AT91C_PIO_PB0        (1 <<  0) /* Pin Controlled by PB0 */
+#define AT91C_PIO_PB1        (1 <<  1) /* Pin Controlled by PB1 */
+#define AT91C_PIO_PB10       (1 << 10) /* Pin Controlled by PB10 */
+#define AT91C_PIO_PB11       (1 << 11) /* Pin Controlled by PB11 */
+#define AT91C_PIO_PB12       (1 << 12) /* Pin Controlled by PB12 */
+#define AT91C_PIO_PB13       (1 << 13) /* Pin Controlled by PB13 */
+#define AT91C_PIO_PB14       (1 << 14) /* Pin Controlled by PB14 */
+#define AT91C_PIO_PB15       (1 << 15) /* Pin Controlled by PB15 */
+#define AT91C_PIO_PB16       (1 << 16) /* Pin Controlled by PB16 */
+#define AT91C_PIO_PB17       (1 << 17) /* Pin Controlled by PB17 */
+#define AT91C_PIO_PB18       (1 << 18) /* Pin Controlled by PB18 */
+#define AT91C_PIO_PB19       (1 << 19) /* Pin Controlled by PB19 */
+#define AT91C_PIO_PB2        (1 <<  2) /* Pin Controlled by PB2 */
+#define AT91C_PIO_PB20       (1 << 20) /* Pin Controlled by PB20 */
+#define AT91C_PIO_PB21       (1 << 21) /* Pin Controlled by PB21 */
+#define AT91C_PIO_PB22       (1 << 22) /* Pin Controlled by PB22 */
+#define AT91C_PIO_PB23       (1 << 23) /* Pin Controlled by PB23 */
+#define AT91C_PIO_PB24       (1 << 24) /* Pin Controlled by PB24 */
+#define AT91C_PIO_PB25       (1 << 25) /* Pin Controlled by PB25 */
+#define AT91C_PIO_PB26       (1 << 26) /* Pin Controlled by PB26 */
+#define AT91C_PIO_PB27       (1 << 27) /* Pin Controlled by PB27 */
+#define AT91C_PIO_PB28       (1 << 28) /* Pin Controlled by PB28 */
+#define AT91C_PIO_PB29       (1 << 29) /* Pin Controlled by PB29 */
+#define AT91C_PIO_PB3        (1 <<  3) /* Pin Controlled by PB3 */
+#define AT91C_PIO_PB30       (1 << 30) /* Pin Controlled by PB30 */
+#define AT91C_PIO_PB31       (1 << 31) /* Pin Controlled by PB31 */
+#define AT91C_PIO_PB4        (1 <<  4) /* Pin Controlled by PB4 */
+#define AT91C_PIO_PB5        (1 <<  5) /* Pin Controlled by PB5 */
+#define AT91C_PIO_PB6        (1 <<  6) /* Pin Controlled by PB6 */
+#define AT91C_PIO_PB7        (1 <<  7) /* Pin Controlled by PB7 */
+#define AT91C_PIO_PB8        (1 <<  8) /* Pin Controlled by PB8 */
+#define AT91C_PIO_PB9        (1 <<  9) /* Pin Controlled by PB9 */
+#define AT91C_PIO_PC0        (1 <<  0) /* Pin Controlled by PC0 */
+#define AT91C_PIO_PC1        (1 <<  1) /* Pin Controlled by PC1 */
+#define AT91C_PIO_PC10       (1 << 10) /* Pin Controlled by PC10 */
+#define AT91C_PIO_PC11       (1 << 11) /* Pin Controlled by PC11 */
+#define AT91C_PIO_PC12       (1 << 12) /* Pin Controlled by PC12 */
+#define AT91C_PIO_PC13       (1 << 13) /* Pin Controlled by PC13 */
+#define AT91C_PIO_PC14       (1 << 14) /* Pin Controlled by PC14 */
+#define AT91C_PIO_PC15       (1 << 15) /* Pin Controlled by PC15 */
+#define AT91C_PIO_PC16       (1 << 16) /* Pin Controlled by PC16 */
+#define AT91C_PIO_PC17       (1 << 17) /* Pin Controlled by PC17 */
+#define AT91C_PIO_PC18       (1 << 18) /* Pin Controlled by PC18 */
+#define AT91C_PIO_PC19       (1 << 19) /* Pin Controlled by PC19 */
+#define AT91C_PIO_PC2        (1 <<  2) /* Pin Controlled by PC2 */
+#define AT91C_PIO_PC20       (1 << 20) /* Pin Controlled by PC20 */
+#define AT91C_PIO_PC21       (1 << 21) /* Pin Controlled by PC21 */
+#define AT91C_PIO_PC22       (1 << 22) /* Pin Controlled by PC22 */
+#define AT91C_PIO_PC23       (1 << 23) /* Pin Controlled by PC23 */
+#define AT91C_PIO_PC24       (1 << 24) /* Pin Controlled by PC24 */
+#define AT91C_PIO_PC25       (1 << 25) /* Pin Controlled by PC25 */
+#define AT91C_PIO_PC26       (1 << 26) /* Pin Controlled by PC26 */
+#define AT91C_PIO_PC27       (1 << 27) /* Pin Controlled by PC27 */
+#define AT91C_PIO_PC28       (1 << 28) /* Pin Controlled by PC28 */
+#define AT91C_PIO_PC29       (1 << 29) /* Pin Controlled by PC29 */
+#define AT91C_PIO_PC3        (1 <<  3) /* Pin Controlled by PC3 */
+#define AT91C_PIO_PC30       (1 << 30) /* Pin Controlled by PC30 */
+#define AT91C_PIO_PC31       (1 << 31) /* Pin Controlled by PC31 */
+#define AT91C_PIO_PC4        (1 <<  4) /* Pin Controlled by PC4 */
+#define AT91C_PIO_PC5        (1 <<  5) /* Pin Controlled by PC5 */
+#define AT91C_PIO_PC6        (1 <<  6) /* Pin Controlled by PC6 */
+#define AT91C_PIO_PC7        (1 <<  7) /* Pin Controlled by PC7 */
+#define AT91C_PIO_PC8        (1 <<  8) /* Pin Controlled by PC8 */
+#define AT91C_PIO_PC9        (1 <<  9) /* Pin Controlled by PC9 */
+
+/* PERIPHERAL ID DEFINITIONS FOR AT91SAM9260 */
+#define AT91C_ID_FIQ    ( 0) /* Advanced Interrupt Controller (FIQ) */
+#define AT91C_ID_SYS    ( 1) /* System Controller */
+#define AT91C_ID_PIOA   ( 2) /* Parallel IO Controller A */
+#define AT91C_ID_PIOB   ( 3) /* Parallel IO Controller B */
+#define AT91C_ID_PIOC   ( 4) /* Parallel IO Controller C */
+#define AT91C_ID_ADC    ( 5) /* ADC */
+#define AT91C_ID_US0    ( 6) /* USART 0 */
+#define AT91C_ID_US1    ( 7) /* USART 1 */
+#define AT91C_ID_US2    ( 8) /* USART 2 */
+#define AT91C_ID_MCI    ( 9) /* Multimedia Card Interface 0 */
+#define AT91C_ID_UDP    (10) /* USB Device Port */
+#define AT91C_ID_TWI    (11) /* Two-Wire Interface */
+#define AT91C_ID_SPI0   (12) /* Serial Peripheral Interface 0 */
+#define AT91C_ID_SPI1   (13) /* Serial Peripheral Interface 1 */
+#define AT91C_ID_SSC0   (14) /* Serial Synchronous Controller 0 */
+#define AT91C_ID_TC0    (17) /* Timer Counter 0 */
+#define AT91C_ID_TC1    (18) /* Timer Counter 1 */
+#define AT91C_ID_TC2    (19) /* Timer Counter 2 */
+#define AT91C_ID_UHP    (20) /* USB Host Port */
+#define AT91C_ID_EMAC   (21) /* Ethernet Mac */
+#define AT91C_ID_HISI   (22) /* Image Sensor Interface */
+#define AT91C_ID_US3    (23) /* USART 3 */
+#define AT91C_ID_US4    (24) /* USART 4 */
+#define AT91C_ID_US5    (25) /* USART 5 */
+#define AT91C_ID_TC3    (26) /* Timer Counter 3 */
+#define AT91C_ID_TC4    (27) /* Timer Counter 4 */
+#define AT91C_ID_TC5    (28) /* Timer Counter 5 */
+#define AT91C_ID_IRQ0   (29) /* Advanced Interrupt Controller (IRQ0) */
+#define AT91C_ID_IRQ1   (30) /* Advanced Interrupt Controller (IRQ1) */
+#define AT91C_ID_IRQ2   (31) /* Advanced Interrupt Controller (IRQ2) */
+#define AT91C_ALL_INT   (0xFFFE7FFF) /* ALL VALID INTERRUPTS */
+
+/* MEMORY MAPPING DEFINITIONS FOR AT91SAM9260 */
+#define AT91C_IRAM_1     (0x00200000) /* Maximum IRAM_1 Area : 4Kbyte
+base address */
+#define AT91C_IRAM_1_SIZE    (0x00001000) /* Maximum IRAM_1 Area : 4Kbyte size
+ in byte (4 Kbytes) */
+#define AT91C_EBI_SDRAM_32BIT    (0x20000000) /* SDRAM on EBI Chip Select 1
+base address */
+#define AT91C_BASE_AIC       0xFFFFF000 /* (AIC) Base Address */
diff --git a/firmware/export/config-lyre_proto1.h b/firmware/export/config-lyre_proto1.h
new file mode 100644
index 0000000000..58a9350bb9
--- /dev/null
+++ b/firmware/export/config-lyre_proto1.h
@@ -0,0 +1,100 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/*
+ * This config file is for the Lyre prototype 1.
+ */
+#define TARGET_TREE /* this target is using the target tree system */
+
+#define CONFIG_SDRAM_START 0x20000000
+
+/* For Rolo and boot loader */
+#define MODEL_NUMBER 130
+
+/* define this if the flash memory uses the
+ * SecureDigital Memory Card protocol */
+#define CONFIG_STORAGE STORAGE_SD
+#define HAVE_FLASH_STORAGE
+
+/* define this if you have a bitmap LCD display */
+#define HAVE_LCD_BITMAP
+
+/* define this if you have a colour LCD */
+#define HAVE_LCD_COLOR
+
+#define CONFIG_LCD LCD_LYRE_PROTO1
+
+/* LCD dimensions */
+#define LCD_WIDTH  128
+#define LCD_HEIGHT 128
+/* The LCD used is just rgb444, 64 colours. We do a bit conversion on LCD
+ * drivers. */
+#define LCD_DEPTH  16   /* 65536 colours */
+#define LCD_PIXELFORMAT RGB565 /* rgb565 */
+
+#define HAVE_ALBUMART
+
+#define CONFIG_KEYPAD LYRE_PROTO1_PAD
+
+/* Define this if you do software codec */
+#define CONFIG_CODEC SWCODEC
+
+/* The number of bytes reserved for loadable codecs */
+#define CODEC_SIZE 0x100000
+
+/* The number of bytes reserved for loadable plugins */
+#define PLUGIN_BUFFER_SIZE 0x100000
+
+/* Lyre prototype 1 do not use I2C, just SPI */
+#define CONFIG_I2C I2C_NONE
+
+/* Define this if you have the TLV320 audio codec -> controlled by the DSP */
+#define HAVE_TLV320
+
+/* TLV320 has no tone controls, so we use the software ones */
+#define HAVE_SW_TONE_CONTROLS
+
+#define BATTERY_CAPACITY_DEFAULT 1100 /* default battery capacity */
+#define BATTERY_CAPACITY_MIN 500        /* min. capacity selectable */
+#define BATTERY_CAPACITY_MAX 2500        /* max. capacity selectable */
+#define BATTERY_CAPACITY_INC 100         /* capacity increment */
+#define BATTERY_TYPES_COUNT  1          /* only one type */
+
+#ifndef SIMULATOR
+
+#define CONFIG_CPU AT91SAM9260
+
+/* Define this to the CPU frequency */
+#define CPU_FREQ 198656000
+#define MCK_FREQ 99328000
+#define SLOW_CLOCK 32768
+
+/* Offset ( in the firmware file's header ) to the file CRC */
+#define FIRMWARE_OFFSET_FILE_CRC 0
+
+/* Offset ( in the firmware file's header ) to the real data */
+#define FIRMWARE_OFFSET_FILE_DATA 8
+
+#define BOOTFILE_EXT "lyre_proto1"
+#define BOOTFILE "rockbox." BOOTFILE_EXT
+#define BOOTDIR "/.rockbox"
+
+#endif
diff --git a/firmware/export/config.h b/firmware/export/config.h
index d7375ddaac..45dd5d2394 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -69,6 +69,7 @@
 #define S5L8700      8700
 #define JZ4732       4732
 #define AS3525       3525
+#define AT91SAM9260  9260
 
 /* CONFIG_KEYPAD */
 #define PLAYER_PAD          1
@@ -107,6 +108,7 @@
 #define MEIZU_M3_PAD       34
 #define SANSA_CLIP_PAD     35
 #define SANSA_FUZE_PAD     36
+#define LYRE_PROTO1_PAD    37
 
 /* CONFIG_REMOTE_KEYPAD */
 #define H100_REMOTE 1
@@ -145,7 +147,7 @@
 #define CHARGING_TARGET  3 /* Any algorithm - usually software controlled
                             * charging or specific programming is required to
                             * use the charging hardware. */
-                      
+
 /* CONFIG_LCD */
 #define LCD_SSD1815   1 /* as used by Archos Recorders and Ondios */
 #define LCD_SSD1801   2 /* as used by Archos Player/Studio */
@@ -181,6 +183,7 @@
 #define LCD_ONDAVX767 30 /* as used by the Onda VX767 */
 #define LCD_SSD1303   31 /* as used by the Sansa Clip */
 #define LCD_FUZE      32 /* as used by the Sansa Fuze */
+#define LCD_LYRE_PROTO1      33 /* as used by the Lyre */
 
 /* LCD_PIXELFORMAT */
 #define HORIZONTAL_PACKING 1
@@ -196,6 +199,8 @@
 #define SCREEN_SQUARE       2
 
 /* CONFIG_I2C */
+#define I2C_NONE     0 /* For targets that do not use I2C - as the
+Lyre prototype 1*/
 #define I2C_PLAYREC  1 /* Archos Player/Recorder style */
 #define I2C_ONDIO    2 /* Ondio style */
 #define I2C_COLDFIRE 3 /* Coldfire style */
@@ -356,6 +361,8 @@
 #include "config-fuze.h"
 #elif defined(SANSA_C200V2)
 #include "config-c200v2.h"
+#elif defined(LYRE_PROTO1)
+#include "config-lyre_proto1.h"
 #else
 /* no known platform */
 #endif
@@ -535,7 +542,7 @@
 #endif /* BOOTLOADER */
 
 #if defined(HAVE_USBSTACK) || (CONFIG_CPU == JZ4732) \
-    || (CONFIG_CPU == AS3525) || (CONFIG_CPU == S3C2440) 
+    || (CONFIG_CPU == AS3525) || (CONFIG_CPU == S3C2440)
 #define HAVE_WAKEUP_OBJECTS
 #endif
 
@@ -580,7 +587,8 @@
 #define ARM_ARCH 6 /* ARMv6 */
 #endif
 
-#if defined(CPU_TCC77X) || defined(CPU_TCC780X) || (CONFIG_CPU == DM320)
+#if defined(CPU_TCC77X) || defined(CPU_TCC780X) || (CONFIG_CPU == DM320) \
+  || (CONFIG_CPU == AT91SAM9260)
 #define CPU_ARM
 #define ARM_ARCH 5 /* ARMv5 */
 #endif
diff --git a/firmware/target/arm/at91sam/boot.lds b/firmware/target/arm/at91sam/boot.lds
new file mode 100644
index 0000000000..c638511e47
--- /dev/null
+++ b/firmware/target/arm/at91sam/boot.lds
@@ -0,0 +1,81 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(reset_handler)
+STARTUP(target/arm/at91sam/lyre_proto1/crt0.o)
+
+#define DRAMSIZE    (MEMORYSIZE * 0x100000)
+#define DRAMORIG    0x20000000
+#define IRAM0ORIG   0x200000
+#define IRAM0SIZE   4K
+#define IRAM1ORIG   0x300000
+#define IRAM1SIZE   4K
+#define STACKSIZE   2k
+
+MEMORY
+{
+    DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
+    IRAM0 : ORIGIN = IRAM0ORIG, LENGTH = IRAM0SIZE
+}
+
+SECTIONS
+{
+    /* We will put Rockbox bootloader at the last 1MByte of the  SDRAM. */
+
+    /* Example of a section:
+    * .section VMA(Virtual Memory Address) : LMA(Load Memory Address).
+    * VMA and LMA addresses can be verified by doing:
+    * "arm-elf-objdump -h bootloader.elf". */
+
+    .vectors 0 : AT (DRAMORIG + DRAMSIZE - 1M)
+    {
+        _start_vectors_section = .;
+        *(.vectors)
+        *(.glue_7)
+        *(.glue_7t)
+        . = ALIGN(4);
+        _end_vectors_section = .;
+    }
+
+    .text (DRAMORIG + DRAMSIZE -1M + SIZEOF(.vectors)) : \
+    AT (DRAMORIG + DRAMSIZE -1M + SIZEOF(.vectors))
+    {
+        *(.text)
+        *(.text*)
+        *(.icode)
+        *(.icode*)
+        *(.rodata)
+        *(.rodata*)
+        . = ALIGN(4);
+    }
+
+    /* Initialized variables are placed on SDRAM, right after .vectors section. */
+    /* Data section: VMA is the same as the LMA, right after the end of .vector */
+    .data . :
+    {
+        *(.data)
+        *(.data*)
+        . = ALIGN(4);
+        _end_data_section = .;
+    }
+
+    /* Uninitialized variables are placed at SDRAM, right after .text section. */
+    .bss (NOLOAD) :
+    
+    { 
+        _start_bss_section = .;
+        *(.bss) /* Bss section contains all uninitialized data generated by the compiler. */
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _end_bss_section = .;
+    }
+
+    /* Stack is placed at SDRAM, right after .bss section. */
+    .stack . :
+    {
+       *(.stack)
+       stackbegin = .;
+       . += STACKSIZE;
+       stackend = .;
+    }
+}
diff --git a/firmware/target/arm/at91sam/lyre_proto1/adc-lyre_proto1.c b/firmware/target/arm/at91sam/lyre_proto1/adc-lyre_proto1.c
new file mode 100644
index 0000000000..3734d6d1b1
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/adc-lyre_proto1.c
@@ -0,0 +1,31 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+void adc_init(void)
+{
+}
+
+/* Called to get the recent ADC reading */
+inline unsigned short adc_read(int channel)
+{
+    (void)channel;
+    return 0;
+}
diff --git a/firmware/target/arm/at91sam/lyre_proto1/adc-target.h b/firmware/target/arm/at91sam/lyre_proto1/adc-target.h
new file mode 100644
index 0000000000..3712e476ea
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/adc-target.h
@@ -0,0 +1,28 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef _ADC_TARGET_H_
+#define _ADC_TARGET_H_
+
+void adc_init(void);
+inline unsigned short adc_read(int channel);
+
+#endif
diff --git a/firmware/target/arm/at91sam/lyre_proto1/backlight-lyre_proto1.c b/firmware/target/arm/at91sam/lyre_proto1/backlight-lyre_proto1.c
new file mode 100644
index 0000000000..fabf8aa041
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/backlight-lyre_proto1.c
@@ -0,0 +1,45 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+void _backlight_set_brightness(int brightness)
+{
+    (void)brightness;
+}
+
+void _backlight_on(void)
+{
+
+}
+
+void _backlight_off(void)
+{
+
+}
+
+void _buttonlight_on(void)
+{
+
+}
+
+void _buttonlight_off(void)
+{
+
+}
diff --git a/firmware/target/arm/at91sam/lyre_proto1/backlight-target.h b/firmware/target/arm/at91sam/lyre_proto1/backlight-target.h
new file mode 100644
index 0000000000..f4e253abbe
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/backlight-target.h
@@ -0,0 +1,26 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef BACKLIGHT_TARGET_H
+#define BACKLIGHT_TARGET_H
+
+
+#endif
diff --git a/firmware/target/arm/at91sam/lyre_proto1/button-lyre_proto1.c b/firmware/target/arm/at91sam/lyre_proto1/button-lyre_proto1.c
new file mode 100644
index 0000000000..2d38803115
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/button-lyre_proto1.c
@@ -0,0 +1,99 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "at91sam9260.h"
+#include "button.h"
+
+#define BUTTON_01 AT91C_PIO_PB4
+#define BUTTON_02 AT91C_PIO_PB5
+#define BUTTON_03 AT91C_PIO_PB27
+#define BUTTON_04 AT91C_PIO_PB26
+#define BUTTON_05 AT91C_PIO_PB25
+#define BUTTON_06 AT91C_PIO_PB24
+#define BUTTON_07 AT91C_PIO_PB22
+#define BUTTON_08 AT91C_PIO_PB23
+
+void button_init_device(void)
+{
+    /* Enable the periph clock for the PIO controller */
+    /* This is mandatory when PIO are configured as input */
+    AT91C_PMC_PCER = (1 << AT91C_ID_PIOB);
+
+    /* Set the PIO line in input */
+    AT91C_PIOB_ODR = (BUTTON_01 |
+                      BUTTON_02 |
+                      BUTTON_03 |
+                      BUTTON_04 |
+                      BUTTON_05 |
+                      BUTTON_06 |
+                      BUTTON_07 |
+                      BUTTON_08);
+
+    /* Set the PIO controller in PIO mode instead of peripheral mode */
+    AT91C_PIOB_PER = (BUTTON_01 |
+                      BUTTON_02 |
+                      BUTTON_03 |
+                      BUTTON_04 |
+                      BUTTON_05 |
+                      BUTTON_06 |
+                      BUTTON_07 |
+                      BUTTON_08);
+}
+
+bool button_hold(void)
+{
+    return (0);
+}
+
+/*
+ * Get button pressed from hardware
+ */
+int button_read_device(void)
+{
+    uint32_t buttons = AT91C_PIOB_PDSR;
+    uint32_t ret = 0;
+
+    if ((buttons & BUTTON_01) == 0)
+        ret |= BUTTON_UP;
+
+    if ((buttons & BUTTON_02) == 0)
+        ret |= BUTTON_RIGHT;
+
+    if ((buttons & BUTTON_03) == 0)
+        ret |= BUTTON_PLAY;
+
+    if ((buttons & BUTTON_04) == 0)
+        ret |= BUTTON_SELECT;
+
+    if ((buttons & BUTTON_05) == 0)
+        ret |= BUTTON_LEFT;
+
+    if ((buttons & BUTTON_06) == 0)
+        ret |= BUTTON_DOWN;
+
+    if ((buttons & BUTTON_07) == 0)
+        ret |= BUTTON_STOP;
+
+    if ((buttons & BUTTON_08) == 0)
+        ret |= BUTTON_MENU;
+
+    return ret;
+}
diff --git a/firmware/target/arm/at91sam/lyre_proto1/button-target.h b/firmware/target/arm/at91sam/lyre_proto1/button-target.h
new file mode 100644
index 0000000000..e05f9f294f
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/button-target.h
@@ -0,0 +1,48 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef _BUTTON_TARGET_H_
+#define _BUTTON_TARGET_H_
+
+#include <stdbool.h>
+#include "config.h"
+
+#define BUTTON_SELECT       0x00000001
+#define BUTTON_MENU         0x00000002
+#define BUTTON_PLAY         0x00000004
+#define BUTTON_STOP         0x00000008
+
+#define BUTTON_LEFT         0x00000010
+#define BUTTON_RIGHT        0x00000020
+#define BUTTON_UP           0x00000040
+#define BUTTON_DOWN         0x00000080
+
+#define BUTTON_MAIN         (BUTTON_UP|BUTTON_DOWN|BUTTON_RIGHT|BUTTON_LEFT \
+                            |BUTTON_SELECT|BUTTON_MENU|BUTTON_PLAY \
+                            |BUTTON_STOP)
+bool button_hold(void);
+void button_init_device(void);
+int button_read_device(void);
+
+/* No Remote control */
+#define BUTTON_REMOTE 0
+
+#endif /* _BUTTON_TARGET_H_ */
diff --git a/firmware/target/arm/at91sam/lyre_proto1/crt0.S b/firmware/target/arm/at91sam/lyre_proto1/crt0.S
new file mode 100644
index 0000000000..0146a8409c
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/crt0.S
@@ -0,0 +1,274 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "at91sam9260.h"
+
+#define DRAMORIG        AT91C_EBI_SDRAM_32BIT
+#define DRAMSIZE        (MEMORYSIZE * 0x100000)
+#define IRAM0ORIG       AT91C_IRAM_1
+#define IRAM0SIZE       AT91C_IRAM_1_SIZE
+#define TOP_OF_MEMORY   (IRAM0ORIG + IRAM0SIZE)
+#define ABT_STACK_SIZE  8*3*4
+#define IRQ_STACK_SIZE  8*3*4
+
+#define ARM_MODE_ABT     0x17
+#define ARM_MODE_FIQ     0x11
+#define ARM_MODE_IRQ     0x12
+#define ARM_MODE_SVC     0x13
+
+#define I_BIT            0x80
+#define F_BIT            0x40
+
+
+/* Application startup entry point */
+.globl reset_handler
+
+.align 4
+
+.section .vectors
+.arm
+
+
+/* Exception vectors (should be a branch to be detected as a valid code
+ * by the rom) */
+_exception_vectors:
+reset_vector:
+    ldr      pc, =reset_handler
+undef_vector:
+    b        undef_vector    /* Undefined Instruction */
+swi_vector:
+    b        swi_vector      /* Software Interrupt */
+pabt_vector:
+    ldr      pc, =pabt_handler     /* Prefetch Abort */
+dabt_vector:
+    ldr      pc, =dabt_handler     /* Data Abort */
+rsvd_vector:
+    b        rsvd_vector     /* reserved */
+irq_vector:
+    b        irq_handler     /* IRQ : read the AIC */
+fiq_vector:
+/*-----------------------------------------------------------------------------
+ *- Function             : fiq_handler
+ *- Treatments           : FIQ (Fast Interrupt) Interrupt Handler.
+ *- Called Functions     :
+ *---------------------------------------------------------------------------*/
+fiq_handler:
+pabt_handler:
+dabt_handler:
+    b        fiq_handler
+
+/*-----------------------------------------------------------------------------
+ *- Function             : irq_handler
+ *- Treatments           : IRQ Controller Interrupt Handler.
+ *- Called Functions     : AIC_IVR[interrupt]
+ *---------------------------------------------------------------------------*/
+irq_handler:
+/*- Manage Exception Entry */
+/*- Adjust and save LR_irq in IRQ stack - (LR - Link Register) */
+    sub      lr, lr, #4
+    stmfd    sp!, {lr}
+/*- Save r0 and SPSR (Saved Program Status Register) in IRQ stack */
+    mrs      r14, SPSR
+    stmfd    sp!, {r0,r14}
+
+/*- Write in the IVR (Interrupt Vector Register) to support Protect Mode */
+/*- No effect in Normal Mode */
+/*- De-assert the NIRQ and clear the source in Protect Mode */
+    ldr      r14, =AT91C_BASE_AIC
+    ldr      r0 , [r14, #AIC_IVR]
+    str      r14, [r14, #AIC_IVR]
+
+/*- Enable Interrupt and Switch in Supervisor Mode */
+    msr      CPSR_c, #ARM_MODE_SVC
+
+/*- Save scratch/used registers and LR in User Stack */
+    stmfd    sp!, {r1-r3, r12, r14}
+
+/*- Branch to the routine pointed by the AIC_IVR */
+    mov      r14, pc
+    bx       r0
+
+/*- Restore scratch/used registers and LR from User Stack */
+    ldmia    sp!, {r1-r3, r12, r14}
+
+/*- Disable Interrupt and switch back in IRQ mode */
+    msr      CPSR_c, #ARM_MODE_IRQ | I_BIT
+
+/*- Mark the End of Interrupt on the AIC */
+    ldr      r14, =AT91C_BASE_AIC
+    str      r14, [r14, #AIC_EOICR]
+
+/*- Restore SPSR_irq and r0 from IRQ stack */
+    ldmia    sp!, {r0,r14}
+    msr      SPSR_cxsf, r14
+
+/*- Restore adjusted LR_irq from IRQ stack directly in the PC */
+    ldmia    sp!, {pc}^
+
+/*-----------------------------------------------------------------------------
+ *- Function             : reset_handler
+ *- Treatments           : Reset Interrupt Handler.
+ *- Called Functions     : lowlevel_init
+ *                         main
+ *---------------------------------------------------------------------------*/
+.section .text
+reset_handler:
+/*-----------------------------------------------------------------------------
+ *- Low level Init is performed in a C function: lowlevel_init
+ *- Init Stack Pointer to a valid memory area before calling lowlevel_init
+ *
+ * Put Stack Pointer on end of IRAM 1 and branches to lowlevel_init function.
+ *---------------------------------------------------------------------------*/
+/*- Temporary stack in internal RAM for Low Level Init execution */
+_low_level_init:
+    ldr      r2, =_litteral_pool_lowlevel_init /* Load r2 with the address of
+    * _litteral_pool_lowlevel_init
+    */
+    ldmia    r2, {r0, r1} /* r0 = lowlevel_init and r1 = TOP_OF_MEMORY */
+    mov      sp, r1 /* sp (Stack Pointer) = TOP_OF_MEMORY (end of IRAM 1) */
+    mov      lr, pc /* lr (Link register) = pc (Program Counter) */
+    bx       r0 /* Branch on C function (interworking) -- branch to
+    * lowlevel_init
+    */
+
+/*-----------------------------------------------------------------------------
+ *- Setup the stack for each mode
+ *
+ * Executes this code after returning from lowlevel_init fucntion.
+ * Configures Abort Mode Stack + Interrupt Mode Stack + Supervisor Mode Stack,
+ * reserves 3 blocks, one for each mode and they start at end of IRAM 1.
+ *---------------------------------------------------------------------------*/
+_stack_init:
+    ldr      r2, =_litteral_pool_stack_init
+    ldmia    r2, {r0, r1, r2} /* r0 = TOP_OF_MEMORY (end of IRAM 1);
+    * r1 = ABT_STACK_SIZE;
+    * r2 = IRQ_STACK_SIZE
+    */
+
+    /*- Set up Abort Mode and set ABT Mode Stack */
+    msr      CPSR_c, #ARM_MODE_ABT | I_BIT | F_BIT /* Enter in Mode Abort
+    * and disable IRQ (Interrupt) and FIQ (Fast Interrupt)
+    */
+
+    mov      sp, r0 /* sp (ABT Mode Stack Pointer) = TOP_OF_MEMORY
+    * (end of IRAM 1)
+    */
+
+    /* put r0 with value of the new address for next Stack */
+    sub      r0, r0, r1 /* r0 = r0 - r1 --> r0 = (end of IRAM 1) -
+    * (ABT_STACK_SIZE)
+    */
+
+    /*- Set up Interrupt Mode and set IRQ Mode Stack */
+    msr      CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* Enter in Mode Interrupt
+    * and disable IRQ (Interrupt) and FIQ (Fast Interrupt)
+    */
+
+    mov      sp, r0 /* sp (Interrupt Mode Stack Pointer) =
+    * TOP_OF_MEMORY (end of IRAM 1) - (ABT_STACK_SIZE)
+    */
+
+    sub      r0, r0, r2 /* Put on r0 the new address for next
+    * Stack (Supervisor Mode)
+    */
+
+/*- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack */
+    msr      CPSR_c, #ARM_MODE_SVC | F_BIT
+    mov      sp, r0
+
+/*-----------------------------------------------------------------------------
+ *- Segments initialization
+ *---------------------------------------------------------------------------*/
+/* Copy the vectors section code from the LMA address to the LVA address */
+_init_vectors:
+    ldr      r1, =_litteral_pool_vectors /* Load r1 with the address of
+    * _litteral_pool_vectors
+    */
+    ldmia   r1, {r2, r3, r4} /* r2 = DRAMORIG; r3 = _start_vectors_section;
+    * r4 = _end_vectors_section;
+    */
+1:
+    cmp     r3, r4 /* Compare r3 with r4 (r3 - r4) */
+    ldrcc   r5, [r2], #4 /* if (_start_vectors_section < _end_vectors_section)
+    * { r5 = [r2]; r2 = r2 + 4; }
+    */
+    strcc   r5, [r3], #4 /* if (_start_vectors_section < _end_vectors_section)
+    * { [r3] = r5; r3 = r3 + 4; }
+    */
+    bcc     1b /* loop while (_start_vectors_section < _end_vectors_section) */
+
+/* Clear the bss segment */
+_init_bss:
+    ldr      r2, =_litteral_pool_bss
+    ldmia    r2, {r3, r4} /* r3 = _start_bss_section; r4 = _end_bss_section */
+    mov      r2, #0 /* r2 = 0 */
+1:
+    cmp      r3, r4 /* Compare --> (_start_bss_section - _end_bss_section) */
+    strcc    r2, [r3], #4  /* if (_start_bss_section < _end_bss_section) {
+    * [r3] = 0; r3 = r3 + 4; }
+    */
+    bcc      1b /* loop while _start_bss_section < _end_bss_section */
+
+/* Set up some stack and munge it with 0xdeadbeef */
+    ldr     sp, =stackend
+    mov     r3, sp
+    ldr     r2, =stackbegin
+    ldr     r4, =0xdeadbeef
+
+stackmunge:
+    cmp     r3, r2
+    strhi   r4, [r2], #4
+    bhi     stackmunge
+
+/*-----------------------------------------------------------------------------
+ *- Branch to the main
+ *---------------------------------------------------------------------------*/
+_branch_main:
+    ldr      r0, =main
+    mov      lr, pc
+    bx       r0
+
+/*-----------------------------------------------------------------------------
+ *- Litteral pools
+ *---------------------------------------------------------------------------*/
+_litteral_pool_lowlevel_init:
+    .word    lowlevel_init
+    .word    TOP_OF_MEMORY             /* Default SVC stack after power up */
+
+_litteral_pool_stack_init:
+    .word    TOP_OF_MEMORY             /* Top of the stack */
+    .word    ABT_STACK_SIZE            /* ABT stack size */
+    .word    IRQ_STACK_SIZE            /* IRQ stack size */
+
+_litteral_pool_bss:
+    .word    _start_bss_section
+    .word    _end_bss_section
+
+_litteral_pool_vectors:
+#if defined(BOOTLOADER)
+    .word   (DRAMORIG + DRAMSIZE - 0x100000) /* LMA address of vectors are at
+    * end of DRAM minus 1MByte
+    */
+#else
+    .word   DRAMORIG /* LMA address of vectors are at DRAMORIG */
+#endif
+    .word   _start_vectors_section
+    .word   _end_vectors_section
diff --git a/firmware/target/arm/at91sam/lyre_proto1/debug-lyre_proto1.c b/firmware/target/arm/at91sam/lyre_proto1/debug-lyre_proto1.c
new file mode 100644
index 0000000000..54a262a9ff
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/debug-lyre_proto1.c
@@ -0,0 +1,34 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "at91sam9260.h"
+#include <stdbool.h>
+#include "debug-target.h"
+
+bool __dbg_ports(void)
+{
+    return false;
+}
+
+bool __dbg_hw_info(void)
+{
+    return false;
+}
diff --git a/firmware/target/arm/at91sam/lyre_proto1/debug-target.h b/firmware/target/arm/at91sam/lyre_proto1/debug-target.h
new file mode 100644
index 0000000000..140feafe67
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/debug-target.h
@@ -0,0 +1,26 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include <stdbool.h>
+
+bool __dbg_ports(void);
+bool __dbg_hw_info(void);
+
diff --git a/firmware/target/arm/at91sam/lyre_proto1/kernel-lyre_proto1.c b/firmware/target/arm/at91sam/lyre_proto1/kernel-lyre_proto1.c
new file mode 100644
index 0000000000..4d7167b3ba
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/kernel-lyre_proto1.c
@@ -0,0 +1,78 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "system.h"
+#include "kernel.h"
+#include "timer.h"
+#include "thread.h"
+#include "at91sam9260.h"
+
+/*-----------------------------------------------------------------------------
+ * Function Name       : pitc_handler
+ * Object              : Handler for PITC interrupt
+ *---------------------------------------------------------------------------*/
+void pitc_handler(void)
+{
+    unsigned long pivr = 0;
+    unsigned long pisr = 0;
+
+    /* Read the PISR */
+    pisr = AT91C_PITC_PISR & AT91C_PITC_PITS;
+
+    /* Read the PIVR. It acknowledges the IT */
+    pivr = AT91C_PITC_PIVR;
+
+    /* Run through the list of tick tasks */
+    call_tick_tasks();
+}
+
+void tick_start(unsigned int interval_in_ms)
+{
+    volatile unsigned long pimr = 0;
+
+    /* Configure a resolution of 1 ms */
+    AT91C_PITC_PIMR = MCK_FREQ / (((16 * 1000) - 1) / interval_in_ms);
+
+    /* Enable interrupts */
+    /* Disable the interrupt on the interrupt controller */
+    AT91C_AIC_IDCR = (1 << AT91C_ID_SYS);
+
+    /* Save the interrupt handler routine pointer and the interrupt priority */
+    AT91C_AIC_SVR(AT91C_ID_SYS) = (unsigned long) pitc_handler;
+
+    /* Store the Source Mode Register */
+    AT91C_AIC_SMR(AT91C_ID_SYS) = AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE | \
+    AT91C_AIC_PRIOR_LOWEST;
+    /* Clear the interrupt on the interrupt controller */
+    AT91C_AIC_ICCR = (1 << AT91C_ID_SYS);
+
+    /* Enable the interrupt on the interrupt controller */
+    AT91C_AIC_IECR = (1 << AT91C_ID_SYS);
+
+    /* Enable the interrupt on the pit */
+    pimr = AT91C_PITC_PIMR;
+    AT91C_PITC_PIMR = pimr | AT91C_PITC_PITIEN;
+
+    /* Enable the pit */
+    pimr = AT91C_PITC_PIMR;
+    AT91C_PITC_PIMR = pimr | AT91C_PITC_PITEN;
+}
diff --git a/firmware/target/arm/at91sam/lyre_proto1/lcd-lyre_proto1.c b/firmware/target/arm/at91sam/lyre_proto1/lcd-lyre_proto1.c
new file mode 100644
index 0000000000..3ace8e791d
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/lcd-lyre_proto1.c
@@ -0,0 +1,27 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/* Update the display.
+   This must be called after all other LCD functions that change the display */
+void lcd_update(void)
+{
+
+}
diff --git a/firmware/target/arm/at91sam/lyre_proto1/lcd-target.h b/firmware/target/arm/at91sam/lyre_proto1/lcd-target.h
new file mode 100644
index 0000000000..5008bd861d
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/lcd-target.h
@@ -0,0 +1,24 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+void lcd_update_rect(int x, int y, int width, int height);
+
+
diff --git a/firmware/target/arm/at91sam/lyre_proto1/system-lyre_proto1.c b/firmware/target/arm/at91sam/lyre_proto1/system-lyre_proto1.c
new file mode 100644
index 0000000000..e91ef7a918
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/system-lyre_proto1.c
@@ -0,0 +1,150 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/* Include Standard files */
+#include "at91sam9260.h"
+#include "debug-target.h"
+#include "config.h"
+
+/*-----------------------------------------------------------------------------
+ * Function Name       : default_spurious_handler
+ * Object              : default handler for spurious interrupt
+ *---------------------------------------------------------------------------*/
+void default_spurious_handler(void)
+{
+    while (1);
+}
+
+/*-----------------------------------------------------------------------------
+ * Function Name       : default_fiq_handler
+ * Object              : default handler for fast interrupt
+ *---------------------------------------------------------------------------*/
+void default_fiq_handler(void)
+{
+    while (1);
+}
+
+/*-----------------------------------------------------------------------------
+ * Function Name       : default_irq_handler
+ * Object              : default handler for irq
+ *---------------------------------------------------------------------------*/
+void default_irq_handler(void)
+{
+#if defined(BOOTLOADER)
+    while (1);
+#endif
+}
+
+/*-----------------------------------------------------------------------------
+ * Function Name     : lowlevel_init
+ * Object            : This function performs very low level HW initialization
+ *                     this function can use a Stack, depending the compilation
+ *                     optimization mode
+ *---------------------------------------------------------------------------*/
+void lowlevel_init(void)
+{
+    unsigned char i = 0;
+
+    /* void default_fiq_handler(void)
+     * Init PMC Step 1. Enable Main Oscillator
+     * Main Oscillator startup time is board specific:
+     * Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms
+     * (0x40 for AT91C_CKGR_OSCOUNT field)
+     */
+    AT91C_PMC_MOR = (((AT91C_CKGR_OSCOUNT & (0x40 << 8)) | AT91C_CKGR_MOSCEN));
+    /* Wait Main Oscillator stabilization */
+    while (!(AT91C_PMC_SR & AT91C_PMC_MOSCS));
+
+    /* Init PMC Step 2.
+     * Set PLLA to 198,608MHz
+     * PLL Startup time depends on PLL RC filter: worst case is choosen.
+     *
+     * Crystal frequency = 18.432MHz; PLLA = (18.432 * 96) / 9 = 198,608MHz.
+     */
+
+    AT91C_PMC_PLLAR = (1 << 29)       |
+                      (0x60 << 16)    | /* MULA = 96 */
+                      (0x2 << 14)     |
+                      (0x3f << 8)     |
+                      (0x09); /* DIVA = 9 */
+
+    /* Wait for PLLA stabilization */
+    while (!(AT91C_PMC_SR & AT91C_PMC_LOCKA));
+    /* Wait until the master clock is established for the case we already */
+    /* turn on the PLLA */
+    while (!(AT91C_PMC_SR & AT91C_PMC_MCKRDY));
+
+    /* Init PMC Step 3.
+     * Processor Clock = 198,608MHz (PLLA); Master clock =
+     * (198,608MHz (PLLA))/2 = 98,304MHz.
+     * The PMC_MCKR register must not be programmed in a single write operation
+     * (see. Product Errata Sheet)
+     */
+    AT91C_PMC_MCKR = AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;
+    /* Wait until the master clock is established */
+    while (!(AT91C_PMC_SR & AT91C_PMC_MCKRDY));
+
+    AT91C_PMC_MCKR |= AT91C_PMC_CSS_PLLA_CLK;
+    /* Wait until the master clock is established */
+    while (!(AT91C_PMC_SR & AT91C_PMC_MCKRDY));
+
+    /* Reset AIC: assign default handler for each interrupt source
+     */
+
+    /* Disable the interrupt on the interrupt controller */
+    AT91C_AIC_IDCR = (1 << AT91C_ID_SYS);
+
+    /* Assign default handler for each IRQ source */
+    AT91C_AIC_SVR(AT91C_ID_FIQ) = (int) default_fiq_handler;
+    for (i = 1; i < 31; i++)
+    {
+        AT91C_AIC_SVR(i) = (int) default_irq_handler;
+    }
+    AT91C_AIC_SPU = (unsigned int) default_spurious_handler;
+
+    /* Perform 8 IT acknoledge (write any value in EOICR) */
+
+/* The End of Interrupt Command Register (AIC_EOICR) must be written in order
+to indicate to the AIC that the current interrupt is finished. This causes the
+current level to be popped from the stack, restoring the previous current level
+if one exists on the stack. If another interrupt is pending, with lower or
+equal priority than the old current level but with higher priority than the new
+current level, the nIRQ line is re-asserted, but the interrupt sequence does
+not immediately start because the “I” bit is set in the core.
+SPSR_irq is restored. Finally, the saved value of the link register is restored
+directly into the PC. This has the effect of returning from the interrupt to
+whatever was being executed before, and of loading the CPSR with the stored
+SPSR, masking or unmasking the interrupts depending on the state saved in
+SPSR_irq. */
+    for (i = 0; i < 8 ; i++)
+    {
+        AT91C_AIC_EOICR = 0;
+    }
+
+    /* Enable the interrupt on the interrupt controller */
+    AT91C_AIC_IECR = (1 << AT91C_ID_SYS);
+
+    /* Disable Watchdog */
+    AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS;
+
+    /* Remap */
+    AT91C_MATRIX_MRCR = AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D;
+}
diff --git a/firmware/target/arm/at91sam/lyre_proto1/system-target.h b/firmware/target/arm/at91sam/lyre_proto1/system-target.h
new file mode 100644
index 0000000000..479614f634
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/system-target.h
@@ -0,0 +1,29 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef SYSTEM_TARGET_H
+#define SYSTEM_TARGET_H
+
+#include "system-arm.h"
+
+void system_init(void);
+
+#endif /* SYSTEM_TARGET_H */
diff --git a/firmware/target/arm/at91sam/lyre_proto1/timer-lyre_proto1.c b/firmware/target/arm/at91sam/lyre_proto1/timer-lyre_proto1.c
new file mode 100644
index 0000000000..5924438d10
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/timer-lyre_proto1.c
@@ -0,0 +1,123 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "cpu.h"
+#include "system.h"
+#include "timer.h"
+#include "logf.h"
+#include "at91sam9260.h"
+
+/*-----------------------------------------------------------------------------
+ * Function Name       : pitc_handler
+ * Object              : Handler for PITC interrupt
+ *---------------------------------------------------------------------------*/
+void pitc_handler(void)
+{
+    unsigned long pivr = 0;
+    unsigned long pisr = 0;
+
+    /* Read the PISR */
+    pisr = AT91C_PITC_PISR & AT91C_PITC_PITS;
+
+    if (pisr != 0)
+    {
+        /* Read the PIVR. It acknowledges the IT */
+        pivr = AT91C_PITC_PIVR;
+
+        if (pfn_timer != NULL)
+            pfn_timer();
+    }
+}
+
+bool __timer_set(long cycles, bool start)
+{
+    if (cycles < 1000) /* Max value on PITC?? */
+    {
+        if (start && pfn_unregister != NULL)
+        {
+            pfn_unregister();
+            pfn_unregister = NULL;
+        }
+
+        /* Configure a resolution of <cycles> ms */
+        AT91C_PITC_PIMR = MCK_FREQ / ( 16 * cycles) - 1;
+
+        return true;
+    }
+
+    return false;
+}
+
+bool __timer_register(void)
+{
+    bool retval = true;
+    volatile unsigned long pimr = 0;
+
+    /* Configure a resolution of 1 ms */
+    AT91C_PITC_PIMR = MCK_FREQ / (16 * 1000) - 1;
+
+    /* Enable interrupts */
+    /* Disable the interrupt on the interrupt controller */
+    AT91C_AIC_IDCR = (1 << AT91C_ID_SYS);
+
+    /* Save the interrupt handler routine pointer and the interrupt priority */
+    AT91C_AIC_SVR(AT91C_ID_SYS) = (unsigned long) pitc_handler;
+    /* Store the Source Mode Register */
+    AT91C_AIC_SMR(AT91C_ID_SYS) = AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE | \
+    AT91C_AIC_PRIOR_LOWEST;
+    /* Clear the interrupt on the interrupt controller */
+    AT91C_AIC_ICCR = (1 << AT91C_ID_SYS);
+
+    /* Enable the interrupt on the interrupt controller */
+    AT91C_AIC_IECR = (1 << AT91C_ID_SYS);
+
+    /* Enable the interrupt on the pit */
+    pimr = AT91C_PITC_PIMR;
+    AT91C_PITC_PIMR = pimr | AT91C_PITC_PITIEN;
+
+    /* Enable the pit */
+    pimr = AT91C_PITC_PIMR;
+    AT91C_PITC_PIMR = pimr | AT91C_PITC_PITEN;
+
+    return retval;
+}
+
+void __timer_unregister(void)
+{
+    volatile unsigned long pimr = 0;
+
+    /* Disable the interrupt on the interrupt controller */
+    AT91C_AIC_IDCR = (1 << AT91C_ID_SYS);
+
+    /* Clear the interrupt on the interrupt controller */
+    AT91C_AIC_ICCR = (1 << AT91C_ID_SYS);
+
+    /* Disable the interrupt on the pit */
+    pimr = AT91C_PITC_PIMR;
+    pimr &= ~AT91C_PITC_PITIEN;
+    AT91C_PITC_PIMR = pimr;
+
+    /* Disable the pit */
+    pimr = AT91C_PITC_PIMR;
+    pimr &= ~AT91C_PITC_PITEN;
+    AT91C_PITC_PIMR = pimr;
+}
diff --git a/firmware/target/arm/at91sam/lyre_proto1/timer-target.h b/firmware/target/arm/at91sam/lyre_proto1/timer-target.h
new file mode 100644
index 0000000000..d16577b0de
--- /dev/null
+++ b/firmware/target/arm/at91sam/lyre_proto1/timer-target.h
@@ -0,0 +1,42 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ *
+ *
+ * Copyright (C) 2009 by Jorge Pinto
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef TIMER_TARGET_H
+#define TIMER_TARGET_H
+
+/* timer is based on PCLK and minimum division is 2 */
+#define TIMER_FREQ (49156800/2)
+
+bool __timer_set(long cycles, bool set);
+bool __timer_register(void);
+void __timer_unregister(void);
+
+#define __TIMER_SET(cycles, set) \
+    __timer_set(cycles, set)
+
+#define __TIMER_REGISTER(reg_prio, unregister_callback, cycles, \
+                              int_prio, timer_callback) \
+    __timer_register()
+
+#define __TIMER_UNREGISTER(...) \
+    __timer_unregister()
+
+#endif /* TIMER_TARGET_H */
diff --git a/tools/configure b/tools/configure
index 04954ccb35..b4400dd7fa 100755
--- a/tools/configure
+++ b/tools/configure
@@ -750,10 +750,9 @@ cat <<EOF
                                HDD1830           ==Logik==
  ==Onda==                                        80) DAX 1GB MP3/DAB
  120) VX747               ==Meizu==
- 121) VX767               110) M6SL
- 122) VX747+              111) M6SP
+ 121) VX767               110) M6SL              ==Lyre project==
+ 122) VX747+              111) M6SP              130) Lyre proto 1
                           112) M3
-
 EOF
 
   buildfor=`input`;
@@ -2022,6 +2021,28 @@ fi
     t_manufacturer="ingenic_jz47xx"
     t_model="onda_vx747"
     ;;
+    
+    130|lyre_proto1)
+    target_id=56
+    modelname="lyre_proto1"
+    target="-DLYRE_PROTO1"
+    memory=64
+    arm926ejscc
+    tool="cp"
+    bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
+    bmp2rb_native="$rootdir/tools/bmp2rb -f 4"
+    output="rockbox.lyre"
+    appextra="recorder:gui"
+    plugins=""
+    swcodec="yes"
+    toolset=$scramblebitmaptools
+    boottool="cp"
+    bootoutput="bootloader-proto1.lyre"
+    # architecture, manufacturer and model for the target-tree build
+    t_cpu="arm"
+    t_manufacturer="at91sam"
+    t_model="lyre_proto1"
+    ;;
 
    *)
     echo "Please select a supported target platform!"