x1000: Support GD5F1GQ5xExx NAND chips

This is basically identical to the GD5F1GQ4xExx series, except for
the addition of double-data-rate transfer modes (which are useless
for us). These devices may be found in some Surfans F20s.

Change-Id: I2c04c86bd88f2e27d813de7fe01712ce365ba077

1 files changed, 3 insertions, 0 deletions

diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c
index a0efbb2cbe..af0f972eae 100644
--- a/firmware/target/mips/ingenic_x1000/nand-x1000.c
+++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c
@@ -94,6 +94,7 @@ static const struct nand_chip chip_gd5f1gq4xexx = {
 };
 
 #define chip_ds35x1gaxxx chip_gd5f1gq4xexx
+#define chip_gd5f1gq5xexxg chip_gd5f1gq4xexx
 
 const struct nand_chip_id supported_nand_chips[] = {
     NAND_CHIP_ID(&chip_ato25d1ga, NAND_READID_ADDR, 0x9b, 0x12),
@@ -102,6 +103,8 @@ const struct nand_chip_id supported_nand_chips[] = {
     NAND_CHIP_ID(&chip_gd5f1gq4xexx, NAND_READID_ADDR, 0xc8, 0xc1),
     NAND_CHIP_ID(&chip_ds35x1gaxxx, NAND_READID_ADDR, 0xe5, 0x71), /* 3.3 V */
     NAND_CHIP_ID(&chip_ds35x1gaxxx, NAND_READID_ADDR, 0xe5, 0x21), /* 1.8 V */
+    NAND_CHIP_ID(&chip_gd5f1gq5xexxg, NAND_READID_ADDR, 0xc8, 0x51), /* 3.3 V */
+    NAND_CHIP_ID(&chip_gd5f1gq5xexxg, NAND_READID_ADDR, 0xc8, 0x41), /* 1.8 V */
 };
 
 const size_t nr_supported_nand_chips = ARRAYLEN(supported_nand_chips);