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| author | Jens Arnold <amiconn@rockbox.org> | 2006-12-09 11:36:40 +0000 |
|---|---|---|
| committer | Jens Arnold <amiconn@rockbox.org> | 2006-12-09 11:36:40 +0000 |
| commit | 81f76f21d6ec2e49cd4d3e942d72fcab52947185 (patch) | |
| tree | 93afadfaae1df35d5404695e319fc527f24045d1 | |
| parent | 7ccb5054889b8faba3af1455ff067756c3fdfa65 (diff) | |
| download | rockbox-81f76f21d6ec2e49cd4d3e942d72fcab52947185.tar.gz rockbox-81f76f21d6ec2e49cd4d3e942d72fcab52947185.zip | |
Fix some comments, and make code consistent with comments (CSMR2 was set to 1M instead of 64K).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11698 a1c6a512-1295-4272-9138-f99709370657
| -rw-r--r-- | firmware/target/coldfire/crt0.S | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/firmware/target/coldfire/crt0.S b/firmware/target/coldfire/crt0.S index a0e948486e..7fc389c23d 100644 --- a/firmware/target/coldfire/crt0.S +++ b/firmware/target/coldfire/crt0.S | |||
| @@ -72,12 +72,11 @@ start: | |||
| 72 | /* Chip select 2 - ATA controller */ | 72 | /* Chip select 2 - ATA controller */ |
| 73 | move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */ | 73 | move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */ |
| 74 | move.l %d0,(0x098,%a0) | 74 | move.l %d0,(0x098,%a0) |
| 75 | move.l #0x000f0001,%d0 /* CSMR2 - 64K, Only data access */ | 75 | moveq.l #0x1,%d0 /* CSMR2 - 64K */ |
| 76 | move.l %d0,(0x09c,%a0) | 76 | move.l %d0,(0x09c,%a0) |
| 77 | move.l #0x00000080,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */ | 77 | move.l #0x00000080,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */ |
| 78 | move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states. | 78 | move.l %d0,(0x0a0,%a0) /* wait states are handled by the coldfire |
| 79 | We have to be careful with the access times, | 79 | * IDE interface logic. */ |
| 80 | since IORDY isn't connected to the HDD. */ | ||
| 81 | 80 | ||
| 82 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 81 | #if CONFIG_USBOTG == USBOTG_ISP1362 |
| 83 | /* Chip select 3 - USBOTG controller */ | 82 | /* Chip select 3 - USBOTG controller */ |