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author | Boris Gjenero <dreamlayers@rockbox.org> | 2009-04-06 02:46:42 +0000 |
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committer | Boris Gjenero <dreamlayers@rockbox.org> | 2009-04-06 02:46:42 +0000 |
commit | 7c6194078ca607bd5f364e139ba871b3e4ec0204 (patch) | |
tree | 0c3b729a4bb77806abc92cb26d8e119466bd8cde | |
parent | 02b9c65ea314066b20cc4c391e6e1e69035924c9 (diff) | |
download | rockbox-7c6194078ca607bd5f364e139ba871b3e4ec0204.tar.gz rockbox-7c6194078ca607bd5f364e139ba871b3e4ec0204.zip |
FS#10086 - Playback and recording sample rate setting on the 5G iPod
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20635 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/drivers/audio/wm8758.c | 49 | ||||
-rw-r--r-- | firmware/export/config-ipodvideo.h | 6 | ||||
-rw-r--r-- | firmware/export/wm8758.h | 1 |
3 files changed, 44 insertions, 12 deletions
diff --git a/firmware/drivers/audio/wm8758.c b/firmware/drivers/audio/wm8758.c index b8bf0906e3..bb05960ced 100644 --- a/firmware/drivers/audio/wm8758.c +++ b/firmware/drivers/audio/wm8758.c | |||
@@ -172,20 +172,49 @@ void audiohw_close(void) | |||
172 | /* Note: Disable output before calling this function */ | 172 | /* Note: Disable output before calling this function */ |
173 | void audiohw_set_frequency(int fsel) | 173 | void audiohw_set_frequency(int fsel) |
174 | { | 174 | { |
175 | /**** We force 44.1KHz for now. ****/ | 175 | /* CLKCTRL_MCLKDIV_MASK and ADDCTRL_SR_MASK don't overlap, |
176 | (void)fsel; | 176 | so they can both fit in one byte. Bit 0 selects PLL |
177 | configuration via pll_setups. | ||
178 | */ | ||
179 | static const unsigned char freq_setups[HW_NUM_FREQ] = | ||
180 | { | ||
181 | [HW_FREQ_48] = CLKCTRL_MCLKDIV_2 | ADDCTRL_SR_48kHz | 1, | ||
182 | [HW_FREQ_44] = CLKCTRL_MCLKDIV_2 | ADDCTRL_SR_48kHz, | ||
183 | [HW_FREQ_32] = CLKCTRL_MCLKDIV_3 | ADDCTRL_SR_32kHz | 1, | ||
184 | [HW_FREQ_24] = CLKCTRL_MCLKDIV_4 | ADDCTRL_SR_24kHz | 1, | ||
185 | [HW_FREQ_22] = CLKCTRL_MCLKDIV_4 | ADDCTRL_SR_24kHz, | ||
186 | [HW_FREQ_16] = CLKCTRL_MCLKDIV_6 | ADDCTRL_SR_16kHz | 1, | ||
187 | [HW_FREQ_12] = CLKCTRL_MCLKDIV_8 | ADDCTRL_SR_12kHz | 1, | ||
188 | [HW_FREQ_11] = CLKCTRL_MCLKDIV_8 | ADDCTRL_SR_12kHz, | ||
189 | [HW_FREQ_8] = CLKCTRL_MCLKDIV_12 | ADDCTRL_SR_8kHz | 1 | ||
190 | }; | ||
191 | |||
192 | /* Each PLL configuration is an array consisting of | ||
193 | { PLLN, PLLK1, PLLK2, PLLK3 }. The WM8983 datasheet requires | ||
194 | 5 < PLLN < 13, and states optimum is PLLN = 8, f2 = 90 MHz | ||
195 | */ | ||
196 | static const unsigned short pll_setups[2][4] = | ||
197 | { | ||
198 | /* f1 = 12 MHz, R = 7.5264, f2 = 90.3168 MHz, fPLLOUT = 22.5792 MHz */ | ||
199 | { PLLN_PLLPRESCALE | 0x7, 0x21, 0x161, 0x26 }, | ||
200 | /* f1 = 12 MHz, R = 8.192, f2 = 98.304 MHz, fPLLOUT = 24.576 MHz */ | ||
201 | { PLLN_PLLPRESCALE | 0x8, 0xC, 0x93, 0xE9 } | ||
202 | }; | ||
203 | |||
204 | int i; | ||
177 | 205 | ||
178 | /* setup PLL for MHZ=11.2896 */ | 206 | /* PLLN, PLLK1, PLLK2, PLLK3 are contiguous (at 0x24 to 0x27) */ |
179 | wmcodec_write(PLLN, PLLN_PLLPRESCALE | 0x7); | 207 | for (i = 0; i < 4; i++) |
180 | wmcodec_write(PLLK1, 0x21); | 208 | wmcodec_write(PLLN + i, pll_setups[freq_setups[fsel] & 1][i]); |
181 | wmcodec_write(PLLK2, 0x161); | ||
182 | wmcodec_write(PLLK3, 0x26); | ||
183 | 209 | ||
184 | /* set clock div */ | 210 | /* CLKCTRL_MCLKDIV divides fPLLOUT to get SYSCLK (256 * sample rate) */ |
185 | wmcodec_write(CLKCTRL, CLKCTRL_CLKSEL | CLKCTRL_MCLKDIV_2 | 211 | wmcodec_write(CLKCTRL, CLKCTRL_CLKSEL |
212 | | (freq_setups[fsel] & CLKCTRL_MCLKDIV_MASK) | ||
186 | | CLKCTRL_BCLKDIV_2 | CLKCTRL_MS); | 213 | | CLKCTRL_BCLKDIV_2 | CLKCTRL_MS); |
187 | 214 | ||
188 | wmcodec_write(ADDCTRL, ADDCTRL_SR_48kHz | ADDCTRL_SLOWCLKEN); | 215 | /* set ADC and DAC filter characteristics according to sample rate */ |
216 | wmcodec_write(ADDCTRL, (freq_setups[fsel] & ADDCTRL_SR_MASK) | ||
217 | | ADDCTRL_SLOWCLKEN); | ||
189 | /* SLOWCLK enabled for zero cross timeout to work */ | 218 | /* SLOWCLK enabled for zero cross timeout to work */ |
190 | } | 219 | } |
191 | 220 | ||
diff --git a/firmware/export/config-ipodvideo.h b/firmware/export/config-ipodvideo.h index 0ad3b5c7f2..c9f97dcea5 100644 --- a/firmware/export/config-ipodvideo.h +++ b/firmware/export/config-ipodvideo.h | |||
@@ -21,10 +21,12 @@ | |||
21 | #define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN) | 21 | #define INPUT_SRC_CAPS (SRC_CAP_MIC | SRC_CAP_LINEIN) |
22 | 22 | ||
23 | /* define the bitmask of hardware sample rates */ | 23 | /* define the bitmask of hardware sample rates */ |
24 | #define HW_SAMPR_CAPS (SAMPR_CAP_44) | 24 | #define HW_SAMPR_CAPS (SAMPR_CAP_48 | SAMPR_CAP_44 | SAMPR_CAP_32 | \ |
25 | SAMPR_CAP_24 | SAMPR_CAP_22 | SAMPR_CAP_16 | \ | ||
26 | SAMPR_CAP_12 | SAMPR_CAP_11 | SAMPR_CAP_8) | ||
25 | 27 | ||
26 | /* define the bitmask of recording sample rates */ | 28 | /* define the bitmask of recording sample rates */ |
27 | #define REC_SAMPR_CAPS (SAMPR_CAP_44) | 29 | #define REC_SAMPR_CAPS HW_SAMPR_CAPS |
28 | 30 | ||
29 | /* define this if you have a bitmap LCD display */ | 31 | /* define this if you have a bitmap LCD display */ |
30 | #define HAVE_LCD_BITMAP | 32 | #define HAVE_LCD_BITMAP |
diff --git a/firmware/export/wm8758.h b/firmware/export/wm8758.h index 2c7c9e109d..29304b8794 100644 --- a/firmware/export/wm8758.h +++ b/firmware/export/wm8758.h | |||
@@ -107,6 +107,7 @@ extern void audiohw_set_mixer_vol(int channel1, int channel2); | |||
107 | #define CLKCTRL_MCLKDIV_6 (5 << 5) | 107 | #define CLKCTRL_MCLKDIV_6 (5 << 5) |
108 | #define CLKCTRL_MCLKDIV_8 (6 << 5) | 108 | #define CLKCTRL_MCLKDIV_8 (6 << 5) |
109 | #define CLKCTRL_MCLKDIV_12 (7 << 5) | 109 | #define CLKCTRL_MCLKDIV_12 (7 << 5) |
110 | #define CLKCTRL_MCLKDIV_MASK (7 << 5) | ||
110 | #define CLKCTRL_CLKSEL (1 << 8) | 111 | #define CLKCTRL_CLKSEL (1 << 8) |
111 | 112 | ||
112 | #define ADDCTRL 0x07 | 113 | #define ADDCTRL 0x07 |