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author | Jack Halpin <jack.halpin@gmail.com> | 2009-12-17 19:17:53 +0000 |
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committer | Jack Halpin <jack.halpin@gmail.com> | 2009-12-17 19:17:53 +0000 |
commit | 7bce743218324bd565ffcbe161cb04c90bc9e2e3 (patch) | |
tree | 3d22dea5bf979c3d9ca2273879a5bb11940413b3 | |
parent | 54e163a5a43f24e8d0d76cf038e5eeb636f77c4f (diff) | |
download | rockbox-7bce743218324bd565ffcbe161cb04c90bc9e2e3.tar.gz rockbox-7bce743218324bd565ffcbe161cb04c90bc9e2e3.zip |
Sansa AMS: Revert 4 bit widebus
For some reason 4 bit widebus is creating issues when writing to the .rockbox directory so revert 4 bit widebus and the revision to the write delay that was added as a fix.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24054 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | firmware/target/arm/as3525/ata_sd_as3525.c | 33 |
1 files changed, 2 insertions, 31 deletions
diff --git a/firmware/target/arm/as3525/ata_sd_as3525.c b/firmware/target/arm/as3525/ata_sd_as3525.c index 07ae44a962..6513750652 100644 --- a/firmware/target/arm/as3525/ata_sd_as3525.c +++ b/firmware/target/arm/as3525/ata_sd_as3525.c | |||
@@ -376,31 +376,6 @@ static int sd_init_card(const int drive) | |||
376 | return -10; | 376 | return -10; |
377 | mci_delay(); | 377 | mci_delay(); |
378 | 378 | ||
379 | #ifndef BOOTLOADER | ||
380 | /* Switch to to 4 bit widebus mode */ | ||
381 | if(sd_wait_for_state(drive, SD_TRAN) < 0) | ||
382 | return -11; | ||
383 | mci_delay(); | ||
384 | /* CMD55 */ | ||
385 | if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_ARG, NULL)) | ||
386 | return -12; | ||
387 | mci_delay(); | ||
388 | /* ACMD6 */ | ||
389 | if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_ARG, NULL)) | ||
390 | return -13; | ||
391 | mci_delay(); | ||
392 | /* CMD55 */ | ||
393 | if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_ARG, NULL)) | ||
394 | return -14; | ||
395 | mci_delay(); | ||
396 | /* ACMD42 */ | ||
397 | if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_ARG, NULL)) | ||
398 | return -15; | ||
399 | mci_delay(); | ||
400 | /* Now that card is widebus make controller widebus also */ | ||
401 | MCI_CLOCK(drive) |= MCI_CLOCK_WIDEBUS; | ||
402 | #endif | ||
403 | |||
404 | /* | 379 | /* |
405 | * enable bank switching | 380 | * enable bank switching |
406 | * without issuing this command, we only have access to 1/4 of the blocks | 381 | * without issuing this command, we only have access to 1/4 of the blocks |
@@ -775,17 +750,13 @@ static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start, | |||
775 | dma_enable_channel(0, dma_buf, MCI_FIFO(drive), | 750 | dma_enable_channel(0, dma_buf, MCI_FIFO(drive), |
776 | (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT, | 751 | (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT, |
777 | DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL); | 752 | DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL); |
778 | #if defined(HAVE_MULTIDRIVE) | 753 | |
779 | /*Small delay for writes prevents data crc failures at lower freqs*/ | 754 | /*Small delay for writes prevents data crc failures at lower freqs*/ |
780 | if(!hs_card) | 755 | if((drive == SD_SLOT_AS3525) && !hs_card) |
781 | { | 756 | { |
782 | int write_delay = 125; | 757 | int write_delay = 125; |
783 | while(write_delay--); | 758 | while(write_delay--); |
784 | } | 759 | } |
785 | #else | ||
786 | int write_delay = 125; | ||
787 | while(write_delay--); | ||
788 | #endif | ||
789 | } | 760 | } |
790 | else | 761 | else |
791 | dma_enable_channel(0, MCI_FIFO(drive), dma_buf, | 762 | dma_enable_channel(0, MCI_FIFO(drive), dma_buf, |