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author | Marcin Bukat <marcin.bukat@gmail.com> | 2011-09-06 12:39:58 +0000 |
---|---|---|
committer | Marcin Bukat <marcin.bukat@gmail.com> | 2011-09-06 12:39:58 +0000 |
commit | 77a82ad56ab8aa923f47c908ac10b167c8051cf3 (patch) | |
tree | 2b3013433357d83b5d8ac8251e33fe850b3a03d6 | |
parent | 6d5671a8d8199c7fd04490fce5098b23b893c528 (diff) | |
download | rockbox-77a82ad56ab8aa923f47c908ac10b167c8051cf3.tar.gz rockbox-77a82ad56ab8aa923f47c908ac10b167c8051cf3.zip |
rk27load - fix indentation
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30460 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | utils/rk27utils/rk27load/stage1/main.S | 46 | ||||
-rw-r--r-- | utils/rk27utils/rk27load/stage2/crt0.S | 93 | ||||
-rw-r--r-- | utils/rk27utils/rk27load/stage2/irq.S | 143 | ||||
-rw-r--r-- | utils/rk27utils/rk27load/stage2/main.S | 141 |
4 files changed, 213 insertions, 210 deletions
diff --git a/utils/rk27utils/rk27load/stage1/main.S b/utils/rk27utils/rk27load/stage1/main.S index 44e7e2f914..d8a3225fff 100644 --- a/utils/rk27utils/rk27load/stage1/main.S +++ b/utils/rk27utils/rk27load/stage1/main.S | |||
@@ -2,41 +2,41 @@ | |||
2 | .global start | 2 | .global start |
3 | 3 | ||
4 | start: | 4 | start: |
5 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ | 5 | msr cpsr_c,#0xd3 /* enter supervisor mode, disable IRQ/FIQ */ |
6 | 6 | ||
7 | pll_setup: | 7 | pll_setup: |
8 | mov r0, #0x18000000 | 8 | mov r0,#0x18000000 |
9 | add r0, r0, #0x1c000 | 9 | add r0,r0,#0x1c000 |
10 | 10 | ||
11 | /* setup ARM core freq = 200MHz */ | 11 | /* setup ARM core freq = 200MHz */ |
12 | /* AHB bus freq (HCLK) = 100MHz */ | 12 | /* AHB bus freq (HCLK) = 100MHz */ |
13 | /* APB bus freq (PCLK) = 50MHz */ | 13 | /* APB bus freq (PCLK) = 50MHz */ |
14 | ldr r1, [r0,#0x14] /* SCU_DIVCON1 */ | 14 | ldr r1,[r0,#0x14] /* SCU_DIVCON1 */ |
15 | orr r1, #9 /* ARM slow mode, HCLK:PCLK = 2:1 */ | 15 | orr r1,#9 /* ARM slow mode, HCLK:PCLK = 2:1 */ |
16 | str r1, [r0,#0x14] | 16 | str r1,[r0,#0x14] |
17 | 17 | ||
18 | ldr r1,=0x01970c70 /* (1<<24) | (1<<23) | (23<<16) | (199<<4) */ | 18 | ldr r1,=0x01970c70 /* (1<<24) | (1<<23) | (23<<16) | (199<<4) */ |
19 | str r1, [r0,#0x08] | 19 | str r1,[r0,#0x08] |
20 | 20 | ||
21 | ldr r2,=0x40000 | 21 | ldr r2,=0x40000 |
22 | 1: | 22 | 1: |
23 | ldr r1, [r0,#0x2c] /* SCU_STATUS */ | 23 | ldr r1,[r0,#0x2c] /* SCU_STATUS */ |
24 | tst r1, #1 /* ARM pll lock */ | 24 | tst r1,#1 /* ARM pll lock */ |
25 | bne 1f | 25 | bne 1f |
26 | subs r2, #1 | 26 | subs r2,#1 |
27 | bne 1b | 27 | bne 1b |
28 | 1: | 28 | 1: |
29 | ldr r1, [r0,#0x14] /* SCU_DIVCON1 */ | 29 | ldr r1,[r0,#0x14] /* SCU_DIVCON1 */ |
30 | bic r1, #5 /* leave ARM slow mode, ARMclk:HCLK = 2:1 */ | 30 | bic r1,#5 /* leave ARM slow mode, ARMclk:HCLK = 2:1 */ |
31 | str r1, [r0,#0x14] | 31 | str r1,[r0,#0x14] |
32 | 32 | ||
33 | sdram_config: | 33 | sdram_config: |
34 | add r0, r0, #0x94000 /* SDRAM base */ | 34 | add r0,r0, #0x94000 /* SDRAM base */ |
35 | 35 | ||
36 | mov r1, #1 | 36 | mov r1,#1 |
37 | str r1, [r0,#0x10c] /* MCSDR_BASIC Round-robin, SDRAM width 16bits */ | 37 | str r1,[r0,#0x10c] /* MCSDR_BASIC Round-robin, SDRAM width 16bits */ |
38 | 38 | ||
39 | add r1, #0x10 | 39 | add r1,#0x10 |
40 | str r1, [r0,#0x108] /* MCSDR_ADDCFG 12 bits row/9 bits col addr */ | 40 | str r1,[r0,#0x108] /* MCSDR_ADDCFG 12 bits row/9 bits col addr */ |
41 | 41 | ||
42 | mov pc, lr /* we are done, return to bootrom code */ | 42 | mov pc,lr /* we are done, return to bootrom code */ |
diff --git a/utils/rk27utils/rk27load/stage2/crt0.S b/utils/rk27utils/rk27load/stage2/crt0.S index c85477546d..d931123f95 100644 --- a/utils/rk27utils/rk27load/stage2/crt0.S +++ b/utils/rk27utils/rk27load/stage2/crt0.S | |||
@@ -1,55 +1,56 @@ | |||
1 | // | 1 | /* |
2 | // startup code | 2 | * startup code |
3 | // | 3 | * |
4 | // | 4 | */ |
5 | 5 | ||
6 | #define PSR_MODE 0x0000001f | 6 | #define PSR_MODE 0x0000001f |
7 | #define PSR_USR_MODE 0x00000010 | 7 | #define PSR_USR_MODE 0x00000010 |
8 | #define PSR_IRQ_MODE 0x00000012 | 8 | #define PSR_IRQ_MODE 0x00000012 |
9 | #define PSR_SVC_MODE 0x00000013 | 9 | #define PSR_SVC_MODE 0x00000013 |
10 | 10 | ||
11 | #define PSR_INT_MASK 0x000000c0 | 11 | #define PSR_INT_MASK 0x000000c0 |
12 | #define PSR_FIQ_DIS 0x00000040 | 12 | #define PSR_FIQ_DIS 0x00000040 |
13 | #define PSR_IRQ_DIS 0x00000080 | 13 | #define PSR_IRQ_DIS 0x00000080 |
14 | 14 | ||
15 | .section .init.text,"ax",%progbits | 15 | .section .init.text,"ax",%progbits |
16 | .global start | 16 | .global start |
17 | .extern _interrupt_disable | 17 | .extern _interrupt_disable |
18 | 18 | ||
19 | // ----------------------------------------------------- | 19 | /* ----------------------------------------------------- |
20 | // startup code (setup stacks, branch to main) | 20 | * startup code (setup stacks, branch to main) |
21 | // ----------------------------------------------------- | 21 | * ----------------------------------------------------- |
22 | */ | ||
22 | start: | 23 | start: |
23 | // setup IRQ stack | 24 | /* setup IRQ stack */ |
24 | mov r0, #(PSR_IRQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS) | 25 | mov r0,#(PSR_IRQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS) |
25 | msr cpsr, r0 | 26 | msr cpsr,r0 |
26 | ldr sp,=irqstackend | 27 | ldr sp,=irqstackend |
27 | 28 | ||
28 | // setup SVC stack | 29 | /* setup SVC stack */ |
29 | mov r0, #(PSR_SVC_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS) | 30 | mov r0,#(PSR_SVC_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS) |
30 | msr cpsr, r0 | 31 | msr cpsr,r0 |
31 | ldr sp,=stackend | 32 | ldr sp,=stackend |
32 | 33 | ||
33 | // disbale interrupts | 34 | /* disbale interrupts */ |
34 | mrs r0, cpsr | 35 | mrs r0,cpsr |
35 | orr r0, r0, #0xc0 | 36 | orr r0,r0,#0xc0 |
36 | msr cpsr_c, r0 | 37 | msr cpsr_c, r0 |
37 | 38 | ||
38 | // remap | 39 | /* remap */ |
39 | mov r0, #0x18000000 | 40 | mov r0,#0x18000000 |
40 | add r0, r0, #0x1C000 | 41 | add r0,r0,#0x1C000 |
41 | ldr r1,=0xdeadbeef | 42 | ldr r1,=0xdeadbeef |
42 | str r1, [r0, #4] | 43 | str r1,[r0,#4] |
43 | 44 | ||
44 | // relocate itself | 45 | /* relocate itself */ |
45 | ldr r0,=_relocstart | 46 | ldr r0,=_relocstart |
46 | ldr r1,=_relocend | 47 | ldr r1,=_relocend |
47 | ldr r2,=0x0 | 48 | ldr r2,=0x0 |
48 | 1: | 49 | 1: |
49 | cmp r1,r0 | 50 | cmp r1,r0 |
50 | ldrhi r3,[r0],#4 | 51 | ldrhi r3,[r0],#4 |
51 | strhi r3,[r2],#4 | 52 | strhi r3,[r2],#4 |
52 | bhi 1b | 53 | bhi 1b |
53 | 54 | ||
54 | // continue running in SVC (supervisor mode) | 55 | /* continue running in SVC (supervisor mode) */ |
55 | ldr pc,=0x0 | 56 | ldr pc,=0x0 |
diff --git a/utils/rk27utils/rk27load/stage2/irq.S b/utils/rk27utils/rk27load/stage2/irq.S index 043bf185a5..29ffdb49bb 100644 --- a/utils/rk27utils/rk27load/stage2/irq.S +++ b/utils/rk27utils/rk27load/stage2/irq.S | |||
@@ -1,103 +1,102 @@ | |||
1 | .section .text | 1 | .section .text |
2 | .align 4 | 2 | .align 4 |
3 | 3 | ||
4 | .global irq_handler | 4 | .global irq_handler |
5 | #define BUFF_ADDR 0x60800000 | 5 | #define BUFF_ADDR 0x60800000 |
6 | 6 | ||
7 | irq_handler: | 7 | irq_handler: |
8 | stmfd sp!, {r0-r7, ip, lr} | 8 | stmfd sp!,{r0-r7,ip,lr} |
9 | 9 | ||
10 | // get interrupt number | 10 | /* get interrupt number */ |
11 | mov r4, #0x18000000 | 11 | mov r4,#0x18000000 |
12 | add r4, r4, #0x80000 | 12 | add r4,r4,#0x80000 |
13 | ldr r5, [r4, #0x104] | 13 | ldr r5,[r4,#0x104] |
14 | and r5, r5, #0x1f | 14 | and r5,r5,#0x1f |
15 | cmp r5, #0x10 // UDC interrupt | 15 | cmp r5,#0x10 /* UDC interrupt */ |
16 | 16 | ||
17 | bleq udc_irq | 17 | bleq udc_irq |
18 | 18 | ||
19 | // clear pending interrupt | 19 | /* clear pending interrupt */ |
20 | mov r3, #1 | 20 | mov r3,#1 |
21 | mov r2, r3, LSL r5 | 21 | mov r2,r3,LSL r5 |
22 | str r2, [r4, #0x118] | 22 | str r2,[r4,#0x118] |
23 | 23 | ||
24 | ldmfd sp!, {r0-r7, ip, lr} | 24 | ldmfd sp!,{r0-r7,ip,lr} |
25 | subs pc, lr, #4 | 25 | subs pc,lr,#4 |
26 | 26 | ||
27 | udc_irq: | 27 | udc_irq: |
28 | stmfd sp!, {r4-r8, lr} | 28 | stmfd sp!,{r4-r8,lr} |
29 | 29 | ||
30 | // handle usb interrupt | 30 | /* handle usb interrupt */ |
31 | ldr r4,=0x180A0000 | 31 | ldr r4,=0x180A0000 |
32 | ldr r5, [r4, #0x18] // UDC_INTFLAG | 32 | ldr r5,[r4,#0x18] /* UDC_INTFLAG */ |
33 | 33 | ||
34 | // ep0 in intr | 34 | /* ep0 in intr */ |
35 | tst r5, #0x04 | 35 | tst r5,#0x04 |
36 | beq bulk_recv_intr | 36 | beq bulk_recv_intr |
37 | ep0: | ||
38 | ldr r5,[r4,#0x40] | ||
39 | mov r5,r5,lsr #10 | ||
40 | mov r5,r5,lsl #10 /* clear lower 10 bits in TX0STAT */ | ||
41 | str r5,[r4,#0x40] | ||
37 | 42 | ||
38 | // write_reg32(UDC_TX0STAT, read_reg32(UDC_TX0STAT) & ~0x7FF); | 43 | /* set buffer addres in UDC_DMA0LM_OADDR */ |
39 | ldr r5, [r4, #0x40] | 44 | mov r5,#0x60000000 |
40 | mov r5, r5, lsr #10 | 45 | str r5,[r4, #0x3c] |
41 | mov r5, r5, lsl #10 // clear clower 10 bits | ||
42 | str r5, [r4, #0x40] | ||
43 | 46 | ||
44 | // write_reg32(UDC_DMA0LM_OADDR, (uint32_t)(state.ctrlep_data)); | 47 | /* write DMA_START in UDC_DMA0CTLO */ |
45 | mov r5, #0x60000000 | 48 | mov r5,#1 |
46 | str r5, [r4, #0x3c] | 49 | str r5,[r4,#0x38] |
47 | 50 | ||
48 | // write_reg32(UDC_DMA0CTLO, read_reg32(UDC_DMA0CTLO) | ENP_DMA_START); | 51 | ldmfd sp!,{r4-r8,pc} |
49 | mov r5, #1 | ||
50 | str r5, [r4, #0x38] | ||
51 | 52 | ||
52 | ldmfd sp!, {r4-r8, pc} | 53 | /* bulk out interrupt */ |
53 | |||
54 | // bulk out interrupt | ||
55 | bulk_recv_intr: | 54 | bulk_recv_intr: |
56 | tst r5, #0x100 | 55 | tst r5,#0x100 |
57 | ldmeqfd sp!, {r4-r8, pc} | 56 | ldmeqfd sp!,{r4-r8,pc} |
58 | 57 | ||
59 | // read UDC_RX1STAT | 58 | /* read UDC_RX1STAT */ |
60 | ldr r5, [r4, #0x54] | 59 | ldr r5,[r4,#0x54] |
61 | mov r5, r5, lsl #21 | 60 | mov r5,r5,lsl #21 |
62 | mov r5, r5, lsr #21 // r5 = length | 61 | mov r5,r5,lsr #21 /* r5 = length */ |
63 | 62 | ||
64 | ldr r6,=usb_sz | 63 | ldr r6,=usb_sz |
65 | ldr r6, [r6] | 64 | ldr r6,[r6] |
66 | ldr r7, [r6] // r7 = total_code_length expected | 65 | ldr r7,[r6] /* r7 = total_code_length expected */ |
67 | 66 | ||
68 | subs r7, r7, r5 | 67 | subs r7,r7,r5 |
69 | bne usb_bulk_out1_recv | 68 | bne usb_bulk_out1_recv |
70 | 69 | ||
71 | // copy from buff to the begining of the ram | 70 | /* copy from buff to the begining of the ram */ |
72 | ldr r0,=BUFF_ADDR | 71 | ldr r0,=BUFF_ADDR |
73 | ldr r1,[r0,#-4] // size | 72 | ldr r1,[r0,#-4] /* size */ |
74 | 73 | ||
75 | ldr r1,=0x800000 // buffer size | 74 | ldr r1,=0x800000 /* buffer size */ |
76 | 75 | ||
77 | add r1,r1,r0 // end address | 76 | add r1,r1,r0 /* end address */ |
78 | ldr r2,=0x60000000 // destination | 77 | ldr r2,=0x60000000 /* destination */ |
79 | 1: | 78 | 1: |
80 | cmp r1,r0 | 79 | cmp r1,r0 |
81 | ldrhi r3,[r0],#4 | 80 | ldrhi r3,[r0],#4 |
82 | strhi r3,[r2],#4 | 81 | strhi r3,[r2],#4 |
83 | bhi 1b | 82 | bhi 1b |
84 | 83 | ||
85 | // execute user code | 84 | /* execute user code */ |
86 | ldr r0,=0x60000000 | 85 | ldr r0,=0x60000000 |
87 | bx r0 // jump to 0x60000000 | 86 | bx r0 /* jump to 0x60000000 */ |
88 | 87 | ||
89 | usb_bulk_out1_recv: | 88 | usb_bulk_out1_recv: |
90 | str r7, [r6] // size = size - received | 89 | str r7,[r6] /* size = size - received */ |
91 | 90 | ||
92 | ldr r6,=usb_write_addr | 91 | ldr r6,=usb_write_addr |
93 | ldr r7, [r6] | 92 | ldr r7,[r6] |
94 | 93 | ||
95 | add r7, r7, r5 | 94 | add r7,r7,r5 |
96 | str r7, [r6] // usb_write_addr += length | 95 | str r7,[r6] /* usb_write_addr += length */ |
97 | 96 | ||
98 | str r7, [r4, #0x60] // DMA1LM_OADDR = usb_write_addr | 97 | str r7,[r4,#0x60] /* DMA1LM_OADDR = usb_write_addr */ |
99 | 98 | ||
100 | mov r5, #1 | 99 | mov r5,#1 |
101 | str r5, [r4, #0x5c] // DMA1_CTL0 = ENP_DMA_START | 100 | str r5,[r4,#0x5c] /* DMA1_CTL0 = ENP_DMA_START */ |
102 | 101 | ||
103 | ldmfd sp!, {r4-r8, pc} | 102 | ldmfd sp!,{r4-r8,pc} |
diff --git a/utils/rk27utils/rk27load/stage2/main.S b/utils/rk27utils/rk27load/stage2/main.S index c8474b0579..14e83e0d01 100644 --- a/utils/rk27utils/rk27load/stage2/main.S +++ b/utils/rk27utils/rk27load/stage2/main.S | |||
@@ -1,89 +1,92 @@ | |||
1 | .section .text | ||
2 | .align 4 | ||
1 | 3 | ||
2 | .section .text | 4 | .arm |
3 | .align 4 | ||
4 | |||
5 | .arm | ||
6 | |||
7 | .global main | ||
8 | .global _interrupt_disable | ||
9 | .global _interrupt_enable | ||
10 | 5 | ||
11 | .global usb_write_addr | 6 | .global main |
12 | .global usb_sz | 7 | .global _interrupt_disable |
8 | .global _interrupt_enable | ||
13 | 9 | ||
14 | #define BUFF_ADDR 0x60800000 | 10 | .global usb_write_addr |
11 | .global usb_sz | ||
15 | 12 | ||
16 | // ----------------------------------------------------- | 13 | #define BUFF_ADDR 0x60800000 |
17 | // vector table | ||
18 | // ----------------------------------------------------- | ||
19 | ldr pc, =main | ||
20 | ldr pc, =main | ||
21 | ldr pc, =main | ||
22 | ldr pc, =main | ||
23 | ldr pc, =main | ||
24 | ldr pc, =main | ||
25 | ldr pc, =irq_handler | ||
26 | ldr pc, =main | ||
27 | 14 | ||
28 | // ----------------------------------------------------- | 15 | /* ----------------------------------------------------- |
29 | // main | 16 | * vector table |
30 | // ----------------------------------------------------- | 17 | * ----------------------------------------------------- |
18 | */ | ||
19 | ldr pc,=main | ||
20 | ldr pc,=main | ||
21 | ldr pc,=main | ||
22 | ldr pc,=main | ||
23 | ldr pc,=main | ||
24 | ldr pc,=main | ||
25 | ldr pc,=irq_handler | ||
26 | ldr pc,=main | ||
27 | |||
28 | /* ----------------------------------------------------- | ||
29 | * main | ||
30 | * ----------------------------------------------------- | ||
31 | */ | ||
31 | main: | 32 | main: |
32 | // turn on usb interrupts | 33 | /* turn on usb interrupts */ |
33 | mov r0, #0x18000000 | 34 | mov r0,#0x18000000 |
34 | add r0, r0, #0x80000 | 35 | add r0,r0,#0x80000 |
35 | ldr r1, [r0, #0x10c] | 36 | ldr r1,[r0,#0x10c] |
36 | orr r1, r1, #0x10000 | 37 | orr r1,r1,#0x10000 |
37 | str r1, [r0, #0x10c] | 38 | str r1,[r0,#0x10c] |
38 | 39 | ||
39 | // enable usb-bulk | 40 | /* enable usb-bulk */ |
40 | add r0, r0, #0x20000 // R0 = 0x180A0000 (UDC_BASE) | 41 | add r0,r0,#0x20000 /* R0 = 0x180A0000 (UDC_BASE) */ |
41 | 42 | ||
42 | // enable EP1, write_reg32(UDC_RX1CON, (0x1 << 8) | RxACKINTEN | RxEPEN); | 43 | /* enable EP1 */ |
43 | mov r1, #0x190 // bits 8,7,4 -> 0x190 | 44 | mov r1,#0x190 /* bits 8,7,4 -> 0x190 */ |
44 | str r1, [r0, #0x58] | 45 | str r1,[r0,#0x58] |
45 | 46 | ||
46 | // setup receive buffer (must be aligned on dword boundary) | 47 | /* setup receive buffer (must be aligned on dword boundary) */ |
47 | ldr r1,=usb_write_addr // write_reg32(UDC_DMA1LM_OADDR, (uint32_t)rx_buff); | 48 | ldr r1,=usb_write_addr |
48 | ldr r1, [r1] | 49 | ldr r1,[r1] |
49 | str r1, [r0, #0x60] // UDC_DMA1LM_OADDR = usb_write_addr | 50 | str r1,[r0, #0x60] /* UDC_DMA1LM_OADDR = usb_write_addr */ |
50 | 51 | ||
51 | // write_reg32(UDC_DMA1CTRLO, read_reg32(UDC_DMA1CTRLO) | ENP_DMA_START); | 52 | /* write DMA_START in UDC_DMA1CTRLO */ |
52 | ldr r1, [r0, #0x5c] | 53 | ldr r1,[r0,#0x5c] |
53 | orr r1, r1, #2 | 54 | orr r1,r1,#2 |
54 | str r1, [r0, #0x5c] | 55 | str r1,[r0,#0x5c] |
55 | 56 | ||
56 | // enable bulk_out1 interrupt | 57 | /* enable bulk_out1 interrupt */ |
57 | ldr r1, [r0, #0x14] // UDC_ENINT | 58 | ldr r1,[r0,#0x14] /* UDC_ENINT */ |
58 | orr r1, r1, #0x100 // EN_BOUT1_INTR | 59 | orr r1,r1,#0x100 /* EN_BOUT1_INTR */ |
59 | str r1, [r0, #0x14] | 60 | str r1,[r0,#0x14] |
60 | 61 | ||
61 | bl _interrupt_enable | 62 | bl _interrupt_enable |
62 | idle: | 63 | idle: |
63 | b idle | 64 | b idle |
64 | 65 | ||
65 | // ----------------------------------------------------- | 66 | /* ----------------------------------------------------- |
66 | // _interrupt_enable - enables interrupts | 67 | * _interrupt_enable - enables interrupts |
67 | // ----------------------------------------------------- | 68 | * ----------------------------------------------------- |
69 | */ | ||
68 | _interrupt_enable: | 70 | _interrupt_enable: |
69 | mrs r0, cpsr | 71 | mrs r0,cpsr |
70 | bic r0, r0, #0x80 | 72 | bic r0,r0,#0x80 |
71 | msr cpsr_c, r0 | 73 | msr cpsr_c,r0 |
72 | mov pc, lr | 74 | mov pc,lr |
73 | 75 | ||
74 | // ----------------------------------------------------- | 76 | /* ----------------------------------------------------- |
75 | // _interrupt_disable - disables interrupts | 77 | * _interrupt_disable - disables interrupts |
76 | // ----------------------------------------------------- | 78 | * ----------------------------------------------------- |
79 | */ | ||
77 | _interrupt_disable: | 80 | _interrupt_disable: |
78 | mrs r0, cpsr | 81 | mrs r0,cpsr |
79 | orr r0, r0, #0xc0 | 82 | orr r0,r0,#0xc0 |
80 | msr cpsr_c, r0 | 83 | msr cpsr_c,r0 |
81 | mov pc, lr | 84 | mov pc,lr |
82 | 85 | ||
83 | 86 | ||
84 | .section .data | 87 | .section .data |
85 | usb_write_addr: | 88 | usb_write_addr: |
86 | .word (BUFF_ADDR-4) | 89 | .word (BUFF_ADDR-4) |
87 | 90 | ||
88 | usb_sz: | 91 | usb_sz: |
89 | .word (BUFF_ADDR-4) | 92 | .word (BUFF_ADDR-4) |