AMSv2: DBOP frequency divided by 2

After setting new PCLK (96 Mhz) we have too high DBOP (96 / 16 = 6 MHz).
According to datasheet DBOP should be maximum 4 MHz.

Change-Id: I1cbec054f41a76a6f18eadccb902c5b174ad6e3a

1 files changed, 4 insertions, 3 deletions

diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h
index f4bb5568fb..7f6b17eff4 100644
--- a/firmware/target/arm/as3525/clock-target.h
+++ b/firmware/target/arm/as3525/clock-target.h
@@ -86,6 +86,8 @@
 
 
 #define AS3525_DRAM_FREQ        96000000    /* Initial DRAM frequency  */
+#define AS3525_PCLK_FREQ      (AS3525_DRAM_FREQ/1)   /* PCLK divided from DRAM freq */
+#define AS3525_DBOP_FREQ      (AS3525_PCLK_FREQ/2)   /* DBOP divided from PCLK freq */
 
 #else
 /* AS3525v1 */
@@ -113,12 +115,11 @@
 #define AS3525_FCLK_FREQ      248000000            /* Boosted FCLK frequency  */
 #define AS3525_DRAM_FREQ       62000000            /* Initial DRAM frequency  */
 /* AS3525_PCLK_FREQ != AS3525_DRAM_FREQ/1 will boot to white lcd screen */
+#define AS3525_PCLK_FREQ      (AS3525_DRAM_FREQ/1)   /* PCLK divided from DRAM freq */
+#define AS3525_DBOP_FREQ      (AS3525_PCLK_FREQ/1)   /* DBOP divided from PCLK freq */
 
 #endif  /* CONFIG_CPU == AS3525v2 */
 
-#define AS3525_PCLK_FREQ      (AS3525_DRAM_FREQ/1)   /* PCLK divided from DRAM freq */
-
-#define AS3525_DBOP_FREQ      (AS3525_PCLK_FREQ/1)   /* DBOP divided from PCLK freq */
 
 /** ****************************************************************************/