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authorMarcin Bukat <marcin.bukat@gmail.com>2018-09-07 09:43:05 +0200
committerMarcin Bukat <marcin.bukat@gmail.com>2018-09-07 09:43:05 +0200
commit734be0d6aa79e47871bd9746394b2f5c98df5fcf (patch)
tree86a6c70fd1aae4c39b1dd72f2dfe50d49717d855
parentb1ee789f977dece1ba79af2189525abc86f6f4a6 (diff)
downloadrockbox-734be0d6aa79e47871bd9746394b2f5c98df5fcf.tar.gz
rockbox-734be0d6aa79e47871bd9746394b2f5c98df5fcf.zip
MIPS: fix memset()
swr/swl instructions used for word aligning were wrong. This made memset() terribly broken. I can't imagine how it went uncaught for soooo long. Spotted by Solomon Peachy. I run unit tests for alignments 0,1,2,3 size 1, 2, 3, 4, 5, 63, 64, 65, 127, 128, 129; and fill pattern 0x00 and other (since 0 is special case in this implementation). Change-Id: I513a10734335fe97734c10ab5a6c3e3fb3f4687a
Diffstat
-rw-r--r--firmware/asm/mips/memset.S115
-rw-r--r--utils/hwstub/stub/asm/mips/memset.S115
2 files changed, 6 insertions, 224 deletions
diff --git a/firmware/asm/mips/memset.S b/firmware/asm/mips/memset.S
index 8db76d9123..6dfe0bf864 100644
--- a/firmware/asm/mips/memset.S
+++ b/firmware/asm/mips/memset.S
@@ -24,106 +24,6 @@
24#include "config.h" 24#include "config.h"
25#include "mips.h" 25#include "mips.h"
26 26
27#define FILL256(dst, offset, val) \
28 sw val, (offset + 0x00)(dst); \
29 sw val, (offset + 0x04)(dst); \
30 sw val, (offset + 0x08)(dst); \
31 sw val, (offset + 0x0c)(dst); \
32 sw val, (offset + 0x10)(dst); \
33 sw val, (offset + 0x14)(dst); \
34 sw val, (offset + 0x18)(dst); \
35 sw val, (offset + 0x1c)(dst); \
36 sw val, (offset + 0x20)(dst); \
37 sw val, (offset + 0x24)(dst); \
38 sw val, (offset + 0x28)(dst); \
39 sw val, (offset + 0x2c)(dst); \
40 sw val, (offset + 0x30)(dst); \
41 sw val, (offset + 0x34)(dst); \
42 sw val, (offset + 0x38)(dst); \
43 sw val, (offset + 0x3c)(dst); \
44 sw val, (offset + 0x40)(dst); \
45 sw val, (offset + 0x44)(dst); \
46 sw val, (offset + 0x48)(dst); \
47 sw val, (offset + 0x4c)(dst); \
48 sw val, (offset + 0x50)(dst); \
49 sw val, (offset + 0x54)(dst); \
50 sw val, (offset + 0x58)(dst); \
51 sw val, (offset + 0x5c)(dst); \
52 sw val, (offset + 0x60)(dst); \
53 sw val, (offset + 0x64)(dst); \
54 sw val, (offset + 0x68)(dst); \
55 sw val, (offset + 0x6c)(dst); \
56 sw val, (offset + 0x70)(dst); \
57 sw val, (offset + 0x74)(dst); \
58 sw val, (offset + 0x78)(dst); \
59 sw val, (offset + 0x7c)(dst); \
60 sw val, (offset + 0x80)(dst); \
61 sw val, (offset + 0x84)(dst); \
62 sw val, (offset + 0x88)(dst); \
63 sw val, (offset + 0x8c)(dst); \
64 sw val, (offset + 0x90)(dst); \
65 sw val, (offset + 0x94)(dst); \
66 sw val, (offset + 0x98)(dst); \
67 sw val, (offset + 0x9c)(dst); \
68 sw val, (offset + 0xa0)(dst); \
69 sw val, (offset + 0xa4)(dst); \
70 sw val, (offset + 0xa8)(dst); \
71 sw val, (offset + 0xac)(dst); \
72 sw val, (offset + 0xb0)(dst); \
73 sw val, (offset + 0xb4)(dst); \
74 sw val, (offset + 0xb8)(dst); \
75 sw val, (offset + 0xbc)(dst); \
76 sw val, (offset + 0xc0)(dst); \
77 sw val, (offset + 0xc4)(dst); \
78 sw val, (offset + 0xc8)(dst); \
79 sw val, (offset + 0xcc)(dst); \
80 sw val, (offset + 0xd0)(dst); \
81 sw val, (offset + 0xd4)(dst); \
82 sw val, (offset + 0xd8)(dst); \
83 sw val, (offset + 0xdc)(dst); \
84 sw val, (offset + 0xe0)(dst); \
85 sw val, (offset + 0xe4)(dst); \
86 sw val, (offset + 0xe8)(dst); \
87 sw val, (offset + 0xec)(dst); \
88 sw val, (offset + 0xf0)(dst); \
89 sw val, (offset + 0xf4)(dst); \
90 sw val, (offset + 0xf8)(dst); \
91 sw val, (offset + 0xfc)(dst);
92
93#define FILL128(dst, offset, val) \
94 sw val, (offset + 0x00)(dst); \
95 sw val, (offset + 0x04)(dst); \
96 sw val, (offset + 0x08)(dst); \
97 sw val, (offset + 0x0c)(dst); \
98 sw val, (offset + 0x10)(dst); \
99 sw val, (offset + 0x14)(dst); \
100 sw val, (offset + 0x18)(dst); \
101 sw val, (offset + 0x1c)(dst); \
102 sw val, (offset + 0x20)(dst); \
103 sw val, (offset + 0x24)(dst); \
104 sw val, (offset + 0x28)(dst); \
105 sw val, (offset + 0x2c)(dst); \
106 sw val, (offset + 0x30)(dst); \
107 sw val, (offset + 0x34)(dst); \
108 sw val, (offset + 0x38)(dst); \
109 sw val, (offset + 0x3c)(dst); \
110 sw val, (offset + 0x40)(dst); \
111 sw val, (offset + 0x44)(dst); \
112 sw val, (offset + 0x48)(dst); \
113 sw val, (offset + 0x4c)(dst); \
114 sw val, (offset + 0x50)(dst); \
115 sw val, (offset + 0x54)(dst); \
116 sw val, (offset + 0x58)(dst); \
117 sw val, (offset + 0x5c)(dst); \
118 sw val, (offset + 0x60)(dst); \
119 sw val, (offset + 0x64)(dst); \
120 sw val, (offset + 0x68)(dst); \
121 sw val, (offset + 0x6c)(dst); \
122 sw val, (offset + 0x70)(dst); \
123 sw val, (offset + 0x74)(dst); \
124 sw val, (offset + 0x78)(dst); \
125 sw val, (offset + 0x7c)(dst);
126
127#define FILL64(dst, offset, val) \ 27#define FILL64(dst, offset, val) \
128 sw val, (offset + 0x00)(dst); \ 28 sw val, (offset + 0x00)(dst); \
129 sw val, (offset + 0x04)(dst); \ 29 sw val, (offset + 0x04)(dst); \
@@ -142,24 +42,15 @@
142 sw val, (offset + 0x38)(dst); \ 42 sw val, (offset + 0x38)(dst); \
143 sw val, (offset + 0x3c)(dst); 43 sw val, (offset + 0x3c)(dst);
144 44
145#define FILL32(dst, offset, val) \
146 sw val, (offset + 0x00)(dst); \
147 sw val, (offset + 0x04)(dst); \
148 sw val, (offset + 0x08)(dst); \
149 sw val, (offset + 0x0c)(dst); \
150 sw val, (offset + 0x10)(dst); \
151 sw val, (offset + 0x14)(dst); \
152 sw val, (offset + 0x18)(dst); \
153 sw val, (offset + 0x1c)(dst);
154
155#define FILL 64 45#define FILL 64
156#define F_FILL FILL64 46#define F_FILL FILL64
157 47
158
159#ifdef ROCKBOX_BIG_ENDIAN 48#ifdef ROCKBOX_BIG_ENDIAN
160# define SWHI swl /* high part is left in big-endian */ 49# define SWHI swl /* high part is left in big-endian */
50# define SWLO swr
161#else 51#else
162# define SWHI swr /* high part is right in little-endian */ 52# define SWHI swr /* high part is right in little-endian */
53# define SWLO swl
163#endif 54#endif
164 55
165/* 56/*
@@ -221,7 +112,7 @@ memset_partial:
221 112
222 beqz a2, 1f 113 beqz a2, 1f
223 addu a0, a2 /* What's left */ 114 addu a0, a2 /* What's left */
224 SWHI a1, -1(a0) 115 SWLO a1, -1(a0)
2251: jr ra 1161: jr ra
226 move a2, zero 117 move a2, zero
227 118
diff --git a/utils/hwstub/stub/asm/mips/memset.S b/utils/hwstub/stub/asm/mips/memset.S
index 8db76d9123..6dfe0bf864 100644
--- a/utils/hwstub/stub/asm/mips/memset.S
+++ b/utils/hwstub/stub/asm/mips/memset.S
@@ -24,106 +24,6 @@
24#include "config.h" 24#include "config.h"
25#include "mips.h" 25#include "mips.h"
26 26
27#define FILL256(dst, offset, val) \
28 sw val, (offset + 0x00)(dst); \
29 sw val, (offset + 0x04)(dst); \
30 sw val, (offset + 0x08)(dst); \
31 sw val, (offset + 0x0c)(dst); \
32 sw val, (offset + 0x10)(dst); \
33 sw val, (offset + 0x14)(dst); \
34 sw val, (offset + 0x18)(dst); \
35 sw val, (offset + 0x1c)(dst); \
36 sw val, (offset + 0x20)(dst); \
37 sw val, (offset + 0x24)(dst); \
38 sw val, (offset + 0x28)(dst); \
39 sw val, (offset + 0x2c)(dst); \
40 sw val, (offset + 0x30)(dst); \
41 sw val, (offset + 0x34)(dst); \
42 sw val, (offset + 0x38)(dst); \
43 sw val, (offset + 0x3c)(dst); \
44 sw val, (offset + 0x40)(dst); \
45 sw val, (offset + 0x44)(dst); \
46 sw val, (offset + 0x48)(dst); \
47 sw val, (offset + 0x4c)(dst); \
48 sw val, (offset + 0x50)(dst); \
49 sw val, (offset + 0x54)(dst); \
50 sw val, (offset + 0x58)(dst); \
51 sw val, (offset + 0x5c)(dst); \
52 sw val, (offset + 0x60)(dst); \
53 sw val, (offset + 0x64)(dst); \
54 sw val, (offset + 0x68)(dst); \
55 sw val, (offset + 0x6c)(dst); \
56 sw val, (offset + 0x70)(dst); \
57 sw val, (offset + 0x74)(dst); \
58 sw val, (offset + 0x78)(dst); \
59 sw val, (offset + 0x7c)(dst); \
60 sw val, (offset + 0x80)(dst); \
61 sw val, (offset + 0x84)(dst); \
62 sw val, (offset + 0x88)(dst); \
63 sw val, (offset + 0x8c)(dst); \
64 sw val, (offset + 0x90)(dst); \
65 sw val, (offset + 0x94)(dst); \
66 sw val, (offset + 0x98)(dst); \
67 sw val, (offset + 0x9c)(dst); \
68 sw val, (offset + 0xa0)(dst); \
69 sw val, (offset + 0xa4)(dst); \
70 sw val, (offset + 0xa8)(dst); \
71 sw val, (offset + 0xac)(dst); \
72 sw val, (offset + 0xb0)(dst); \
73 sw val, (offset + 0xb4)(dst); \
74 sw val, (offset + 0xb8)(dst); \
75 sw val, (offset + 0xbc)(dst); \
76 sw val, (offset + 0xc0)(dst); \
77 sw val, (offset + 0xc4)(dst); \
78 sw val, (offset + 0xc8)(dst); \
79 sw val, (offset + 0xcc)(dst); \
80 sw val, (offset + 0xd0)(dst); \
81 sw val, (offset + 0xd4)(dst); \
82 sw val, (offset + 0xd8)(dst); \
83 sw val, (offset + 0xdc)(dst); \
84 sw val, (offset + 0xe0)(dst); \
85 sw val, (offset + 0xe4)(dst); \
86 sw val, (offset + 0xe8)(dst); \
87 sw val, (offset + 0xec)(dst); \
88 sw val, (offset + 0xf0)(dst); \
89 sw val, (offset + 0xf4)(dst); \
90 sw val, (offset + 0xf8)(dst); \
91 sw val, (offset + 0xfc)(dst);
92
93#define FILL128(dst, offset, val) \
94 sw val, (offset + 0x00)(dst); \
95 sw val, (offset + 0x04)(dst); \
96 sw val, (offset + 0x08)(dst); \
97 sw val, (offset + 0x0c)(dst); \
98 sw val, (offset + 0x10)(dst); \
99 sw val, (offset + 0x14)(dst); \
100 sw val, (offset + 0x18)(dst); \
101 sw val, (offset + 0x1c)(dst); \
102 sw val, (offset + 0x20)(dst); \
103 sw val, (offset + 0x24)(dst); \
104 sw val, (offset + 0x28)(dst); \
105 sw val, (offset + 0x2c)(dst); \
106 sw val, (offset + 0x30)(dst); \
107 sw val, (offset + 0x34)(dst); \
108 sw val, (offset + 0x38)(dst); \
109 sw val, (offset + 0x3c)(dst); \
110 sw val, (offset + 0x40)(dst); \
111 sw val, (offset + 0x44)(dst); \
112 sw val, (offset + 0x48)(dst); \
113 sw val, (offset + 0x4c)(dst); \
114 sw val, (offset + 0x50)(dst); \
115 sw val, (offset + 0x54)(dst); \
116 sw val, (offset + 0x58)(dst); \
117 sw val, (offset + 0x5c)(dst); \
118 sw val, (offset + 0x60)(dst); \
119 sw val, (offset + 0x64)(dst); \
120 sw val, (offset + 0x68)(dst); \
121 sw val, (offset + 0x6c)(dst); \
122 sw val, (offset + 0x70)(dst); \
123 sw val, (offset + 0x74)(dst); \
124 sw val, (offset + 0x78)(dst); \
125 sw val, (offset + 0x7c)(dst);
126
127#define FILL64(dst, offset, val) \ 27#define FILL64(dst, offset, val) \
128 sw val, (offset + 0x00)(dst); \ 28 sw val, (offset + 0x00)(dst); \
129 sw val, (offset + 0x04)(dst); \ 29 sw val, (offset + 0x04)(dst); \
@@ -142,24 +42,15 @@
142 sw val, (offset + 0x38)(dst); \ 42 sw val, (offset + 0x38)(dst); \
143 sw val, (offset + 0x3c)(dst); 43 sw val, (offset + 0x3c)(dst);
144 44
145#define FILL32(dst, offset, val) \
146 sw val, (offset + 0x00)(dst); \
147 sw val, (offset + 0x04)(dst); \
148 sw val, (offset + 0x08)(dst); \
149 sw val, (offset + 0x0c)(dst); \
150 sw val, (offset + 0x10)(dst); \
151 sw val, (offset + 0x14)(dst); \
152 sw val, (offset + 0x18)(dst); \
153 sw val, (offset + 0x1c)(dst);
154
155#define FILL 64 45#define FILL 64
156#define F_FILL FILL64 46#define F_FILL FILL64
157 47
158
159#ifdef ROCKBOX_BIG_ENDIAN 48#ifdef ROCKBOX_BIG_ENDIAN
160# define SWHI swl /* high part is left in big-endian */ 49# define SWHI swl /* high part is left in big-endian */
50# define SWLO swr
161#else 51#else
162# define SWHI swr /* high part is right in little-endian */ 52# define SWHI swr /* high part is right in little-endian */
53# define SWLO swl
163#endif 54#endif
164 55
165/* 56/*
@@ -221,7 +112,7 @@ memset_partial:
221 112
222 beqz a2, 1f 113 beqz a2, 1f
223 addu a0, a2 /* What's left */ 114 addu a0, a2 /* What's left */
224 SWHI a1, -1(a0) 115 SWLO a1, -1(a0)
2251: jr ra 1161: jr ra
226 move a2, zero 117 move a2, zero
227 118
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