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author | William Wilgus <me.theuser@yahoo.com> | 2018-07-29 05:08:27 +0200 |
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committer | William Wilgus <me.theuser@yahoo.com> | 2020-05-23 15:03:58 +0200 |
commit | 6ed38c89aeb1b855fda1e09e999110deeda6ecd8 (patch) | |
tree | eda852a48c3dd250a3eefea5e5f00382dfd715ad | |
parent | 084aa9c1fd670d2250123d0bae42c42ad2570309 (diff) | |
download | rockbox-6ed38c89aeb1b855fda1e09e999110deeda6ecd8.tar.gz rockbox-6ed38c89aeb1b855fda1e09e999110deeda6ecd8.zip |
Sansa Clip+ set lcd SSP properly
Change-Id: I152f038954ac1649b30dd17c3e6332e4d756502c
-rw-r--r-- | firmware/target/arm/as3525/sansa-clipplus/lcd-clip-plus.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/firmware/target/arm/as3525/sansa-clipplus/lcd-clip-plus.c b/firmware/target/arm/as3525/sansa-clipplus/lcd-clip-plus.c index a50a9e5c80..42cd43a880 100644 --- a/firmware/target/arm/as3525/sansa-clipplus/lcd-clip-plus.c +++ b/firmware/target/arm/as3525/sansa-clipplus/lcd-clip-plus.c | |||
@@ -26,11 +26,25 @@ | |||
26 | #include "system.h" | 26 | #include "system.h" |
27 | #include "cpu.h" | 27 | #include "cpu.h" |
28 | 28 | ||
29 | static void ssp_set_prescaler(unsigned int prescaler) | ||
30 | { | ||
31 | int oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS); | ||
32 | /* must be on to write regs */ | ||
33 | bool ssp_enabled = bitset32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE) & | ||
34 | CGU_SSP_CLOCK_ENABLE; | ||
35 | SSP_CPSR = prescaler; | ||
36 | |||
37 | if (!ssp_enabled) /* put it back how we found it */ | ||
38 | bitclr32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE); | ||
39 | |||
40 | restore_irq(oldlevel); | ||
41 | } | ||
42 | |||
29 | int lcd_hw_init(void) | 43 | int lcd_hw_init(void) |
30 | { | 44 | { |
31 | bitset32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE); | 45 | bitset32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE); |
32 | 46 | ||
33 | SSP_CPSR = AS3525_SSP_PRESCALER; /* OF = 0x10 */ | 47 | ssp_set_prescaler(AS3525_SSP_PRESCALER); /* OF = 0x10 */ |
34 | SSP_CR0 = (1<<7) | (1<<6) | 7; /* Motorola SPI frame format, 8 bits */ | 48 | SSP_CR0 = (1<<7) | (1<<6) | 7; /* Motorola SPI frame format, 8 bits */ |
35 | SSP_CR1 = (1<<3) | (1<<1); /* SSP Operation enabled */ | 49 | SSP_CR1 = (1<<3) | (1<<1); /* SSP Operation enabled */ |
36 | SSP_IMSC = 0; /* No interrupts */ | 50 | SSP_IMSC = 0; /* No interrupts */ |