I2S buffer level adjustment is not necessary on c200 as there is no memory mapped framebuffer that requires constant cache flushing like on e200.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14974 a1c6a512-1295-4272-9138-f99709370657

2 files changed, 3 insertions, 3 deletions

diff --git a/firmware/target/arm/i2s-pp.c b/firmware/target/arm/i2s-pp.c
index fc01e38e91..b9e32b8789 100644
--- a/firmware/target/arm/i2s-pp.c
+++ b/firmware/target/arm/i2s-pp.c
@@ -142,7 +142,7 @@ void i2s_reset(void)
     IISFIFO_CFG |= 0x1100;
 }
 
-#if defined(SANSA_E200) || defined(SANSA_C200)
+#ifdef SANSA_E200
 void i2s_scale_attn_level(long frequency)
 {
     unsigned int iisfifo_cfg = IISFIFO_CFG & ~0xff;
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c
index a817c8d411..501916ca10 100644
--- a/firmware/target/arm/system-pp502x.c
+++ b/firmware/target/arm/system-pp502x.c
@@ -142,7 +142,7 @@ static void pp_set_cpu_frequency(long frequency)
     while (test_and_set(&boostctrl_mtx.locked, 1)) ;
 #endif
 
-#if defined(SANSA_E200) || defined(SANSA_C200)
+#ifdef SANSA_E200
     i2s_scale_attn_level(CPUFREQ_DEFAULT);
 #endif
 
@@ -205,7 +205,7 @@ static void pp_set_cpu_frequency(long frequency)
     CLCD_CLOCK_SRC;             /* dummy read (to sync the write pipeline??) */
     CLCD_CLOCK_SRC = clcd_clock_src; /* restore saved value */
 
-#if defined(SANSA_E200) || defined(SANSA_C200)
+#ifdef SANSA_E200
     i2s_scale_attn_level(frequency);
 #endif