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authorMichael Sevakis <jethead71@rockbox.org>2010-05-27 23:22:55 +0000
committerMichael Sevakis <jethead71@rockbox.org>2010-05-27 23:22:55 +0000
commit6b6123444e5f1e75eb6167e8f061164f57408f66 (patch)
treec4fb240750f378c30b30d71f5280d623fe9fbd00
parent25ebd9832dcc61709571abf9705066b6a83f2038 (diff)
downloadrockbox-6b6123444e5f1e75eb6167e8f061164f57408f66.tar.gz
rockbox-6b6123444e5f1e75eb6167e8f061164f57408f66.zip
Gigabeat S PCM: Sync some comments to changes.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26341 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c
index cf68eb0fe0..f74b167400 100644
--- a/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c
+++ b/firmware/target/arm/imx31/gigabeat-s/pcm-gigabeat-s.c
@@ -241,7 +241,7 @@ static void play_start_pcm(void)
241 SSI_SCR2 |= SSI_SCR_SSIEN; /* Enable SSI */ 241 SSI_SCR2 |= SSI_SCR_SSIEN; /* Enable SSI */
242 SSI_STCR2 |= SSI_STCR_TFEN0; /* Enable TX FIFO */ 242 SSI_STCR2 |= SSI_STCR_TFEN0; /* Enable TX FIFO */
243 243
244 dma_play_data.state = 1; /* Enable DMA requests on unlock */ 244 dma_play_data.state = 1; /* Check callback on unlock */
245 245
246 /* Do prefill to prevent swapped channels (see TLSbo61214 in MCIMX31CE). 246 /* Do prefill to prevent swapped channels (see TLSbo61214 in MCIMX31CE).
247 * No actual solution was offered but this appears to work. */ 247 * No actual solution was offered but this appears to work. */
@@ -469,7 +469,7 @@ void pcm_rec_dma_start(void *addr, size_t size)
469 dma_rec_bd.mode.command = TRANSFER_16BIT; 469 dma_rec_bd.mode.command = TRANSFER_16BIT;
470 dma_rec_bd.mode.status = BD_DONE | BD_WRAP | BD_INTR; 470 dma_rec_bd.mode.status = BD_DONE | BD_WRAP | BD_INTR;
471 471
472 dma_rec_data.state = 1; 472 dma_rec_data.state = 1; /* Check callback on unlock */
473 473
474 SSI_SRCR1 |= SSI_SRCR_RFEN0; /* Enable RX FIFO */ 474 SSI_SRCR1 |= SSI_SRCR_RFEN0; /* Enable RX FIFO */
475 475