iPod Video: Fix playback after recording (FS #7402). Implement recording gain adjustment. * Enable timeout for zero-crossing detection (SLOWCLK), avoids hanging volume/ gain due to DC offsets.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18509 a1c6a512-1295-4272-9138-f99709370657

5 files changed, 367 insertions, 196 deletions

diff --git a/firmware/drivers/audio/wm8758.c b/firmware/drivers/audio/wm8758.c
index 7918d03274..d698049a8b 100644
--- a/firmware/drivers/audio/wm8758.c
+++ b/firmware/drivers/audio/wm8758.c
@@ -41,117 +41,113 @@ const struct sound_settings_info audiohw_settings[] = {
     [SOUND_CHANNELS]      = {"",   0,  1,   0,   5,   0},
     [SOUND_STEREO_WIDTH]  = {"%",  0,  5,   0, 250, 100},
 #ifdef HAVE_RECORDING
-    [SOUND_LEFT_GAIN]     = {"dB", 1,  1,-128,  96,   0},
-    [SOUND_RIGHT_GAIN]    = {"dB", 1,  1,-128,  96,   0},
-    [SOUND_MIC_GAIN]      = {"dB", 1,  1,-128, 108,  16},
+    [SOUND_LEFT_GAIN]     = {"dB", 1,  1,   0,  63,  16},
+    [SOUND_RIGHT_GAIN]    = {"dB", 1,  1,   0,  63,  16},
+    [SOUND_MIC_GAIN]      = {"dB", 1,  1,   0,  63,  16},
 #endif
     [SOUND_BASS_CUTOFF]   = {"",   0,  1,   1,   4,   1},
     [SOUND_TREBLE_CUTOFF] = {"",   0,  1,   1,   4,   1},
 };
 
 /* shadow registers */
-unsigned int eq1_reg;
-unsigned int eq5_reg;
+static unsigned short eq1_reg = EQ1_EQ3DMODE | EQ_GAIN_VALUE(0);
+static unsigned short eq5_reg = EQ_GAIN_VALUE(0);
 
 /* convert tenth of dB volume (-57..6) to master volume register value */
 int tenthdb2master(int db)
 {
-    /* +6 to -57dB in 1dB steps == 64 levels = 6 bits */
-    /* 0111111 == +6dB  (0x3f) = 63) */
-    /* 0111001 == 0dB   (0x39) = 57) */
-    /* 0000001 == -56dB (0x01) = */
-    /* 0000000 == -57dB (0x00) */
-
-    /* 1000000 == Mute (0x40) */
-
     if (db < VOLUME_MIN) {
         return 0x40;
     } else {
-        return((db/10)+57);
+        return (db/10)+57;
     }
 }
 
-/* convert tenth of dB volume (-780..0) to mixer volume register value */
-int tenthdb2mixer(int db)
+int sound_val2phys(int setting, int value)
 {
-    if (db < -660)                 /* 1.5 dB steps */
-        return (2640 - db) / 15;
-    else if (db < -600)            /* 0.75 dB steps */
-        return (990 - db) * 2 / 15;
-    else if (db < -460)            /* 0.5 dB steps */
-        return (460 - db) / 5; 
-    else                           /* 0.25 dB steps */
-        return -db * 2 / 5;
-}
+    int result;
 
-#define IPOD_PCM_LEVEL 0x65       /* -6dB */
+    switch(setting)
+    {
+#ifdef HAVE_RECORDING
+    case SOUND_LEFT_GAIN:
+    case SOUND_RIGHT_GAIN:
+    case SOUND_MIC_GAIN:
+        result = ((value - 16) * 15) / 2;
+        break;
+#endif
+    default:
+        result = value;
+        break;
+    }
 
-//#define BASSCTRL   0x
-//#define TREBCTRL   0x0b
+    return result;
+}
 
-/* Silently enable / disable audio output */
-void audiohw_enable_output(bool enable)
+void audiohw_mute(bool mute)
 {
-    if (enable) 
-    {
-        /* reset the I2S controller into known state */
-        i2s_reset();
-
-        /* TODO: Review the power-up sequence to prevent pops */
+    if (mute) {
+        wmcodec_write(DACCTRL, DACCTRL_SOFTMUTE);
+    } else {
+        wmcodec_write(DACCTRL, 0);
+    }
+}
 
-        wmcodec_write(RESET, 0x1ff);    /*Reset*/
-    
-        wmcodec_write(PWRMGMT1, 0x2b);
-        wmcodec_write(PWRMGMT2, 0x180);
-        wmcodec_write(PWRMGMT3, 0x6f);
+void audiohw_preinit(void)
+{
+    i2s_reset();
 
-        wmcodec_write(AINTFCE, 0x10);
-        wmcodec_write(CLKCTRL, 0x49);
+    wmcodec_write(RESET, RESET_RESET);
 
-        wmcodec_write(OUTCTRL, 1);
+    wmcodec_write(PWRMGMT1, PWRMGMT1_PLLEN | PWRMGMT1_BIASEN
+                          | PWRMGMT1_VMIDSEL_5K);
+    wmcodec_write(PWRMGMT2, PWRMGMT2_ROUT1EN | PWRMGMT2_LOUT1EN);
+    wmcodec_write(PWRMGMT3, PWRMGMT3_LOUT2EN | PWRMGMT3_ROUT2EN
+                          | PWRMGMT3_RMIXEN | PWRMGMT3_LMIXEN
+                          | PWRMGMT3_DACENR | PWRMGMT3_DACENL);
+                          
+    wmcodec_write(AINTFCE, AINTFCE_IWL_16BIT | AINTFCE_FORMAT_I2S);
+    wmcodec_write(OUTCTRL, OUTCTRL_VROI);
+    wmcodec_write(CLKCTRL, CLKCTRL_MS); /* WM8758 is clock master */
 
-        /* The iPod can handle multiple frequencies, but fix at 44.1KHz
-           for now */
-        audiohw_set_sample_rate(WM8758_44100HZ);
+    audiohw_set_sample_rate(WM8758_44100HZ);
     
-        wmcodec_write(LOUTMIX,0x1); /* Enable mixer */
-        wmcodec_write(ROUTMIX,0x1); /* Enable mixer */
-        audiohw_mute(0);
-    } else {
-        audiohw_mute(1);
-    }
+    wmcodec_write(LOUTMIX, LOUTMIX_DACL2LMIX);
+    wmcodec_write(ROUTMIX, ROUTMIX_DACR2RMIX);
+}
+
+void audiohw_postinit(void)
+{
+    wmcodec_write(PWRMGMT1, PWRMGMT1_PLLEN | PWRMGMT1_BIASEN
+                          | PWRMGMT1_VMIDSEL_75K); 
+                          /* lower the VMID power consumption */
+    audiohw_mute(false);
 }
 
 void audiohw_set_master_vol(int vol_l, int vol_r)
 {
     /* OUT1 */
-    wmcodec_write(LOUT1VOL, 0x080 | vol_l);
-    wmcodec_write(ROUT1VOL, 0x180 | vol_r);
+    wmcodec_write(LOUT1VOL, LOUT1VOL_LOUT1ZC | vol_l);
+    wmcodec_write(ROUT1VOL, ROUT1VOL_OUT1VU | ROUT1VOL_ROUT1ZC | vol_r);
 }
 
 void audiohw_set_lineout_vol(int vol_l, int vol_r)
 {
     /* OUT2 */
-    wmcodec_write(LOUT2VOL, vol_l);
-    wmcodec_write(ROUT2VOL, 0x100 | vol_r);
-}
-
-void audiohw_set_mixer_vol(int channel1, int channel2)
-{
-    (void)channel1;
-    (void)channel2;
+    wmcodec_write(LOUT2VOL, LOUT2VOL_LOUT2ZC | vol_l);
+    wmcodec_write(ROUT2VOL, ROUT2VOL_OUT2VU | ROUT2VOL_ROUT2ZC | vol_r);
 }
 
 void audiohw_set_bass(int value)
 {
     eq1_reg = (eq1_reg & ~EQ_GAIN_MASK) | EQ_GAIN_VALUE(value);
-    wmcodec_write(EQ1, 0x100 | eq1_reg);
+    wmcodec_write(EQ1, eq1_reg);
 }
 
 void audiohw_set_bass_cutoff(int value)
 {
     eq1_reg = (eq1_reg & ~EQ_CUTOFF_MASK) | EQ_CUTOFF_VALUE(value);
-    wmcodec_write(EQ1, 0x100 | eq1_reg);
+    wmcodec_write(EQ1, eq1_reg);
 }
 
 void audiohw_set_treble(int value)
@@ -166,31 +162,16 @@ void audiohw_set_treble_cutoff(int value)
     wmcodec_write(EQ5, eq5_reg); 
 }
 
-void audiohw_mute(bool mute)
-{
-    if (mute)
-    {
-        /* Set DACMU = 1 to soft-mute the audio DACs. */
-        wmcodec_write(DACCTRL, 0x40);
-    } else {
-        /* Set DACMU = 0 to soft-un-mute the audio DACs. */
-        wmcodec_write(DACCTRL, 0x0);
-    }
-}
-
 /* Nice shutdown of WM8758 codec */
 void audiohw_close(void)
 {
-    audiohw_mute(1);
-
-    wmcodec_write(PWRMGMT3, 0x0);
-
-    wmcodec_write(PWRMGMT1, 0x0);
+    audiohw_mute(true);
 
-    wmcodec_write(PWRMGMT2, 0x40);
+    wmcodec_write(PWRMGMT3, 0);
+    wmcodec_write(PWRMGMT1, 0);
+    wmcodec_write(PWRMGMT2, PWRMGMT2_SLEEP);
 }
 
-/* Change the order of the noise shaper, 5th order is recommended above 32kHz */
 void audiohw_set_nsorder(int order)
 {
     (void)order;
@@ -202,89 +183,68 @@ void audiohw_set_sample_rate(int sampling_control)
     /**** We force 44.1KHz for now. ****/
     (void)sampling_control;
 
-    /* set clock div */
-    wmcodec_write(CLKCTRL, 1 | (0 << 2) | (2 << 5));
-
     /* setup PLL for MHZ=11.2896 */
-    wmcodec_write(PLLN, (1 << 4) | 0x7);
+    wmcodec_write(PLLN, PLLN_PLLPRESCALE | 0x7);
     wmcodec_write(PLLK1, 0x21);
     wmcodec_write(PLLK2, 0x161);
     wmcodec_write(PLLK3, 0x26);
 
     /* set clock div */
-    wmcodec_write(CLKCTRL, 1 | (1 << 2) | (2 << 5) | (1 << 8));
+    wmcodec_write(CLKCTRL, CLKCTRL_CLKSEL | CLKCTRL_MCLKDIV_2
+                         | CLKCTRL_BCLKDIV_2 | CLKCTRL_MS);
 
-    /* set srate */
-    wmcodec_write(SRATECTRL, (0 << 1));
+    wmcodec_write(ADDCTRL, ADDCTRL_SR_48kHz | ADDCTRL_SLOWCLKEN);
+    /* SLOWCLK enabled for zero cross timeout to work */
 }
 
 void audiohw_enable_recording(bool source_mic)
 {
     (void)source_mic; /* We only have a line-in (I think) */
- 
-    /* reset the I2S controller into known state */
-    i2s_reset();
- 
-    wmcodec_write(RESET, 0x1ff);    /*Reset*/
     
-    wmcodec_write(PWRMGMT1, 0x2b);
-    wmcodec_write(PWRMGMT2, 0x18f);  /* Enable ADC - 0x0c enables left/right PGA input, and 0x03 turns on power to the ADCs */
-    wmcodec_write(PWRMGMT3, 0x6f);
+    wmcodec_write(PWRMGMT2, PWRMGMT2_ROUT1EN | PWRMGMT2_LOUT1EN
+                          | PWRMGMT2_INPGAENR | PWRMGMT2_INPGAENL
+                          | PWRMGMT2_ADCENR | PWRMGMT2_ADCENL);
 
-    wmcodec_write(AINTFCE, 0x10);
-    wmcodec_write(CLKCTRL, 0x49);
+    wmcodec_write(INCTRL, INCTRL_R2_2INPGA | INCTRL_L2_2INPGA);
 
-    wmcodec_write(OUTCTRL, 1);
-
-    /* The iPod can handle multiple frequencies, but fix at 44.1KHz
-       for now */
-    audiohw_set_sample_rate(WM8758_44100HZ);
-
-    wmcodec_write(INCTRL,0x44);  /* Connect L2 and R2 inputs */
-
-    /* Set L2/R2_2BOOSTVOL to 0db (bits 4-6) */
-    /* 000 = disabled
-       001 = -12dB
-       010 = -9dB
-       011 = -6dB
-       100 = -3dB
-       101 = 0dB
-       110 = 3dB
-       111 = 6dB
-    */
-    wmcodec_write(LADCBOOST,0x50);
-    wmcodec_write(RADCBOOST,0x50);
-
-    /* Set L/R input PGA Volume to 0db */
-    //    wm8758_write(LINPGAVOL,0x3f);
-    //    wm8758_write(RINPGAVOL,0x13f);
+    wmcodec_write(LADCBOOST, LADCBOOST_L2_2BOOST(5));
+    wmcodec_write(RADCBOOST, RADCBOOST_R2_2BOOST(5));
 
     /* Enable monitoring */
-    wmcodec_write(LOUTMIX,0x17); /* Enable output mixer - BYPL2LMIX @ 0db*/
-    wmcodec_write(ROUTMIX,0x17); /* Enable output mixer - BYPR2RMIX @ 0db*/
-
-    audiohw_mute(0);
+    wmcodec_write(LOUTMIX, LOUTMIX_BYP2LMIXVOL(5)
+                         | LOUTMIX_BYPL2LMIX | LOUTMIX_DACL2LMIX);
+    wmcodec_write(ROUTMIX, ROUTMIX_BYP2RMIXVOL(5)
+                         | ROUTMIX_BYPR2RMIX | ROUTMIX_DACR2RMIX);
 }
 
-void audiohw_disable_recording(void) {
-    audiohw_mute(1);
-
-    wmcodec_write(PWRMGMT3, 0x0);
+void audiohw_disable_recording(void) 
+{
+    wmcodec_write(LOUTMIX, LOUTMIX_DACL2LMIX);
+    wmcodec_write(ROUTMIX, ROUTMIX_DACR2RMIX);
 
-    wmcodec_write(PWRMGMT1, 0x0);
- 
-    wmcodec_write(PWRMGMT2, 0x40);
+    wmcodec_write(PWRMGMT2, PWRMGMT2_ROUT1EN | PWRMGMT2_LOUT1EN);
 }
 
-void audiohw_set_recvol(int left, int right, int type) {
-
-    (void)left;
-    (void)right;
-    (void)type;
+void audiohw_set_recvol(int left, int right, int type)
+{
+    switch (type)
+    {
+    case AUDIO_GAIN_MIC:
+        right = left;
+        /* fall through */
+    case AUDIO_GAIN_LINEIN:
+        wmcodec_write(LINPGAVOL, LINPGAVOL_INPGAZCL
+                               | (left & LINPGAVOL_INPGAVOL_MASK));
+        wmcodec_write(RINPGAVOL, RINPGAVOL_INPGAVU | RINPGAVOL_INPGAZCR
+                               | (right & RINPGAVOL_INPGAVOL_MASK));
+        break;
+    default:
+        return;
+    }
 }
 
-void audiohw_set_monitor(bool enable) {
-
+void audiohw_set_monitor(bool enable) 
+{
     (void)enable;
 }
 
diff --git a/firmware/export/wm8758.h b/firmware/export/wm8758.h
index af0e22943d..e7f7906651 100644
--- a/firmware/export/wm8758.h
+++ b/firmware/export/wm8758.h
@@ -37,53 +37,261 @@ extern void audiohw_set_mixer_vol(int channel1, int channel2);
 extern void audiohw_set_nsorder(int order);
 extern void audiohw_set_sample_rate(int sampling_control);
 
-#define RESET      0x00
-#define PWRMGMT1   0x01
-#define PWRMGMT2   0x02
-#define PWRMGMT3   0x03
-#define AINTFCE    0x04
-#define CLKCTRL    0x06
-#define SRATECTRL  0x07
-#define DACCTRL    0x0a
-#define INCTRL     0x2c
-#define LINPGAVOL  0x2d
-#define RINPGAVOL  0x2e
-#define LADCBOOST  0x2f
-#define RADCBOOST  0x30
-#define OUTCTRL    0x31
-#define LOUTMIX    0x32
-#define ROUTMIX    0x33
-
-#define LOUT1VOL   0x34
-#define ROUT1VOL   0x35
-#define LOUT2VOL   0x36
-#define ROUT2VOL   0x37
-
-#define PLLN       0x24
-#define PLLK1      0x25
-#define PLLK2      0x26
-#define PLLK3      0x27
-
-#define EQ1        0x12
-#define EQ2        0x13
-#define EQ3        0x14
-#define EQ4        0x15
-#define EQ5        0x16
-#define EQ_GAIN_MASK       0x001f
-#define EQ_CUTOFF_MASK     0x0060
-#define EQ_GAIN_VALUE(x)   (((-x) + 12) & 0x1f)
-#define EQ_CUTOFF_VALUE(x) ((((x) - 1) & 0x03) << 5)
-
-/* Register settings for the supported samplerates: */
-#define WM8758_8000HZ      0x4d
-#define WM8758_12000HZ     0x61
-#define WM8758_16000HZ     0x55
-#define WM8758_22050HZ     0x77
-#define WM8758_24000HZ     0x79
-#define WM8758_32000HZ     0x59
-#define WM8758_44100HZ     0x63
-#define WM8758_48000HZ     0x41
-#define WM8758_88200HZ     0x7f
-#define WM8758_96000HZ     0x5d
+#define RESET                   0x00
+#define RESET_RESET             0x0
+
+#define PWRMGMT1                0x01
+#define PWRMGMT1_VMIDSEL_OFF    (0 << 0)
+#define PWRMGMT1_VMIDSEL_75K    (1 << 0)
+#define PWRMGMT1_VMIDSEL_300K   (2 << 0)
+#define PWRMGMT1_VMIDSEL_5K     (3 << 0)
+#define PWRMGMT1_BUFIOEN        (1 << 2)
+#define PWRMGMT1_BIASEN         (1 << 3)
+#define PWRMGMT1_MICBEN         (1 << 4)
+#define PWRMGMT1_PLLEN          (1 << 5)
+#define PWRMGMT1_OUT3MIXEN      (1 << 6)
+#define PWRMGMT1_OUT4MIXEN      (1 << 7)
+#define PWRMGMT1_BUFDCOPEN      (1 << 8)
+
+#define PWRMGMT2                0x02
+#define PWRMGMT2_ADCENL         (1 << 0)
+#define PWRMGMT2_ADCENR         (1 << 1)
+#define PWRMGMT2_INPGAENL       (1 << 2)
+#define PWRMGMT2_INPGAENR       (1 << 3)
+#define PWRMGMT2_BOOSTENL       (1 << 4)
+#define PWRMGMT2_BOOSTENR       (1 << 5)
+#define PWRMGMT2_SLEEP          (1 << 6)
+#define PWRMGMT2_LOUT1EN        (1 << 7)
+#define PWRMGMT2_ROUT1EN        (1 << 8)
+
+#define PWRMGMT3                0x03
+#define PWRMGMT3_DACENL         (1 << 0)
+#define PWRMGMT3_DACENR         (1 << 1)
+#define PWRMGMT3_LMIXEN         (1 << 2)
+#define PWRMGMT3_RMIXEN         (1 << 3)
+#define PWRMGMT3_ROUT2EN        (1 << 5)
+#define PWRMGMT3_LOUT2EN        (1 << 6)
+#define PWRMGMT3_OUT3EN         (1 << 7)
+#define PWRMGMT3_OUT4EN         (1 << 8)
+
+#define AINTFCE                 0x04
+#define AINTFCE_MONO            (1 << 0)
+#define AINTFCE_ALRSWAP         (1 << 1)
+#define AINTFCE_DLRSWAP         (1 << 2)
+#define AINTFCE_FORMAT_MSB_RJUST (0 << 3)
+#define AINTFCE_FORMAT_MSB_LJUST (1 << 3)
+#define AINTFCE_FORMAT_I2S      (2 << 3)
+#define AINTFCE_FORMAT_DSP      (3 << 3)
+#define AINTFCE_FORMAT_MASK     (3 << 3)
+#define AINTFCE_IWL_16BIT       (0 << 5)
+#define AINTFCE_IWL_20BIT       (1 << 5)
+#define AINTFCE_IWL_24BIT       (2 << 5)
+#define AINTFCE_IWL_32BIT       (3 << 5)
+#define AINTFCE_IWL_MASK        (3 << 5)
+#define AINTFCE_LRP             (1 << 7)
+#define AINTFCE_BCP             (1 << 8)
+
+#define COMPCTRL                0x05 /* unused */
+
+#define CLKCTRL                 0x06
+#define CLKCTRL_MS              (1 << 0)
+#define CLKCTRL_BCLKDIV_1       (0 << 2)
+#define CLKCTRL_BCLKDIV_2       (1 << 2)
+#define CLKCTRL_BCLKDIV_4       (2 << 2)
+#define CLKCTRL_BCLKDIV_8       (3 << 2)
+#define CLKCTRL_BCLKDIV_16      (4 << 2)
+#define CLKCTRL_BCLKDIV_32      (5 << 2)
+#define CLKCTRL_MCLKDIV_1       (0 << 5)
+#define CLKCTRL_MCLKDIV_1_5     (1 << 5)
+#define CLKCTRL_MCLKDIV_2       (2 << 5)
+#define CLKCTRL_MCLKDIV_3       (3 << 5)
+#define CLKCTRL_MCLKDIV_4       (4 << 5)
+#define CLKCTRL_MCLKDIV_6       (5 << 5)
+#define CLKCTRL_MCLKDIV_8       (6 << 5)
+#define CLKCTRL_MCLKDIV_12      (7 << 5)
+#define CLKCTRL_CLKSEL          (1 << 8)
+
+#define ADDCTRL                 0x07
+#define ADDCTRL_SLOWCLKEN       (1 << 0)
+#define ADDCTRL_SR_48kHz        (0 << 1)
+#define ADDCTRL_SR_32kHz        (1 << 1)
+#define ADDCTRL_SR_24kHz        (2 << 1)
+#define ADDCTRL_SR_16kHz        (3 << 1)
+#define ADDCTRL_SR_12kHz        (4 << 1)
+#define ADDCTRL_SR_8kHz         (5 << 1)
+#define ADDCTRL_SR_MASK         (7 << 1)
+
+/* unused */
+#define GPIOCTRL                0x08
+#define JACKDETECTCTRL1         0x09
+
+#define DACCTRL                 0x0a
+#define DACCTRL_DACLPOL         (1 << 0)
+#define DACCTRL_DACRPOL         (1 << 1)
+#define DACCTRL_AMUTE           (1 << 2)
+#define DACCTRL_DACOSR128       (1 << 3)
+#define DACCTRL_SOFTMUTE        (1 << 6)
+
+#define LDACVOL                 0x0b
+#define LDACVOL_MASK            0xff
+#define LDACVOL_DACVU           (1 << 8)
+
+#define RDACVOL                 0x0c
+#define RDACVOL_MASK            0xff
+#define RDACVOL_DACVU           (1 << 8)
+
+#define JACKDETECTCTRL2         0x0d /* unused */
+
+#define ADCCTRL                 0x0e
+#define ADCCTRL_ADCLPOL         (1 << 0)
+#define ADCCTRL_ADCRPOL         (1 << 1)
+#define ADCCTRL_ADCOSR128       (1 << 3)
+#define ADCCTRL_HPFCUT_MASK     (7 << 4)
+#define ADCCTRL_HPFAPP          (1 << 7)
+#define ADCCTRL_HPFEN           (1 << 8)
+
+#define LADCVOL                 0x0f
+#define LADCVOL_MASK            0xff
+#define LADCVOL_ADCVU           (1 << 8)
+
+#define RADCVOL                 0x10
+#define RADCVOL_MASK            0xff
+#define RADCVOL_ADCVU           (1 << 8)
+
+#define EQ1                     0x12
+#define EQ5                     0x16
+/* note: the WM8983 used for reference has a true 5 band EQ, but the WM8758
+ * does only have low shelf & high shelf (tested). Not sure about 3D mode. */
+#define EQ1_EQ3DMODE            (1 << 8)
+#define EQ_GAIN_MASK            0x1f
+#define EQ_CUTOFF_MASK          (3 << 5)
+#define EQ_GAIN_VALUE(x)        (((-x) + 12) & 0x1f)
+#define EQ_CUTOFF_VALUE(x)      ((((x) - 1) & 0x03) << 5)
+
+/* unused */
+#define DACLIMITER1             0x18
+#define DACLIMITER2             0x19
+#define NOTCHFILTER1            0x1b
+#define NOTCHFILTER2            0x1c
+#define NOTCHFILTER3            0x1d
+#define NOTCHFILTER4            0x1e
+#define ALCCONTROL1             0x20
+#define ALCCONTROL2             0x21
+#define ALCCONTROL3             0x22
+#define NOISEGATE               0x23
+
+#define PLLN                    0x24
+#define PLLN_PLLN_MASK          0x0f
+#define PLLN_PLLPRESCALE        (1 << 4)
+
+#define PLLK1                   0x25
+#define PLLK1_MASK              0x3f
+
+#define PLLK2                   0x26
+#define PLLK3                   0x27
+
+#define THREEDCTRL              0x29
+#define THREEDCTRL_DEPTH3D_MASK 0x0f
+
+#define OUT4TOADC               0x2a
+#define OUT4TOADC_OUT1DEL       (1 << 0)
+#define OUT4TOADC_DELEN         (1 << 1)
+#define OUT4TOADC_POBCTRL       (1 << 2)
+#define OUT4TOADC_OUT4_2LNR     (1 << 5)
+#define OUT4TOADC_OUT4_ADCVOL_MASK (7 << 6)
+
+#define BEEPCTRL                0x2b
+#define BEEPCTRL_BEEPEN         (1 << 0)
+#define BEEPCTRL_BEEPVOL_MASK   (7 << 1)
+#define BEEPCTRL_INVROUT2       (1 << 4)
+#define BEEPCTRL_MUTERPGA2INV   (1 << 5)
+#define BEEPCTRL_BYPR2LMIX      (1 << 7)
+#define BEEPCTRL_BYPL2RMIX      (1 << 8)
+
+#define INCTRL                  0x2c
+#define INCTRL_LIP2INPGA        (1 << 0)
+#define INCTRL_LIN2INPGA        (1 << 1)
+#define INCTRL_L2_2INPGA        (1 << 2)
+#define INCTRL_RIP2INPGA        (1 << 4)
+#define INCTRL_RIN2INPGA        (1 << 5)
+#define INCTRL_R2_2INPGA        (1 << 6)
+#define INCTRL_MBVSEL           (1 << 8)
+
+#define LINPGAVOL               0x2d
+#define LINPGAVOL_INPGAVOL_MASK 0x3f
+#define LINPGAVOL_INPGAMUTEL    (1 << 6)
+#define LINPGAVOL_INPGAZCL      (1 << 7)
+#define LINPGAVOL_INPGAVU       (1 << 8)
+
+#define RINPGAVOL               0x2e
+#define RINPGAVOL_INPGAVOL_MASK 0x3f
+#define RINPGAVOL_INPGAMUTER    (1 << 6)
+#define RINPGAVOL_INPGAZCR      (1 << 7)
+#define RINPGAVOL_INPGAVU       (1 << 8)
+
+#define LADCBOOST               0x2f
+#define LADCBOOST_AUXL2BOOST_MASK (7 << 0)
+#define LADCBOOST_L2_2BOOST_MASK  (7 << 4)
+#define LADCBOOST_L2_2BOOST(x)  ((x) << 4)
+#define LADCBOOST_PGABOOSTL     (1 << 8)
+
+#define RADCBOOST               0x30
+#define RADCBOOST_AUXR2BOOST_MASK (7 << 0)
+#define RADCBOOST_R2_2BOOST_MASK  (7 << 4)
+#define RADCBOOST_R2_2BOOST(x)  ((x) << 4)
+#define RADCBOOST_PGABOOSTR     (1 << 8)
+
+#define OUTCTRL                 0x31
+#define OUTCTRL_VROI            (1 << 0)
+#define OUTCTRL_TSDEN           (1 << 1)
+#define OUTCTRL_SPKBOOST        (1 << 2)
+#define OUTCTRL_OUT3BOOST       (1 << 3)
+#define OUTCTRL_OUT4BOOST       (1 << 4)
+#define OUTCTRL_DACR2LMIX       (1 << 5)
+#define OUTCTRL_DACL2RMIX       (1 << 6)
+
+#define LOUTMIX                 0x32
+#define LOUTMIX_DACL2LMIX       (1 << 0)
+#define LOUTMIX_BYPL2LMIX       (1 << 1)
+#define LOUTMIX_BYP2LMIXVOL_MASK (7 << 2)
+#define LOUTMIX_BYP2LMIXVOL(x)  ((x) << 2)
+#define LOUTMIX_AUXL2LMIX       (1 << 5)
+#define LOUTMIX_AUXLMIXVOL_MASK (7 << 6)
+
+#define ROUTMIX                 0x33
+#define ROUTMIX_DACR2RMIX       (1 << 0)
+#define ROUTMIX_BYPR2RMIX       (1 << 1)
+#define ROUTMIX_BYP2RMIXVOL_MASK (7 << 2)
+#define ROUTMIX_BYP2RMIXVOL(x)  ((x) << 2)
+#define ROUTMIX_AUXR2RMIX       (1 << 5)
+#define ROUTMIX_AUXRMIXVOL_MASK (7 << 6)
+
+#define LOUT1VOL                0x34
+#define LOUT1VOL_MASK           0x3f
+#define LOUT1VOL_LOUT1MUTE      (1 << 6)
+#define LOUT1VOL_LOUT1ZC        (1 << 7)
+#define LOUT1VOL_OUT1VU         (1 << 8)
+
+#define ROUT1VOL                0x35
+#define ROUT1VOL_MASK           0x3f
+#define ROUT1VOL_ROUT1MUTE      (1 << 6)
+#define ROUT1VOL_ROUT1ZC        (1 << 7)
+#define ROUT1VOL_OUT1VU         (1 << 8)
+
+#define LOUT2VOL                0x36
+#define LOUT2VOL_MASK           0x3f
+#define LOUT2VOL_LOUT2MUTE      (1 << 6)
+#define LOUT2VOL_LOUT2ZC        (1 << 7)
+#define LOUT2VOL_OUT2VU         (1 << 8)
+
+#define ROUT2VOL                0x37
+#define ROUT2VOL_MASK           0x3f
+#define ROUT2VOL_ROUT2MUTE      (1 << 6)
+#define ROUT2VOL_ROUT2ZC        (1 << 7)
+#define ROUT2VOL_OUT2VU         (1 << 8)
+
+
+/* Dummy definition, to be removed when the audio driver API gets reworked. */
+#define WM8758_44100HZ     0
 
 #endif /* _WM8758_H */
diff --git a/firmware/sound.c b/firmware/sound.c
index ab09c7e7bc..0a95562b22 100644
--- a/firmware/sound.c
+++ b/firmware/sound.c
@@ -625,8 +625,8 @@ void sound_set(int setting, int value)
         sound_set_val(value);
 }
 
-#if (!defined(HAVE_AS3514) && !defined (HAVE_WM8731)  && !defined (HAVE_WM8975) \
-  && !defined(HAVE_TSC2100)) || defined(SIMULATOR)
+#if (!defined(HAVE_AS3514) && !defined (HAVE_WM8731) && !defined(HAVE_WM8975) \
+  && !defined(HAVE_WM8758) && !defined(HAVE_TSC2100)) || defined(SIMULATOR)
 int sound_val2phys(int setting, int value)
 {
 #if CONFIG_CODEC == MAS3587F
diff --git a/firmware/target/arm/pcm-pp.c b/firmware/target/arm/pcm-pp.c
index e98054ab9e..38fd49165e 100644
--- a/firmware/target/arm/pcm-pp.c
+++ b/firmware/target/arm/pcm-pp.c
@@ -365,7 +365,8 @@ void pcm_play_dma_init(void)
     /* Initialize default register values. */
     audiohw_init();
 
-#if !defined(HAVE_WM8731) && !defined(HAVE_WM8751) && !defined(HAVE_WM8975)
+#if !defined(HAVE_WM8731) && !defined(HAVE_WM8751) && !defined(HAVE_WM8975) \
+ && !defined(HAVE_WM8758)
     /* Power on */
     audiohw_enable_output(true);
     /* Unmute the master channel (DAC should be at zero point now). */
diff --git a/firmware/target/arm/wmcodec-pp.c b/firmware/target/arm/wmcodec-pp.c
index 04cf238ac3..0d751f6b3f 100644
--- a/firmware/target/arm/wmcodec-pp.c
+++ b/firmware/target/arm/wmcodec-pp.c
@@ -96,13 +96,15 @@ void audiohw_init(void) {
 #endif /* IPOD_1G2G/3G */
 #endif
     
-#if defined(HAVE_WM8731) || defined(HAVE_WM8751) || defined(HAVE_WM8975)
+#if defined(HAVE_WM8731) || defined(HAVE_WM8751) || defined(HAVE_WM8975) \
+ || defined(HAVE_WM8758)
     audiohw_preinit();
 #endif
    
 }
 
-#if !defined(HAVE_WM8731) && !defined(HAVE_WM8751) && !defined(HAVE_WM8975)
+#if !defined(HAVE_WM8731) && !defined(HAVE_WM8751) && !defined(HAVE_WM8975) \
+ && !defined(HAVE_WM8758)
 void audiohw_postinit(void)
 {
 }