Move CACHEALIGN_BITS to cpu headers

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25633 a1c6a512-1295-4272-9138-f99709370657

5 files changed, 7 insertions, 2 deletions

diff --git a/firmware/export/pp5002.h b/firmware/export/pp5002.h
index b0c31d9474..95cc8d5058 100644
--- a/firmware/export/pp5002.h
+++ b/firmware/export/pp5002.h
@@ -22,6 +22,9 @@
 #define __PP5002_H__
 
 /* Much info gleaned and/or copied from the iPodLinux project. */
+
+#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
+
 #define DRAM_START       0x28000000
 
 /* LCD bridge */
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h
index 2d8d0e1802..5b5864f4e1 100644
--- a/firmware/export/pp5020.h
+++ b/firmware/export/pp5020.h
@@ -23,6 +23,8 @@
 
 /* All info gleaned and/or copied from the iPodLinux project. */
 
+#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
+
 /* PCM addresses for obtaining buffers will be what DMA is using (physical) */
 #define HAVE_PCM_DMA_ADDRESS
 
diff --git a/firmware/export/s5l8700.h b/firmware/export/s5l8700.h
index ff8daf044a..71ba071365 100644
--- a/firmware/export/s5l8700.h
+++ b/firmware/export/s5l8700.h
@@ -27,6 +27,8 @@
 
 #define TIMER_FREQ  47923200L
 
+#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
+
 /* 04. CALMADM2E */
 
 /* Following registers are mapped on IO Area in data memory area of Calm. */
diff --git a/firmware/target/arm/s5l8700/system-target.h b/firmware/target/arm/s5l8700/system-target.h
index 5f91032d9e..fd45ee1a13 100644
--- a/firmware/target/arm/s5l8700/system-target.h
+++ b/firmware/target/arm/s5l8700/system-target.h
@@ -29,7 +29,6 @@
 #define CPUFREQ_NORMAL  47923200
 #define CPUFREQ_MAX    191692800
 
-#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
 #define WANTS_STORAGE_ALIGN
 
 #define inl(a) (*(volatile unsigned long *) (a))
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h
index 157a450743..5d20c397f8 100644
--- a/firmware/target/arm/system-target.h
+++ b/firmware/target/arm/system-target.h
@@ -161,7 +161,6 @@ static inline void wake_core(int core)
 /* Certain data needs to be out of the way of cache line interference
  * such as data for COP use or for use with UNCACHED_ADDR */
 #define PROC_NEEDS_CACHEALIGN
-#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
 
 #if defined(CPU_PP502x) && defined(HAVE_ATA_DMA)
 #define STORAGE_WANTS_ALIGN