iPod Classic: use new PL080 DMA driver

This patch uses the new pl080 DMA driver for I2S playback and LCD
update. I have tried to be as fiel as possible to the current
behaviour, algorithms and configurations are the same, but using
the new driver. Other modifications:

Playback:

 - CHUNK_SIZE is decreased from 42988 to 8188 bytes, it does not
   affect normal playback (block size 1024), was tested using
   metronome (block size 46080). This change is needed because the
   new code commits d-cache range instead of commiting the whole
   d-cache, maximum time spent commiting the range should be
   limited, CHUNK_SIZE can be decreased even more if necessary.

 - pcm_play_dma_start() calls pcm_play_dma_stop() to stop the
   channel when it is running (metronome replays the tick sound
   without stopping the channel).

 - pcm_play_dma_get_peak_buffer(): same as actual SVN function but
   returns samples count instead of bytes count.
   TODO: AFAIK, actually this function is not used in RB. Not tested,
   but probably this function will fail because it returns pointers
   to the internal double buffer.

LCD update:

 - suppresses lcd_wakeup semaphore and uses yield()

Change-Id: I79b8aa47a941e0dd91847150618f3f7f676c26ef

9 files changed, 336 insertions, 343 deletions

diff --git a/firmware/SOURCES b/firmware/SOURCES
index 17f6ad7e0a..adfedcb212 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -1599,6 +1599,7 @@ target/arm/s5l8702/kernel-s5l8702.c
 target/arm/s5l8702/system-s5l8702.c
 target/arm/s5l8702/gpio-s5l8702.c
 target/arm/s5l8702/pl080.c
+target/arm/s5l8702/dma-s5l8702.c
 target/arm/s5l8702/ipod6g/lcd-ipod6g.c
 target/arm/s5l8702/ipod6g/lcd-asm-ipod6g.S
 #if 0 //TODO
diff --git a/firmware/export/s5l8702.h b/firmware/export/s5l8702.h
index 701dcabeb4..34b6da874b 100644
--- a/firmware/export/s5l8702.h
+++ b/firmware/export/s5l8702.h
@@ -419,178 +419,6 @@
 #define SHA1DATAIN      ((uint32_t volatile*)(0x38000040))
 
 
-/////DMA/////
-#ifndef ASM
-struct dma_lli
-{
-    const void* srcaddr;
-    void* dstaddr;
-    const struct dma_lli* nextlli;
-    uint32_t control;
-};
-#endif
-/* currently these definitions are not used, temporarily
-   removed to avoid conflicts with pl080.h */
-#if 0
-#define DMACINTSTS(d)       (*((uint32_t volatile*)(0x38200000 + 0x1700000 * (d))))
-#define DMACINTTCSTS(d)     (*((uint32_t volatile*)(0x38200004 + 0x1700000 * (d))))
-#define DMACINTTCCLR(d)     (*((uint32_t volatile*)(0x38200008 + 0x1700000 * (d))))
-#define DMACINTERRSTS(d)    (*((uint32_t volatile*)(0x3820000c + 0x1700000 * (d))))
-#define DMACINTERRCLR(d)    (*((uint32_t volatile*)(0x38200010 + 0x1700000 * (d))))
-#define DMACRAWINTTCSTS(d)  (*((uint32_t volatile*)(0x38200014 + 0x1700000 * (d))))
-#define DMACRAWINTERRSTS(d) (*((uint32_t volatile*)(0x38200018 + 0x1700000 * (d))))
-#define DMACENABLEDCHANS(d) (*((uint32_t volatile*)(0x3820001c + 0x1700000 * (d))))
-#define DMACSOFTBREQ(d)     (*((uint32_t volatile*)(0x38200020 + 0x1700000 * (d))))
-#define DMACSOFTSREQ(d)     (*((uint32_t volatile*)(0x38200024 + 0x1700000 * (d))))
-#define DMACSOFTLBREQ(d)    (*((uint32_t volatile*)(0x38200028 + 0x1700000 * (d))))
-#define DMACSOFTLSREQ(d)    (*((uint32_t volatile*)(0x3820002c + 0x1700000 * (d))))
-#define DMACCONFIG(d)       (*((uint32_t volatile*)(0x38200030 + 0x1700000 * (d))))
-#define DMACSYNC(d)         (*((uint32_t volatile*)(0x38200034 + 0x1700000 * (d))))
-#endif
-#define DMACCLLI(d, c)      (*((struct dma_lli volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
-#define DMACCSRCADDR(d, c)  (*((const void* volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
-#define DMACCDESTADDR(d, c) (*((void* volatile*)(0x38200104 + 0x1700000 * (d) + 0x20 * (c))))
-#define DMACCNEXTLLI(d, c)  (*((const void* volatile*)(0x38200108 + 0x1700000 * (d) + 0x20 * (c))))
-#define DMACCCONTROL(d, c)  (*((uint32_t volatile*)(0x3820010c + 0x1700000 * (d) + 0x20 * (c))))
-#define DMACCCONFIG(d, c)   (*((uint32_t volatile*)(0x38200110 + 0x1700000 * (d) + 0x20 * (c))))
-#define DMAC0INTSTS         (*((uint32_t volatile*)(0x38200000)))
-#define DMAC0INTTCSTS       (*((uint32_t volatile*)(0x38200004)))
-#define DMAC0INTTCCLR       (*((uint32_t volatile*)(0x38200008)))
-#define DMAC0INTERRSTS      (*((uint32_t volatile*)(0x3820000c)))
-#define DMAC0INTERRCLR      (*((uint32_t volatile*)(0x38200010)))
-#define DMAC0RAWINTTCSTS    (*((uint32_t volatile*)(0x38200014)))
-#define DMAC0RAWINTERRSTS   (*((uint32_t volatile*)(0x38200018)))
-#define DMAC0ENABLEDCHANS   (*((uint32_t volatile*)(0x3820001c)))
-#define DMAC0SOFTBREQ       (*((uint32_t volatile*)(0x38200020)))
-#define DMAC0SOFTSREQ       (*((uint32_t volatile*)(0x38200024)))
-#define DMAC0SOFTLBREQ      (*((uint32_t volatile*)(0x38200028)))
-#define DMAC0SOFTLSREQ      (*((uint32_t volatile*)(0x3820002c)))
-#define DMAC0CONFIG         (*((uint32_t volatile*)(0x38200030)))
-#define DMAC0SYNC           (*((uint32_t volatile*)(0x38200034)))
-#define DMAC0CLLI(c)        (*((struct dma_lli volatile*)(0x38200100 + 0x20 * (c))))
-#define DMAC0CSRCADDR(c)    (*((const void* volatile*)(0x38200100 + 0x20 * (c))))
-#define DMAC0CDESTADDR(c)   (*((void* volatile*)(0x38200104 + 0x20 * (c))))
-#define DMAC0CNEXTLLI(c)    (*((const void* volatile*)(0x38200108 + 0x20 * (c))))
-#define DMAC0CCONTROL(c)    (*((uint32_t volatile*)(0x3820010c + 0x20 * (c))))
-#define DMAC0CCONFIG(c)     (*((uint32_t volatile*)(0x38200110 + 0x20 * (c))))
-#define DMAC0C0LLI          (*((struct dma_lli volatile*)(0x38200100)))
-#define DMAC0C0SRCADDR      (*((const void* volatile*)(0x38200100)))
-#define DMAC0C0DESTADDR     (*((void* volatile*)(0x38200104)))
-#define DMAC0C0NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200108)))
-#define DMAC0C0CONTROL      (*((uint32_t volatile*)(0x3820010c)))
-#define DMAC0C0CONFIG       (*((uint32_t volatile*)(0x38200110)))
-#define DMAC0C1LLI          (*((struct dma_lli volatile*)(0x38200120)))
-#define DMAC0C1SRCADDR      (*((const void* volatile*)(0x38200120)))
-#define DMAC0C1DESTADDR     (*((void* volatile*)(0x38200124)))
-#define DMAC0C1NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200128)))
-#define DMAC0C1CONTROL      (*((uint32_t volatile*)(0x3820012c)))
-#define DMAC0C1CONFIG       (*((uint32_t volatile*)(0x38200130)))
-#define DMAC0C2LLI          (*((struct dma_lli volatile*)(0x38200140)))
-#define DMAC0C2SRCADDR      (*((const void* volatile*)(0x38200140)))
-#define DMAC0C2DESTADDR     (*((void* volatile*)(0x38200144)))
-#define DMAC0C2NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200148)))
-#define DMAC0C2CONTROL      (*((uint32_t volatile*)(0x3820014c)))
-#define DMAC0C2CONFIG       (*((uint32_t volatile*)(0x38200150)))
-#define DMAC0C3LLI          (*((struct dma_lli volatile*)(0x38200160)))
-#define DMAC0C3SRCADDR      (*((const void* volatile*)(0x38200160)))
-#define DMAC0C3DESTADDR     (*((void* volatile*)(0x38200164)))
-#define DMAC0C3NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200168)))
-#define DMAC0C3CONTROL      (*((uint32_t volatile*)(0x3820016c)))
-#define DMAC0C3CONFIG       (*((uint32_t volatile*)(0x38200170)))
-#define DMAC0C4LLI          (*((struct dma_lli volatile*)(0x38200180)))
-#define DMAC0C4SRCADDR      (*((const void* volatile*)(0x38200180)))
-#define DMAC0C4DESTADDR     (*((void* volatile*)(0x38200184)))
-#define DMAC0C4NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200188)))
-#define DMAC0C4CONTROL      (*((uint32_t volatile*)(0x3820018c)))
-#define DMAC0C4CONFIG       (*((uint32_t volatile*)(0x38200190)))
-#define DMAC0C5LLI          (*((struct dma_lli volatile*)(0x382001a0)))
-#define DMAC0C5SRCADDR      (*((const void* volatile*)(0x382001a0)))
-#define DMAC0C5DESTADDR     (*((void* volatile*)(0x382001a4)))
-#define DMAC0C5NEXTLLI      (*((const struct dma_lli* volatile*)(0x382001a8)))
-#define DMAC0C5CONTROL      (*((uint32_t volatile*)(0x382001ac)))
-#define DMAC0C5CONFIG       (*((uint32_t volatile*)(0x382001b0)))
-#define DMAC0C6LLI          (*((struct dma_lli volatile*)(0x382001c0)))
-#define DMAC0C6SRCADDR      (*((const void* volatile*)(0x382001c0)))
-#define DMAC0C6DESTADDR     (*((void* volatile*)(0x382001c4)))
-#define DMAC0C6NEXTLLI      (*((const struct dma_lli* volatile*)(0x382001c8)))
-#define DMAC0C6CONTROL      (*((uint32_t volatile*)(0x382001cc)))
-#define DMAC0C6CONFIG       (*((uint32_t volatile*)(0x382001d0)))
-#define DMAC0C7LLI          (*((struct dma_lli volatile*)(0x382001e0)))
-#define DMAC0C7SRCADDR      (*((const void* volatile*)(0x382001e0)))
-#define DMAC0C7DESTADDR     (*((void* volatile*)(0x382001e4)))
-#define DMAC0C7NEXTLLI      (*((const struct dma_lli* volatile*)(0x382001e8)))
-#define DMAC0C7CONTROL      (*((uint32_t volatile*)(0x382001ec)))
-#define DMAC0C7CONFIG       (*((uint32_t volatile*)(0x382001f0)))
-#define DMAC1INTSTS         (*((uint32_t volatile*)(0x39900000)))
-#define DMAC1INTTCSTS       (*((uint32_t volatile*)(0x39900004)))
-#define DMAC1INTTCCLR       (*((uint32_t volatile*)(0x39900008)))
-#define DMAC1INTERRSTS      (*((uint32_t volatile*)(0x3990000c)))
-#define DMAC1INTERRCLR      (*((uint32_t volatile*)(0x39900010)))
-#define DMAC1RAWINTTCSTS    (*((uint32_t volatile*)(0x39900014)))
-#define DMAC1RAWINTERRSTS   (*((uint32_t volatile*)(0x39900018)))
-#define DMAC1ENABLEDCHANS   (*((uint32_t volatile*)(0x3990001c)))
-#define DMAC1SOFTBREQ       (*((uint32_t volatile*)(0x39900020)))
-#define DMAC1SOFTSREQ       (*((uint32_t volatile*)(0x39900024)))
-#define DMAC1SOFTLBREQ      (*((uint32_t volatile*)(0x39900028)))
-#define DMAC1SOFTLSREQ      (*((uint32_t volatile*)(0x3990002c)))
-#define DMAC1CONFIG         (*((uint32_t volatile*)(0x39900030)))
-#define DMAC1SYNC           (*((uint32_t volatile*)(0x39900034)))
-#define DMAC1CLLI(c)        (*((struct dma_lli volatile*)(0x39900100 + 0x20 * (c))))
-#define DMAC1CSRCADDR(c)    (*((const void* volatile*)(0x39900100 + 0x20 * (c))))
-#define DMAC1CDESTADDR(c)   (*((void* volatile*)(0x39900104 + 0x20 * (c))))
-#define DMAC1CNEXTLLI(c)    (*((const void* volatile*)(0x39900108 + 0x20 * (c))))
-#define DMAC1CCONTROL(c)    (*((uint32_t volatile*)(0x3990010c + 0x20 * (c))))
-#define DMAC1CCONFIG(c)     (*((uint32_t volatile*)(0x39900110 + 0x20 * (c))))
-#define DMAC1C0LLI          (*((struct dma_lli volatile*)(0x39900100)))
-#define DMAC1C0SRCADDR      (*((const void* volatile*)(0x39900100)))
-#define DMAC1C0DESTADDR     (*((void* volatile*)(0x39900104)))
-#define DMAC1C0NEXTLLI      (*((const struct dma_lli* volatile*)(0x39900108)))
-#define DMAC1C0CONTROL      (*((uint32_t volatile*)(0x3990010c)))
-#define DMAC1C0CONFIG       (*((uint32_t volatile*)(0x39900110)))
-#define DMAC1C1LLI          (*((struct dma_lli volatile*)(0x39900120)))
-#define DMAC1C1SRCADDR      (*((const void* volatile*)(0x39900120)))
-#define DMAC1C1DESTADDR     (*((void* volatile*)(0x39900124)))
-#define DMAC1C1NEXTLLI      (*((const struct dma_lli* volatile*)(0x39900128)))
-#define DMAC1C1CONTROL      (*((uint32_t volatile*)(0x3990012c)))
-#define DMAC1C1CONFIG       (*((uint32_t volatile*)(0x39900130)))
-#define DMAC1C2LLI          (*((struct dma_lli volatile*)(0x39900140)))
-#define DMAC1C2SRCADDR      (*((const void* volatile*)(0x39900140)))
-#define DMAC1C2DESTADDR     (*((void* volatile*)(0x39900144)))
-#define DMAC1C2NEXTLLI      (*((const struct dma_lli* volatile*)(0x39900148)))
-#define DMAC1C2CONTROL      (*((uint32_t volatile*)(0x3990014c)))
-#define DMAC1C2CONFIG       (*((uint32_t volatile*)(0x39900150)))
-#define DMAC1C3LLI          (*((struct dma_lli volatile*)(0x39900160)))
-#define DMAC1C3SRCADDR      (*((const void* volatile*)(0x39900160)))
-#define DMAC1C3DESTADDR     (*((void* volatile*)(0x39900164)))
-#define DMAC1C3NEXTLLI      (*((volatile void**)(0x39900168)))
-#define DMAC1C3CONTROL      (*((uint32_t volatile*)(0x3990016c)))
-#define DMAC1C3CONFIG       (*((uint32_t volatile*)(0x39900170)))
-#define DMAC1C4LLI          (*((struct dma_lli volatile*)(0x39900180)))
-#define DMAC1C4SRCADDR      (*((const void* volatile*)(0x39900180)))
-#define DMAC1C4DESTADDR     (*((void* volatile*)(0x39900184)))
-#define DMAC1C4NEXTLLI      (*((const struct dma_lli* volatile*)(0x39900188)))
-#define DMAC1C4CONTROL      (*((uint32_t volatile*)(0x3990018c)))
-#define DMAC1C4CONFIG       (*((uint32_t volatile*)(0x39900190)))
-#define DMAC1C5LLI          (*((struct dma_lli volatile*)(0x399001a0)))
-#define DMAC1C5SRCADDR      (*((const void* volatile*)(0x399001a0)))
-#define DMAC1C5DESTADDR     (*((void* volatile*)(0x399001a4)))
-#define DMAC1C5NEXTLLI      (*((const struct dma_lli* volatile*)(0x399001a8)))
-#define DMAC1C5CONTROL      (*((uint32_t volatile*)(0x399001ac)))
-#define DMAC1C5CONFIG       (*((uint32_t volatile*)(0x399001b0)))
-#define DMAC1C6LLI          (*((struct dma_lli volatile*)(0x399001c0)))
-#define DMAC1C6SRCADDR      (*((const void* volatile*)(0x399001c0)))
-#define DMAC1C6DESTADDR     (*((void* volatile*)(0x399001c4)))
-#define DMAC1C6NEXTLLI      (*((const struct dma_lli* volatile*)(0x399001c8)))
-#define DMAC1C6CONTROL      (*((uint32_t volatile*)(0x399001cc)))
-#define DMAC1C6CONFIG       (*((uint32_t volatile*)(0x399001d0)))
-#define DMAC1C7LLI          (*((struct dma_lli volatile*)(0x399001e0)))
-#define DMAC1C7SRCADDR      (*((const void* volatile*)(0x399001e0)))
-#define DMAC1C7DESTADDR     (*((void* volatile*)(0x399001e4)))
-#define DMAC1C7NEXTLLI      (*((const struct dma_lli* volatile*)(0x399001e8)))
-#define DMAC1C7CONTROL      (*((uint32_t volatile*)(0x399001ec)))
-#define DMAC1C7CONFIG       (*((uint32_t volatile*)(0x399001f0)))
-
-
 /////LCD/////
 #define LCD_BASE   (0x38300000)
 #define LCD_CONFIG (*((uint32_t volatile*)(0x38300000)))
@@ -844,6 +672,8 @@ struct dma_lli
 /////CLOCK GATES/////
 #define CLOCKGATE_USB_1 2
 #define CLOCKGATE_USB_2 35
+#define CLOCKGATE_DMAC0 25
+#define CLOCKGATE_DMAC1 26
 
 
 /////INTERRUPTS/////
diff --git a/firmware/target/arm/s5l8702/debug-s5l8702.c b/firmware/target/arm/s5l8702/debug-s5l8702.c
index 66bfa36a93..74f765e447 100644
--- a/firmware/target/arm/s5l8702/debug-s5l8702.c
+++ b/firmware/target/arm/s5l8702/debug-s5l8702.c
@@ -44,7 +44,7 @@ bool dbg_hw_info(void)
     int line;
     int i;
     unsigned int state = 0;
-    const unsigned int max_states=3;
+    const unsigned int max_states=2;
 
     lcd_clear_display();
     lcd_setfont(FONT_SYSFIXED);
@@ -95,16 +95,6 @@ bool dbg_hw_info(void)
             _DEBUG_PRINTF("backlight: %s", pmu_read(0x29) ? "on" : "off");
             _DEBUG_PRINTF("brightness value: %d", pmu_read(0x28));
         }
-        else if(state==2)
-        {
-            _DEBUG_PRINTF("Audio DMA:");
-            _DEBUG_PRINTF(">%08X %08X %08X %08X %08X", DMAC0C0CONFIG, DMAC0C0SRCADDR,
-                          DMAC0C0DESTADDR, DMAC0C0NEXTLLI, DMAC0C0CONTROL);
-            for(i = 0; i < PCM_LLICOUNT; i++)
-                _DEBUG_PRINTF("%08X: %08X %08X %08X %08X", &pcm_lli[i], pcm_lli[i].srcaddr,
-                              pcm_lli[i].dstaddr, pcm_lli[i].nextlli, pcm_lli[i].control);
-            _DEBUG_PRINTF("chunk: %08X %08X", pcm_chunksize, pcm_remaining);
-        }
         else
         {
             state=0;
diff --git a/firmware/target/arm/s5l8702/dma-s5l8702.c b/firmware/target/arm/s5l8702/dma-s5l8702.c
new file mode 100644
index 0000000000..6fe25f712a
--- /dev/null
+++ b/firmware/target/arm/s5l8702/dma-s5l8702.c
@@ -0,0 +1,68 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2014 by Cástor Muñoz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include <config.h>
+
+#include "s5l8702.h"
+#include "pl080.h"
+#include "dma-s5l8702.h"
+
+/* s5l8702 PL080 controllers configuration */
+struct dmac s5l8702_dmac0 = {
+    .baddr = S5L8702_DMAC0_BASE,
+    .m1 = DMACCONFIG_M_LITTLE_ENDIAN,
+    .m2 = DMACCONFIG_M_LITTLE_ENDIAN,
+};
+
+struct dmac s5l8702_dmac1 = {
+    .baddr = S5L8702_DMAC1_BASE,
+    .m1 = DMACCONFIG_M_LITTLE_ENDIAN,
+    .m2 = DMACCONFIG_M_LITTLE_ENDIAN,
+};
+
+void ICODE_ATTR INT_DMAC0(void)
+{
+    dmac_callback(&s5l8702_dmac0);
+}
+
+void ICODE_ATTR INT_DMAC1(void)
+{
+    dmac_callback(&s5l8702_dmac1);
+}
+
+void dma_init_ctrl(struct dmac* dmac, int irq, int clockgate, int onoff)
+{
+    /* init DMAC */
+    VIC0INTENCLEAR = (1 << irq);        /* disable interrupts */
+    PWRCON(0) &= ~(1 << clockgate);     /* unmask clock gate */
+    dmac_open(dmac);                    /* init/reset controller */
+
+    if (onoff)
+        VIC0INTENABLE = (1 << irq);     /* enable interrupts */
+    else
+        PWRCON(0) |= (1 << clockgate);  /* mask clockgate */
+}
+
+void dma_init(void)
+{
+    dma_init_ctrl(&s5l8702_dmac0, IRQ_DMAC0, CLOCKGATE_DMAC0, 1);
+    dma_init_ctrl(&s5l8702_dmac1, IRQ_DMAC1, CLOCKGATE_DMAC1, 0);
+}
diff --git a/firmware/target/arm/s5l8702/dma-s5l8702.h b/firmware/target/arm/s5l8702/dma-s5l8702.h
new file mode 100644
index 0000000000..5f338578f7
--- /dev/null
+++ b/firmware/target/arm/s5l8702/dma-s5l8702.h
@@ -0,0 +1,107 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2014 by Cástor Muñoz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef _DMA_S5l8702_H
+#define _DMA_S5l8702_H
+
+#include "pl080.h"
+
+/*
+ * s5l8702 PL080 controllers configuration
+ */
+
+extern struct dmac s5l8702_dmac0;
+extern struct dmac s5l8702_dmac1;
+
+#define S5L8702_DMAC_COUNT          2   /* N PL080 controllers */
+#define S5L8702_DMAC0_BASE          0x38200000
+#define S5L8702_DMAC1_BASE          0x39900000
+
+/* S5L7802 DMAC0 peripherals */
+#define S5L8702_DMAC0_PERI_IIS2_TX          0x0
+#define S5L8702_DMAC0_PERI_IIS2_RX          0x1
+#define S5L8702_DMAC0_PERI_UNKNOWN          0x2
+#define S5L8702_DMAC0_PERI_LCD_WR           0x3
+#define S5L8702_DMAC0_PERI_SPI0_TX          0x4
+#define S5L8702_DMAC0_PERI_SPI0_RX          0x5
+#define S5L8702_DMAC0_PERI_UART0_TX         0x6
+#define S5L8702_DMAC0_PERI_UART0_RX         0x7
+#define S5L8702_DMAC0_PERI_UART1_TX         0x8
+#define S5L8702_DMAC0_PERI_UART1_RX         0x9
+#define S5L8702_DMAC0_PERI_IIS0_TX          0xA
+#define S5L8702_DMAC0_PERI_IIS0_RX          0xB
+#define S5L8702_DMAC0_PERI_SPI2_TX          0xC
+#define S5L8702_DMAC0_PERI_SPI2_RX          0xD
+#define S5L8702_DMAC0_PERI_SPI1_TX          0xE
+#define S5L8702_DMAC0_PERI_SPI1_RX          0xF
+
+/* S5L7802 DMAC1 peripherals */
+#define S5L8702_DMAC1_PERI_CEATA_WR         0x0
+#define S5L8702_DMAC1_PERI_CEATA_RD         0x1
+#define S5L8702_DMAC1_PERI_IIS1_TX          0x2
+#define S5L8702_DMAC1_PERI_IIS1_RX          0x3
+#define S5L8702_DMAC1_PERI_IIS2_TX          0x4
+#define S5L8702_DMAC1_PERI_IIS2_RX          0x5
+#define S5L8702_DMAC1_PERI_SPI1_TX          0x6
+#define S5L8702_DMAC1_PERI_SPI1_RX          0x7
+#define S5L8702_DMAC1_PERI_UART2_TX         0x8
+#define S5L8702_DMAC1_PERI_UART2_RX         0x9
+#define S5L8702_DMAC1_PERI_SPI0_TX          0xA
+#define S5L8702_DMAC1_PERI_SPI0_RX          0xB
+#define S5L8702_DMAC1_PERI_UART3_TX         0xC
+#define S5L8702_DMAC1_PERI_UART3_RX         0xD
+#define S5L8702_DMAC1_PERI_SPI2_TX          0xE
+#define S5L8702_DMAC1_PERI_SPI2_RX          0xF
+
+/* used when src and/or dst peripheral is memory */
+#define S5L8702_DMAC0_PERI_MEM              DMAC_PERI_NONE
+#define S5L8702_DMAC1_PERI_MEM              DMAC_PERI_NONE
+
+/* s5l8702 peripheral DMA R/W addesses */
+#define S5L8702_DADDR_PERI_LCD_WR           0x38300040
+#define S5L8702_DADDR_PERI_UNKNOWN          0x3CB00010  /* SPDIF ??? */
+#define S5L8702_DADDR_PERI_UART0_TX         0x3CC00020
+#define S5L8702_DADDR_PERI_UART0_RX         0x3CC00024
+#define S5L8702_DADDR_PERI_UART1_TX         0x3CC04020
+#define S5L8702_DADDR_PERI_UART1_RX         0x3CC04024
+#define S5L8702_DADDR_PERI_UART2_TX         0x3CC08020
+#define S5L8702_DADDR_PERI_UART2_RX         0x3CC08024
+#define S5L8702_DADDR_PERI_UART3_TX         0x3CC0C020
+#define S5L8702_DADDR_PERI_UART3_RX         0x3CC0C024
+#define S5L8702_DADDR_PERI_IIS0_TX          0x3CA00010
+#define S5L8702_DADDR_PERI_IIS0_RX          0x3CA00038
+#define S5L8702_DADDR_PERI_IIS1_TX          0x3CD00010
+#define S5L8702_DADDR_PERI_IIS1_RX          0x3CD00038
+#define S5L8702_DADDR_PERI_IIS2_TX          0x3D400010
+#define S5L8702_DADDR_PERI_IIS2_RX          0x3D400038
+#define S5L8702_DADDR_PERI_CEATA_WR         0x38A00080
+#define S5L8702_DADDR_PERI_CEATA_RD         0x38A04080
+#define S5L8702_DADDR_PERI_SPI0_TX          0x3C300010
+#define S5L8702_DADDR_PERI_SPI0_RX          0x3C300020
+#define S5L8702_DADDR_PERI_SPI1_TX          0x3CE00010
+#define S5L8702_DADDR_PERI_SPI1_RX          0x3CE00020
+#define S5L8702_DADDR_PERI_SPI2_TX          0x3D200010
+#define S5L8702_DADDR_PERI_SPI2_RX          0x3D200020
+
+/* proto */
+void dma_init(void);
+
+#endif /* _DMA_S5l8702_H */
diff --git a/firmware/target/arm/s5l8702/ipod6g/lcd-ipod6g.c b/firmware/target/arm/s5l8702/ipod6g/lcd-ipod6g.c
index f9dbab6180..bf6c1a1402 100644
--- a/firmware/target/arm/s5l8702/ipod6g/lcd-ipod6g.c
+++ b/firmware/target/arm/s5l8702/ipod6g/lcd-ipod6g.c
@@ -28,6 +28,7 @@
 #include "pmu-target.h"
 #include "power.h"
 #include "string.h"
+#include "dma-s5l8702.h"
 
 
 #define R_HORIZ_GRAM_ADDR_SET     0x200
@@ -49,10 +50,8 @@
 /** globals **/
 
 int lcd_type; /* also needed in debug-s5l8702.c */
-static struct dma_lli lcd_lli[(LCD_WIDTH * LCD_HEIGHT - 1) / 0xfff] CACHEALIGN_ATTR;
-static struct semaphore lcd_wakeup;
 static struct mutex lcd_mutex;
-static uint16_t lcd_dblbuf[LCD_HEIGHT][LCD_WIDTH];
+static uint16_t lcd_dblbuf[LCD_HEIGHT][LCD_WIDTH] CACHEALIGN_ATTR;
 static bool lcd_ispowered;
 
 #define SLEEP       0
@@ -197,6 +196,48 @@ static const unsigned short lcd_init_sequence_23[] =
 };
 #endif
 
+/* DMA configuration */
+
+/* one single transfer at once, needed LLIs:
+ *   screen_size / (DMAC_LLI_MAX_COUNT << swidth) =
+ *   (320*240*2) / (4095*2) = 19
+ */
+#define LCD_DMA_TSKBUF_SZ   1   /* N tasks, MUST be pow2 */
+#define LCD_DMA_LLIBUF_SZ   32  /* N LLIs, MUST be pow2 */
+
+static struct dmac_tsk lcd_dma_tskbuf[LCD_DMA_TSKBUF_SZ];
+static struct dmac_lli volatile \
+            lcd_dma_llibuf[LCD_DMA_LLIBUF_SZ] CACHEALIGN_ATTR;
+
+static struct dmac_ch lcd_dma_ch = {
+    .dmac = &s5l8702_dmac0,
+    .prio = DMAC_CH_PRIO(4),
+    .cb_fn = NULL,
+
+    .tskbuf = lcd_dma_tskbuf,
+    .tskbuf_mask = LCD_DMA_TSKBUF_SZ - 1,
+    .queue_mode = QUEUE_NORMAL,
+
+    .llibuf = lcd_dma_llibuf,
+    .llibuf_mask = LCD_DMA_LLIBUF_SZ - 1,
+    .llibuf_bus = DMAC_MASTER_AHB1,
+};
+
+static struct dmac_ch_cfg lcd_dma_ch_cfg = {
+    .srcperi = S5L8702_DMAC0_PERI_MEM,
+    .dstperi = S5L8702_DMAC0_PERI_LCD_WR,
+    .sbsize  = DMACCxCONTROL_BSIZE_1,
+    .dbsize  = DMACCxCONTROL_BSIZE_1,
+    .swidth  = DMACCxCONTROL_WIDTH_16,
+    .dwidth  = DMACCxCONTROL_WIDTH_16,
+    .sbus    = DMAC_MASTER_AHB1,
+    .dbus    = DMAC_MASTER_AHB1,
+    .sinc    = DMACCxCONTROL_INC_ENABLE,
+    .dinc    = DMACCxCONTROL_INC_DISABLE,
+    .prot    = DMAC_PROT_CACH | DMAC_PROT_BUFF | DMAC_PROT_PRIV,
+    .lli_xfer_max_count = DMAC_LLI_MAX_COUNT,
+};
+
 static inline void s5l_lcd_write_reg(int cmd, unsigned int data)
 {
     while (LCD_STATUS & 0x10);
@@ -328,12 +369,14 @@ void lcd_awake(void)
 void lcd_init_device(void)
 {
     /* Detect lcd type */
-    semaphore_init(&lcd_wakeup, 1, 0);
     mutex_init(&lcd_mutex);
     lcd_type = (PDAT6 & 0x30) >> 4;
     while (!(LCD_STATUS & 0x2));
     LCD_CONFIG = 0x80100db0;
 
+    /* Configure DMA channel */
+    dmac_ch_init(&lcd_dma_ch, &lcd_dma_ch_cfg);
+
     lcd_ispowered = true;
 }
 
@@ -362,8 +405,10 @@ extern void lcd_write_line(const fb_data *addr,
 static void displaylcd_setup(int x, int y, int width, int height) ICODE_ATTR;
 static void displaylcd_setup(int x, int y, int width, int height)
 {
+    /* TODO: ISR()->panicf()->lcd_update() blocks forever */
     mutex_lock(&lcd_mutex);
-    while (DMAC0C4CONFIG & 1) semaphore_wait(&lcd_wakeup, HZ / 10);
+    while (dmac_ch_running(&lcd_dma_ch))
+        yield();
 
     int xe = (x + width) - 1;           /* max horiz */
     int ye = (y + height) - 1;          /* max vert */
@@ -398,31 +443,12 @@ static void displaylcd_setup(int x, int y, int width, int height)
 static void displaylcd_dma(int pixels) ICODE_ATTR;
 static void displaylcd_dma(int pixels)
 {
-    int i;
-    void* data = lcd_dblbuf;
-    for (i = -1; i < (int)ARRAYLEN(lcd_lli) && pixels > 0; i++, pixels -= 0xfff)
-    {
-        bool last = i + 1 >= (int)ARRAYLEN(lcd_lli) || pixels <= 0xfff;
-        struct dma_lli* lli = i < 0 ? (struct dma_lli*)((int)&DMAC0C4LLI) : &lcd_lli[i];
-        lli->srcaddr = data;
-        lli->dstaddr = (void*)((int)&LCD_WDATA);
-        lli->nextlli = last ? NULL : &lcd_lli[i + 1];
-        lli->control = 0x70240000 | (last ? pixels : 0xfff)
-                     | (last ? 0x80000000 : 0) | 0x4000000;
-        data += 0x1ffe;
-    }
     commit_dcache();
-    DMAC0C4CONFIG = 0x88c1;
+    dmac_ch_queue(&lcd_dma_ch, lcd_dblbuf,
+            (void*)S5L8702_DADDR_PERI_LCD_WR, pixels*2, NULL);
     mutex_unlock(&lcd_mutex);
 }
 
-void INT_DMAC0C4(void) ICODE_ATTR;
-void INT_DMAC0C4(void)
-{
-    DMAC0INTTCCLR = 0x10;
-    semaphore_release(&lcd_wakeup);
-}
-
 /* Update a fraction of the display. */
 void lcd_update_rect(int, int, int, int) ICODE_ATTR;
 void lcd_update_rect(int x, int y, int width, int height)
diff --git a/firmware/target/arm/s5l8702/pcm-s5l8702.c b/firmware/target/arm/s5l8702/pcm-s5l8702.c
index 1048354ec5..a4ea56edce 100644
--- a/firmware/target/arm/s5l8702/pcm-s5l8702.c
+++ b/firmware/target/arm/s5l8702/pcm-s5l8702.c
@@ -31,104 +31,129 @@
 #include "pcm_sampr.h"
 #include "mmu-arm.h"
 #include "pcm-target.h"
+#include "dma-s5l8702.h"
+
+/* DMA configuration */
+
+/* 3 DMA tasks needed, one chunk task and two dblbuf tasks */
+#define DMA_PLAY_TSKBUF_SZ  4   /* N tasks, MUST be pow2 */
+#define DMA_PLAY_LLIBUF_SZ  4   /* N LLIs, MUST be pow2 */
+
+static struct dmac_tsk dma_play_tskbuf[DMA_PLAY_TSKBUF_SZ];
+static struct dmac_lli volatile \
+            dma_play_llibuf[DMA_PLAY_LLIBUF_SZ] CACHEALIGN_ATTR;
+
+static void dma_play_callback(void *data) ICODE_ATTR;
+
+static struct dmac_ch dma_play_ch = {
+    .dmac = &s5l8702_dmac0,
+    .prio = DMAC_CH_PRIO(2),
+    .cb_fn = dma_play_callback,
+
+    .tskbuf = dma_play_tskbuf,
+    .tskbuf_mask = DMA_PLAY_TSKBUF_SZ - 1,
+    .queue_mode = QUEUE_LINK,
+
+    .llibuf = dma_play_llibuf,
+    .llibuf_mask = DMA_PLAY_LLIBUF_SZ - 1,
+    .llibuf_bus = DMAC_MASTER_AHB1,
+};
+
+static struct dmac_ch_cfg dma_play_ch_cfg = {
+    .srcperi = S5L8702_DMAC0_PERI_MEM,
+    .dstperi = S5L8702_DMAC0_PERI_IIS0_TX,
+    .sbsize  = DMACCxCONTROL_BSIZE_8,
+    .dbsize  = DMACCxCONTROL_BSIZE_4,
+    .swidth  = DMACCxCONTROL_WIDTH_16,
+    .dwidth  = DMACCxCONTROL_WIDTH_16,
+    .sbus    = DMAC_MASTER_AHB1,
+    .dbus    = DMAC_MASTER_AHB1,
+    .sinc    = DMACCxCONTROL_INC_ENABLE,
+    .dinc    = DMACCxCONTROL_INC_DISABLE,
+    .prot    = DMAC_PROT_CACH | DMAC_PROT_BUFF | DMAC_PROT_PRIV,
+    /* align LLI transfers to L-R pairs (samples) */
+    .lli_xfer_max_count = DMAC_LLI_MAX_COUNT & ~1,
+};
+#define LLI_MAX_BYTES       8188  /* lli_xfer_max_count << swidth */
+
+/* Use all available LLIs for chunk */
+/*#define CHUNK_MAX_BYTES     (LLI_MAX_BYTES * (DMA_PLAY_LLIBUF_SZ - 2))*/
+#define CHUNK_MAX_BYTES     (LLI_MAX_BYTES * 1)
+#define WATERMARK_BYTES     (PCM_WATERMARK * 4)
 
 static volatile int locked = 0;
-static const int zerosample = 0;
-static unsigned char dblbuf[2][PCM_WATERMARK * 4];
+static unsigned char dblbuf[2][WATERMARK_BYTES] CACHEALIGN_ATTR;
 static int active_dblbuf;
-struct dma_lli pcm_lli[PCM_LLICOUNT] __attribute__((aligned(16)));
-static struct dma_lli* lastlli;
-static const void* dataptr;
 size_t pcm_remaining;
-size_t pcm_chunksize;
 
 /* Mask the DMA interrupt */
 void pcm_play_lock(void)
 {
-    if (locked++ == 0) {
-        //TODO: Urgh, I don't like that at all...
-        VIC0INTENCLEAR = 1 << IRQ_DMAC0;
-    }
+    if (locked++ == 0)
+        dmac_ch_lock_int(&dma_play_ch);
 }
 
 /* Unmask the DMA interrupt if enabled */
 void pcm_play_unlock(void)
 {
-    if (--locked == 0) {
-        VIC0INTENABLE = 1 << IRQ_DMAC0;
-    }
+    if (--locked == 0)
+        dmac_ch_unlock_int(&dma_play_ch);
 }
 
-void INT_DMAC0C0(void) ICODE_ATTR;
-void INT_DMAC0C0(void)
+static inline void play_queue_dma(void *addr, size_t size, void *cb_data)
 {
-    DMAC0INTTCCLR = 1;
-    if (!pcm_remaining)
-    {
-        pcm_play_dma_complete_callback(PCM_DMAST_OK, &dataptr, &pcm_remaining);
-        pcm_chunksize = pcm_remaining;
-    }
+    commit_dcache_range(addr, size);
+    dmac_ch_queue(&dma_play_ch, addr,
+                (void*)S5L8702_DADDR_PERI_IIS0_TX, size, cb_data);
+}
+
+static void dma_play_callback(void *cb_data)
+{
+    if (!cb_data)
+        return; /* dblbuf callback entered, nothing to do */
+
+    const void *dataptr = cb_data;
+
     if (!pcm_remaining)
-    {
-        pcm_lli->nextlli = NULL;
-        pcm_lli->control = 0x7524a000;
-        commit_dcache();
-        return;
-    }
-    uint32_t lastsize = MIN(PCM_WATERMARK * 4, pcm_remaining / 2 + 1) & ~1;
+        if (!pcm_play_dma_complete_callback(
+                     PCM_DMAST_OK, &dataptr, &pcm_remaining))
+            return;
+
+    uint32_t lastsize = MIN(WATERMARK_BYTES, pcm_remaining >> 1);
     pcm_remaining -= lastsize;
-    if (pcm_remaining) lastlli = &pcm_lli[ARRAYLEN(pcm_lli) - 1];
-    else lastlli = pcm_lli;
-    uint32_t chunksize = MIN(PCM_CHUNKSIZE * 4 - lastsize, pcm_remaining);
-    if (pcm_remaining > chunksize && chunksize > pcm_remaining - PCM_WATERMARK * 8)
-        chunksize = pcm_remaining - PCM_WATERMARK * 8;
+    uint32_t chunksize = MIN(CHUNK_MAX_BYTES, pcm_remaining);
+
+    /* last chunk should be at least 2*WATERMARK_BYTES in size */
+    if ((pcm_remaining > chunksize) &&
+                (pcm_remaining < chunksize + WATERMARK_BYTES * 2))
+        chunksize = pcm_remaining - WATERMARK_BYTES * 2;
+
     pcm_remaining -= chunksize;
-    bool last = !chunksize;
-    int i = 0;
-    while (chunksize)
-    {
-        uint32_t thislli = MIN(PCM_LLIMAX * 4, chunksize);
-        chunksize -= thislli;
-        pcm_lli[i].srcaddr = (void*)dataptr;
-        pcm_lli[i].dstaddr = (void*)((int)&I2STXDB0);
-        pcm_lli[i].nextlli = chunksize ? &pcm_lli[i + 1] : lastlli;
-        pcm_lli[i].control = (chunksize ? 0x7524a000 : 0xf524a000) | (thislli / 2);
-        dataptr += thislli;
-        i++;
-    }
-    if (!pcm_remaining)
-    {
-        memcpy(dblbuf[active_dblbuf], dataptr, lastsize);
-        lastlli->srcaddr = dblbuf[active_dblbuf];
-        active_dblbuf ^= 1;
-    }
-    else lastlli->srcaddr = dataptr;
-    lastlli->dstaddr = (void*)((int)&I2STXDB0);
-    lastlli->nextlli = last ? NULL : pcm_lli;
-    lastlli->control = (last ? 0xf524a000 : 0x7524a000) | (lastsize / 2);
-    dataptr += lastsize;
-    commit_dcache();
-    if (!(DMAC0C0CONFIG & 1) && (pcm_lli[0].control & 0xfff))
-    {
-        DMAC0C0LLI = pcm_lli[0];
-        DMAC0C0CONFIG = 0x8a81;
-    }
-    else DMAC0C0NEXTLLI = pcm_lli;
+
+    /* first part */
+    play_queue_dma((void*)dataptr, chunksize,
+                (void*)dataptr + chunksize + lastsize); /* cb_data */
+
+    /* second part */
+    memcpy(dblbuf[active_dblbuf], dataptr + chunksize, lastsize);
+    play_queue_dma(dblbuf[active_dblbuf], lastsize, NULL);
+    active_dblbuf ^= 1;
 
     pcm_play_dma_status_callback(PCM_DMAST_STARTED);
 }
 
 void pcm_play_dma_start(const void* addr, size_t size)
 {
-    dataptr = addr;
+    pcm_play_dma_stop();
+
     pcm_remaining = size;
     I2STXCOM = 0xe;
-    INT_DMAC0C0();
+    dma_play_callback((void*)addr);
 }
 
 void pcm_play_dma_stop(void)
 {
-    DMAC0C0CONFIG = 0x8a80;
+    dmac_ch_stop(&dma_play_ch);
     I2STXCOM = 0xa;
 }
 
@@ -184,9 +209,11 @@ void pcm_play_dma_init(void)
 {
     PWRCON(0) &= ~(1 << 4);
     PWRCON(1) &= ~(1 << 7);
+
+    dmac_ch_init(&dma_play_ch, &dma_play_ch_cfg);
+
     I2STXCON = 0xb100019;
     I2SCLKCON = 1;
-    VIC0INTENABLE = 1 << IRQ_DMAC0;
 
     audiohw_preinit();
     pcm_dma_apply_settings();
@@ -199,21 +226,16 @@ void pcm_play_dma_postinit(void)
 
 size_t pcm_get_bytes_waiting(void)
 {
-    int bytes = pcm_remaining;
-    const struct dma_lli* lli = (const struct dma_lli*)((int)&DMAC0C0LLI);
-    while (lli)
-    {
-        bytes += (lli->control & 0xfff) * 2;
-        if (lli == lastlli) break;
-        lli = lli->nextlli;
-    }
-    return bytes;
+    size_t total_bytes;
+    dmac_ch_get_info(&dma_play_ch, NULL, &total_bytes);
+    return total_bytes;
 }
 
 const void* pcm_play_dma_get_peak_buffer(int *count)
 {
-    *count = (DMAC0C0LLI.control & 0xfff) * 2;
-    return (void*)(((uint32_t)DMAC0C0LLI.srcaddr) & ~3);
+    void *addr = dmac_ch_get_info(&dma_play_ch, count, NULL);
+    *count >>= 2; /* bytes to samples */
+    return addr; /* aligned to dest burst */
 }
 
 #ifdef HAVE_PCM_DMA_ADDRESS
diff --git a/firmware/target/arm/s5l8702/pcm-target.h b/firmware/target/arm/s5l8702/pcm-target.h
index aefb64e328..b858581c4e 100644
--- a/firmware/target/arm/s5l8702/pcm-target.h
+++ b/firmware/target/arm/s5l8702/pcm-target.h
@@ -23,18 +23,7 @@
 
 
 /* S5L8702 PCM driver tunables: */
-#define PCM_LLIMAX (2047)     /* Maximum number of samples per LLI */
-#define PCM_CHUNKSIZE (10747) /* Maximum number of samples to handle with one IRQ */
-                              /* (bigger chunks will be segmented internally)     */
 #define PCM_WATERMARK (512)   /* Number of remaining samples to schedule IRQ at */
 
 
-#define PCM_LLICOUNT ((PCM_CHUNKSIZE - PCM_WATERMARK + PCM_LLIMAX - 1) / PCM_LLIMAX + 1)
-
-
-extern struct dma_lli pcm_lli[PCM_LLICOUNT];
-extern size_t pcm_remaining;
-extern size_t pcm_chunksize;
-
-
 #endif /* __PCM_TARGET_H__ */
diff --git a/firmware/target/arm/s5l8702/system-s5l8702.c b/firmware/target/arm/s5l8702/system-s5l8702.c
index f93a6a70ec..6a06c29694 100644
--- a/firmware/target/arm/s5l8702/system-s5l8702.c
+++ b/firmware/target/arm/s5l8702/system-s5l8702.c
@@ -25,6 +25,7 @@
 #include "system-target.h"
 #include "pmu-target.h"
 #include "gpio-s5l8702.h"
+#include "dma-s5l8702.h"
 
 #define default_interrupt(name) \
   extern __attribute__((weak,alias("UIRQ"))) void name (void)
@@ -55,22 +56,8 @@ default_interrupt(INT_IRQ12);
 default_interrupt(INT_IRQ13);
 default_interrupt(INT_IRQ14);
 default_interrupt(INT_IRQ15);
-default_interrupt(INT_DMAC0C0);
-default_interrupt(INT_DMAC0C1);
-default_interrupt(INT_DMAC0C2);
-default_interrupt(INT_DMAC0C3);
-default_interrupt(INT_DMAC0C4);
-default_interrupt(INT_DMAC0C5);
-default_interrupt(INT_DMAC0C6);
-default_interrupt(INT_DMAC0C7);
-default_interrupt(INT_DMAC1C0);
-default_interrupt(INT_DMAC1C1);
-default_interrupt(INT_DMAC1C2);
-default_interrupt(INT_DMAC1C3);
-default_interrupt(INT_DMAC1C4);
-default_interrupt(INT_DMAC1C5);
-default_interrupt(INT_DMAC1C6);
-default_interrupt(INT_DMAC1C7);
+default_interrupt(INT_DMAC0);
+default_interrupt(INT_DMAC1);
 default_interrupt(INT_IRQ18);
 default_interrupt(INT_USB_FUNC);
 default_interrupt(INT_IRQ20);
@@ -141,34 +128,6 @@ void INT_TIMER32()
     if ((THCON >> 12) & 0x7 & tstat) INT_TIMERH();
 }
 
-void INT_DMAC0(void) ICODE_ATTR;
-void INT_DMAC0()
-{
-    uint32_t intsts = DMAC0INTSTS;
-    if (intsts & 1) INT_DMAC0C0();
-    if (intsts & 2) INT_DMAC0C1();
-    if (intsts & 4) INT_DMAC0C2();
-    if (intsts & 8) INT_DMAC0C3();
-    if (intsts & 0x10) INT_DMAC0C4();
-    if (intsts & 0x20) INT_DMAC0C5();
-    if (intsts & 0x40) INT_DMAC0C6();
-    if (intsts & 0x80) INT_DMAC0C7();
-}
-
-void INT_DMAC1(void) ICODE_ATTR;
-void INT_DMAC1()
-{
-    uint32_t intsts = DMAC1INTSTS;
-    if (intsts & 1) INT_DMAC1C0();
-    if (intsts & 2) INT_DMAC1C1();
-    if (intsts & 4) INT_DMAC1C2();
-    if (intsts & 8) INT_DMAC1C3();
-    if (intsts & 0x10) INT_DMAC1C4();
-    if (intsts & 0x20) INT_DMAC1C5();
-    if (intsts & 0x40) INT_DMAC1C6();
-    if (intsts & 0x80) INT_DMAC1C7();
-}
-
 static void (* const irqvector[])(void) =
 {
     INT_EXT0,INT_EXT1,INT_EXT2,INT_EXT3,INT_IRQ4,INT_IRQ5,INT_IRQ6,INT_TIMER32,
@@ -225,6 +184,7 @@ void system_init(void)
 {
     /*gpio_init();*/
     pmu_init();
+    dma_init();
     VIC0INTENABLE = 1 << IRQ_WHEEL;
     VIC0INTENABLE = 1 << IRQ_ATA;
     VIC1INTENABLE = 1 << (IRQ_MMC - 32);