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author | Linus Nielsen Feltzing <linus@haxx.se> | 2005-07-09 07:46:42 +0000 |
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committer | Linus Nielsen Feltzing <linus@haxx.se> | 2005-07-09 07:46:42 +0000 |
commit | 62c768c0db601fa1cc8532bb583060f2a8080453 (patch) | |
tree | 96c83ffdb5f8b0edc3dc1e0f6fc417a60d607bc9 | |
parent | f69c77933c7fca7b72dfc6aa94cbe03651a149f8 (diff) | |
download | rockbox-62c768c0db601fa1cc8532bb583060f2a8080453.tar.gz rockbox-62c768c0db601fa1cc8532bb583060f2a8080453.zip |
Recovered from my major brain failure and reverted to using the same load address for both H110 and H120/140
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7082 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r-- | apps/plugins/plugin.lds | 6 | ||||
-rw-r--r-- | bootloader/main.c | 4 | ||||
-rw-r--r-- | firmware/app.lds | 10 | ||||
-rw-r--r-- | firmware/boot.lds | 2 | ||||
-rw-r--r-- | firmware/crt0.S | 17 |
5 files changed, 12 insertions, 27 deletions
diff --git a/apps/plugins/plugin.lds b/apps/plugins/plugin.lds index c0150055eb..41193d950c 100644 --- a/apps/plugins/plugin.lds +++ b/apps/plugins/plugin.lds | |||
@@ -18,14 +18,10 @@ OUTPUT_FORMAT(elf32-sh) | |||
18 | #define ARCH_IRIVER | 18 | #define ARCH_IRIVER |
19 | #endif | 19 | #endif |
20 | 20 | ||
21 | #if defined(IRIVER_H120) || defined(IRIVER_H300) | 21 | #ifdef ARCH_IRIVER |
22 | #define DRAMORIG 0x31000000 | 22 | #define DRAMORIG 0x31000000 |
23 | #define IRAMORIG 0x10010000 | 23 | #define IRAMORIG 0x10010000 |
24 | #define IRAMSIZE 0x8000 | 24 | #define IRAMSIZE 0x8000 |
25 | #elif defined(IRIVER_H100) | ||
26 | #define DRAMORIG 0x30000000 | ||
27 | #define IRAMORIG 0x10010000 | ||
28 | #define IRAMSIZE 0x8000 | ||
29 | #else | 25 | #else |
30 | #define DRAMORIG 0x09000000 + STUBOFFSET | 26 | #define DRAMORIG 0x09000000 + STUBOFFSET |
31 | #endif | 27 | #endif |
diff --git a/bootloader/main.c b/bootloader/main.c index e7e61665fd..5cc995c855 100644 --- a/bootloader/main.c +++ b/bootloader/main.c | |||
@@ -35,12 +35,12 @@ | |||
35 | #include "power.h" | 35 | #include "power.h" |
36 | #include "file.h" | 36 | #include "file.h" |
37 | 37 | ||
38 | #define DRAM_START 0x31000000 | ||
39 | |||
38 | #ifdef IRIVER_H100 | 40 | #ifdef IRIVER_H100 |
39 | #define MODEL_NUMBER 1 | 41 | #define MODEL_NUMBER 1 |
40 | #define DRAM_START 0x30000000 | ||
41 | #else | 42 | #else |
42 | #define MODEL_NUMBER 0 | 43 | #define MODEL_NUMBER 0 |
43 | #define DRAM_START 0x31000000 | ||
44 | #endif | 44 | #endif |
45 | 45 | ||
46 | int line = 0; | 46 | int line = 0; |
diff --git a/firmware/app.lds b/firmware/app.lds index 5816f40d35..135e521ef4 100644 --- a/firmware/app.lds +++ b/firmware/app.lds | |||
@@ -113,14 +113,10 @@ _pluginbuf = 0; | |||
113 | 113 | ||
114 | #define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE | 114 | #define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE |
115 | 115 | ||
116 | #ifdef IRIVER_H100_SERIES | 116 | #if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300) |
117 | #define IRAMSIZE 0x10000 | ||
118 | #define IRAMORIG 0x10000000 | ||
119 | #ifdef IRIVER_H100 | ||
120 | #define DRAMORIG 0x30000000 + STUBOFFSET | ||
121 | #else /* H120/H140 */ | ||
122 | #define DRAMORIG 0x31000000 + STUBOFFSET | 117 | #define DRAMORIG 0x31000000 + STUBOFFSET |
123 | #endif | 118 | #define IRAMORIG 0x10000000 |
119 | #define IRAMSIZE 0x10000 | ||
124 | #else | 120 | #else |
125 | #define DRAMORIG 0x09000000 + STUBOFFSET | 121 | #define DRAMORIG 0x09000000 + STUBOFFSET |
126 | #define IRAMORIG 0x0f000000 | 122 | #define IRAMORIG 0x0f000000 |
diff --git a/firmware/boot.lds b/firmware/boot.lds index fe5061c5f2..bdab6c9c97 100644 --- a/firmware/boot.lds +++ b/firmware/boot.lds | |||
@@ -16,7 +16,7 @@ INPUT(crt0.o) | |||
16 | 16 | ||
17 | #define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE | 17 | #define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE |
18 | 18 | ||
19 | #ifdef IRIVER_H100 | 19 | #ifdef IRIVER_H100_SERIES |
20 | #define DRAMORIG 0x31000000 | 20 | #define DRAMORIG 0x31000000 |
21 | #define IRAMORIG 0x10000000 | 21 | #define IRAMORIG 0x10000000 |
22 | #define IRAMSIZE 0x18000 | 22 | #define IRAMSIZE 0x18000 |
diff --git a/firmware/crt0.S b/firmware/crt0.S index 749039bc37..65577e02b9 100644 --- a/firmware/crt0.S +++ b/firmware/crt0.S | |||
@@ -190,7 +190,7 @@ irq_handler: | |||
190 | 190 | ||
191 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz | 191 | /* Set up the DRAM controller. The refresh is based on the 11.2896MHz |
192 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ | 192 | clock (5.6448MHz bus frequency). We haven't yet started the PLL */ |
193 | #ifdef IRIVER_H100 | 193 | #if MEM < 32 |
194 | move.w #0x8202,%d0 /* DCR - Synchronous, 64 cycle refresh */ | 194 | move.w #0x8202,%d0 /* DCR - Synchronous, 64 cycle refresh */ |
195 | #else | 195 | #else |
196 | move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */ | 196 | move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */ |
@@ -205,8 +205,8 @@ irq_handler: | |||
205 | In our case this means that we set the base address 16M ahead and | 205 | In our case this means that we set the base address 16M ahead and |
206 | use a 64M mask. | 206 | use a 64M mask. |
207 | */ | 207 | */ |
208 | #ifdef IRIVER_H100 | 208 | #if MEM < 32 |
209 | move.l #0x30002320,%d0 /* DACR0 - Base 0x30000000, Banks on 21 and up, | 209 | move.l #0x31002320,%d0 /* DACR0 - Base 0x31000000, Banks on 21 and up, |
210 | CAS latency 1, No refresh yet */ | 210 | CAS latency 1, No refresh yet */ |
211 | move.l %d0,(0x108,%a0) | 211 | move.l %d0,(0x108,%a0) |
212 | move.l #0x00fc0001,%d0 /* Size: 16M */ | 212 | move.l #0x00fc0001,%d0 /* Size: 16M */ |
@@ -224,10 +224,7 @@ irq_handler: | |||
224 | or.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a | 224 | or.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a |
225 | Precharge command */ | 225 | Precharge command */ |
226 | move.l #0xabcd1234,%d0 | 226 | move.l #0xabcd1234,%d0 |
227 | move.l %d0,0x30000000 /* Issue precharge command by writing somewhere | 227 | move.l %d0,0x31000000 /* Issue precharge command */ |
228 | in the SDRAM. (The 0x30000000 address is | ||
229 | mirrored on 32Mbyte devices so it works on | ||
230 | all models.) */ | ||
231 | 228 | ||
232 | /* Let it refresh */ | 229 | /* Let it refresh */ |
233 | move.l #1000,%d0 | 230 | move.l #1000,%d0 |
@@ -245,7 +242,7 @@ irq_handler: | |||
245 | or.l %d0,(0x108,%a0) | 242 | or.l %d0,(0x108,%a0) |
246 | 243 | ||
247 | move.l #0xabcd1234,%d0 | 244 | move.l #0xabcd1234,%d0 |
248 | move.l %d0,0x30000800 /* A12=1 means CASL=1 (a0 is not connected) */ | 245 | move.l %d0,0x31000800 /* A12=1 means CASL=1 (a0 is not connected) */ |
249 | 246 | ||
250 | move.l #0xffffffbf,%d0 | 247 | move.l #0xffffffbf,%d0 |
251 | and.l %d0,(0x108,%a0) /* Back to normal, the DRAM is now ready */ | 248 | and.l %d0,(0x108,%a0) /* Back to normal, the DRAM is now ready */ |
@@ -260,11 +257,7 @@ irq_handler: | |||
260 | movec.l %d0,%cacr | 257 | movec.l %d0,%cacr |
261 | 258 | ||
262 | /* Cache enabled in SDRAM only, buffered writes enabled */ | 259 | /* Cache enabled in SDRAM only, buffered writes enabled */ |
263 | #ifdef IRIVER_H100 | ||
264 | move.l #0x3003c020,%d0 | ||
265 | #else | ||
266 | move.l #0x3103c020,%d0 | 260 | move.l #0x3103c020,%d0 |
267 | #endif | ||
268 | movec.l %d0,%acr0 | 261 | movec.l %d0,%acr0 |
269 | moveq.l #0,%d0 | 262 | moveq.l #0,%d0 |
270 | movec.l %d0,%acr1 | 263 | movec.l %d0,%acr1 |