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authorAidan MacDonald <amachronic@protonmail.com>2022-11-29 22:33:56 +0000
committerAidan MacDonald <amachronic@protonmail.com>2022-12-01 12:11:46 -0500
commit52ca65806930fac06216a1d2ae62861b1da39a1f (patch)
tree61ff41d6ec60943ff87ef014d78c63eceb1f77c4
parentc9c340704faf923501afe24c74e21ca7f821ab3a (diff)
downloadrockbox-52ca65806930fac06216a1d2ae62861b1da39a1f.tar.gz
rockbox-52ca65806930fac06216a1d2ae62861b1da39a1f.zip
x1000: Add support for DS35x1GAxxx flash chips
This flash chip is found on some Surfans F20 units. For our purposes it's the same as the GD5F1GA4xExx so just #define an alias instead of adding a whole new chip struct. Change-Id: I2f4c4fbf1faf3a0c7a1503534430afacbddc426e
-rw-r--r--firmware/target/mips/ingenic_x1000/nand-x1000.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c
index 28e050fcef..a0efbb2cbe 100644
--- a/firmware/target/mips/ingenic_x1000/nand-x1000.c
+++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c
@@ -93,11 +93,15 @@ static const struct nand_chip chip_gd5f1gq4xexx = {
93 .cmd_program_load = NANDCMD_PROGRAM_LOAD_x4, 93 .cmd_program_load = NANDCMD_PROGRAM_LOAD_x4,
94}; 94};
95 95
96#define chip_ds35x1gaxxx chip_gd5f1gq4xexx
97
96const struct nand_chip_id supported_nand_chips[] = { 98const struct nand_chip_id supported_nand_chips[] = {
97 NAND_CHIP_ID(&chip_ato25d1ga, NAND_READID_ADDR, 0x9b, 0x12), 99 NAND_CHIP_ID(&chip_ato25d1ga, NAND_READID_ADDR, 0x9b, 0x12),
98 NAND_CHIP_ID(&chip_w25n01gvxx, NAND_READID_ADDR, 0xef, 0xaa, 0x21), 100 NAND_CHIP_ID(&chip_w25n01gvxx, NAND_READID_ADDR, 0xef, 0xaa, 0x21),
99 NAND_CHIP_ID(&chip_gd5f1gq4xexx, NAND_READID_ADDR, 0xc8, 0xd1), 101 NAND_CHIP_ID(&chip_gd5f1gq4xexx, NAND_READID_ADDR, 0xc8, 0xd1),
100 NAND_CHIP_ID(&chip_gd5f1gq4xexx, NAND_READID_ADDR, 0xc8, 0xc1), 102 NAND_CHIP_ID(&chip_gd5f1gq4xexx, NAND_READID_ADDR, 0xc8, 0xc1),
103 NAND_CHIP_ID(&chip_ds35x1gaxxx, NAND_READID_ADDR, 0xe5, 0x71), /* 3.3 V */
104 NAND_CHIP_ID(&chip_ds35x1gaxxx, NAND_READID_ADDR, 0xe5, 0x21), /* 1.8 V */
101}; 105};
102 106
103const size_t nr_supported_nand_chips = ARRAYLEN(supported_nand_chips); 107const size_t nr_supported_nand_chips = ARRAYLEN(supported_nand_chips);