Gigabeat S system setup changes. Unaligned loads/stores on. Mixed-endian support on. VIC on early.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17495 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 8 insertions, 4 deletions

diff --git a/firmware/target/arm/imx31/crt0.S b/firmware/target/arm/imx31/crt0.S
index 101c9799e2..f319adb668 100644
--- a/firmware/target/arm/imx31/crt0.S
+++ b/firmware/target/arm/imx31/crt0.S
@@ -200,25 +200,29 @@ remap_start:
     mrc     p15, 0, r0, c1, c0, 0
     bic     r0, r0, #((1 << 29) | /* AF by AP disabled */ \
                       (1 << 28) | /* TEX remap disabled */ \
-                      (1 << 24) | /* Vectored interrupt OFF */ \
-                      (1 << 23) | /* Sub AP bits enabled (compatible) */ \
-                      (1 << 22))  /* Unaligned access support disabled */
+                      (1 << 23))  /* Sub AP bits enabled (compatible) */
     bic     r0, r0, #((1 << 21) | /* All performance features enabled */ \
                       (1 << 15))  /* Loads to PC set T bit */
     bic     r0, r0, #((1 << 13))  /* Low vectors */
+    bic     r0, r0, #((1 <<  1))  /* Strict alignment disabled */
+    orr     r0, r0, #((1 << 24) | /* Vectored interrupt ON */ \
+                      (1 << 22))  /* Unaligned access support enabled */
     orr     r0, r0, #((1 << 14) | /* Round-robin replacement for I/D caches */ \
                       (1 << 12) | /* L1 I-cache enabled */ \
                       (1 << 11) | /* Program flow prediction enabled */ \
                       (1 <<  9) | /* ROM protection enabled */ \
                       (1 <<  8))  /* MMU protection enabled */
     orr     r0, r0, #((1 <<  2) | /* L1 D-cache enabled */ \
-                      (1 <<  1) | /* Strict alignment enabled */ \
                       (1 <<  0))  /* MMU enabled */
     mcr     p15, 0, r0, c1, c0, 0
     nop
     nop
     nop
     nop
+    nop
+    nop
+    nop
+    nop
     ldr     pc, L_post_remap
 L_post_remap:
     .word remap_end